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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3--- |4 define void @test_and_regs() { ret void }5 define void @test_and_imm() { ret void }6 7 define void @test_bfc() { ret void }8 define void @test_no_bfc_bad_mask() { ret void }9 10 define void @test_mvn() { ret void }11 define void @test_bic() { ret void }12 define void @test_orn() { ret void }13...14---15name: test_and_regs16legalized: true17regBankSelected: true18selected: false19registers:20 - { id: 0, class: gprb }21 - { id: 1, class: gprb }22 - { id: 2, class: gprb }23body: |24 bb.0:25 liveins: $r0, $r126 27 ; CHECK-LABEL: name: test_and_regs28 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r029 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r130 ; CHECK: [[t2ANDrr:%[0-9]+]]:rgpr = t2ANDrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg31 ; CHECK: $r0 = COPY [[t2ANDrr]]32 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r033 %0(s32) = COPY $r034 35 %1(s32) = COPY $r136 37 %2(s32) = G_AND %0, %138 39 $r0 = COPY %2(s32)40 41 BX_RET 14, $noreg, implicit $r042...43---44name: test_and_imm45legalized: true46regBankSelected: true47selected: false48registers:49 - { id: 0, class: gprb }50 - { id: 1, class: gprb }51 - { id: 2, class: gprb }52body: |53 bb.0:54 liveins: $r055 56 ; CHECK-LABEL: name: test_and_imm57 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r058 ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY]], 786444, 14 /* CC::al */, $noreg, $noreg59 ; CHECK: $r0 = COPY [[t2ANDri]]60 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r061 %0(s32) = COPY $r062 63 %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c64 %2(s32) = G_AND %0, %165 66 $r0 = COPY %2(s32)67 68 BX_RET 14, $noreg, implicit $r069...70---71name: test_bfc72legalized: true73regBankSelected: true74selected: false75registers:76 - { id: 0, class: gprb }77 - { id: 1, class: gprb }78 - { id: 2, class: gprb }79body: |80 bb.0:81 liveins: $r082 83 ; CHECK-LABEL: name: test_bfc84 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r085 ; CHECK: [[t2BFC:%[0-9]+]]:rgpr = t2BFC [[COPY]], -65529, 14 /* CC::al */, $noreg86 ; CHECK: $r0 = COPY [[t2BFC]]87 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r088 %0(s32) = COPY $r089 90 %1(s32) = G_CONSTANT i32 -65529 ; 0xFFFF000791 %2(s32) = G_AND %0, %192 93 $r0 = COPY %2(s32)94 95 BX_RET 14, $noreg, implicit $r096...97---98name: test_no_bfc_bad_mask99legalized: true100regBankSelected: true101selected: false102registers:103 - { id: 0, class: gprb }104 - { id: 1, class: gprb }105 - { id: 2, class: gprb }106body: |107 bb.0:108 liveins: $r0109 110 ; CHECK-LABEL: name: test_no_bfc_bad_mask111 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0112 ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY]], 786444, 14 /* CC::al */, $noreg, $noreg113 ; CHECK: $r0 = COPY [[t2ANDri]]114 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0115 %0(s32) = COPY $r0116 117 %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c118 %2(s32) = G_AND %0, %1119 120 $r0 = COPY %2(s32)121 122 BX_RET 14, $noreg, implicit $r0123...124---125name: test_mvn126legalized: true127regBankSelected: true128selected: false129registers:130 - { id: 0, class: gprb }131 - { id: 1, class: gprb }132 - { id: 2, class: gprb }133body: |134 bb.0:135 liveins: $r0136 137 ; CHECK-LABEL: name: test_mvn138 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0139 ; CHECK: [[t2MVNr:%[0-9]+]]:rgpr = t2MVNr [[COPY]], 14 /* CC::al */, $noreg, $noreg140 ; CHECK: $r0 = COPY [[t2MVNr]]141 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0142 %0(s32) = COPY $r0143 144 %1(s32) = G_CONSTANT i32 -1145 %2(s32) = G_XOR %0, %1146 147 $r0 = COPY %2(s32)148 149 BX_RET 14, $noreg, implicit $r0150...151---152name: test_bic153legalized: true154regBankSelected: true155selected: false156registers:157 - { id: 0, class: gprb }158 - { id: 1, class: gprb }159 - { id: 2, class: gprb }160 - { id: 3, class: gprb }161 - { id: 4, class: gprb }162body: |163 bb.0:164 liveins: $r0, $r1165 166 ; CHECK-LABEL: name: test_bic167 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0168 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1169 ; CHECK: [[t2BICrr:%[0-9]+]]:rgpr = t2BICrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg170 ; CHECK: $r0 = COPY [[t2BICrr]]171 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0172 %0(s32) = COPY $r0173 %1(s32) = COPY $r1174 175 %2(s32) = G_CONSTANT i32 -1176 %3(s32) = G_XOR %1, %2177 178 %4(s32) = G_AND %0, %3179 180 $r0 = COPY %4(s32)181 182 BX_RET 14, $noreg, implicit $r0183...184---185name: test_orn186legalized: true187regBankSelected: true188selected: false189registers:190 - { id: 0, class: gprb }191 - { id: 1, class: gprb }192 - { id: 2, class: gprb }193 - { id: 3, class: gprb }194 - { id: 4, class: gprb }195body: |196 bb.0:197 liveins: $r0, $r1198 199 ; CHECK-LABEL: name: test_orn200 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0201 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1202 ; CHECK: [[t2ORNrr:%[0-9]+]]:rgpr = t2ORNrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg203 ; CHECK: $r0 = COPY [[t2ORNrr]]204 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0205 %0(s32) = COPY $r0206 %1(s32) = COPY $r1207 208 %2(s32) = G_CONSTANT i32 -1209 %3(s32) = G_XOR %1, %2210 211 %4(s32) = G_OR %0, %3212 213 $r0 = COPY %4(s32)214 215 BX_RET 14, $noreg, implicit $r0216...217