94 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3--- |4 define void @test_ashr_rr() { ret void }5 6 define void @test_shl_ri() { ret void }7 define void @test_shl_ri_bad_imm() { ret void }8...9---10name: test_ashr_rr11legalized: true12regBankSelected: true13selected: false14registers:15 - { id: 0, class: gprb }16 - { id: 1, class: gprb }17 - { id: 2, class: gprb }18body: |19 bb.0:20 liveins: $r0, $r121 22 ; CHECK-LABEL: name: test_ashr_rr23 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r024 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r125 ; CHECK: [[t2ASRrr:%[0-9]+]]:rgpr = t2ASRrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg26 ; CHECK: $r0 = COPY [[t2ASRrr]]27 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r028 %0(s32) = COPY $r029 30 %1(s32) = COPY $r131 32 %2(s32) = G_ASHR %0, %133 34 $r0 = COPY %2(s32)35 36 BX_RET 14, $noreg, implicit $r037...38---39name: test_shl_ri40legalized: true41regBankSelected: true42selected: false43registers:44 - { id: 0, class: gprb }45 - { id: 1, class: gprb }46 - { id: 2, class: gprb }47body: |48 bb.0:49 liveins: $r050 51 ; CHECK-LABEL: name: test_shl_ri52 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r053 ; CHECK: [[t2LSLri:%[0-9]+]]:rgpr = t2LSLri [[COPY]], 31, 14 /* CC::al */, $noreg, $noreg54 ; CHECK: $r0 = COPY [[t2LSLri]]55 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r056 %0(s32) = COPY $r057 58 %1(s32) = G_CONSTANT i32 3159 %2(s32) = G_SHL %0, %160 61 $r0 = COPY %2(s32)62 63 BX_RET 14, $noreg, implicit $r064...65---66name: test_shl_ri_bad_imm67legalized: true68regBankSelected: true69selected: false70registers:71 - { id: 0, class: gprb }72 - { id: 1, class: gprb }73 - { id: 2, class: gprb }74body: |75 bb.0:76 liveins: $r077 78 ; CHECK-LABEL: name: test_shl_ri_bad_imm79 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r080 ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 32, 14 /* CC::al */, $noreg, $noreg81 ; CHECK: [[t2LSLrr:%[0-9]+]]:rgpr = t2LSLrr [[COPY]], [[t2MOVi]], 14 /* CC::al */, $noreg, $noreg82 ; CHECK: $r0 = COPY [[t2LSLrr]]83 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r084 %0(s32) = COPY $r085 86 %1(s32) = G_CONSTANT i32 3287 88 %2(s32) = G_SHL %0, %189 90 $r0 = COPY %2(s32)91 92 BX_RET 14, $noreg, implicit $r093...94