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1; RUN: llc -mtriple=arm -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 | grep -v "Verify generated machine code" | FileCheck %s2 3; REQUIRES: asserts4 5; CHECK: ModulePass Manager6; CHECK-NEXT: Pre-ISel Intrinsic Lowering7; CHECK-NEXT: FunctionPass Manager8; CHECK-NEXT: Expand large div/rem9; CHECK-NEXT: Expand fp10; CHECK-NEXT: Expand Atomic instructions11; CHECK-NEXT: Simplify the CFG12; CHECK-NEXT: Dominator Tree Construction13; CHECK-NEXT: Natural Loop Information14; CHECK-NEXT: MVE gather/scatter lowering15; CHECK-NEXT: MVE lane interleaving16; CHECK-NEXT: Module Verifier17; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)18; CHECK-NEXT: Canonicalize natural loops19; CHECK-NEXT: Scalar Evolution Analysis20; CHECK-NEXT: Loop Pass Manager21; CHECK-NEXT: Canonicalize Freeze Instructions in Loops22; CHECK-NEXT: Induction Variable Users23; CHECK-NEXT: Loop Strength Reduction24; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)25; CHECK-NEXT: Function Alias Analysis Results26; CHECK-NEXT: Merge contiguous icmps into a memcmp27; CHECK-NEXT: Natural Loop Information28; CHECK-NEXT: Lazy Branch Probability Analysis29; CHECK-NEXT: Lazy Block Frequency Analysis30; CHECK-NEXT: Expand memcmp() to load/stores31; CHECK-NEXT: Lower Garbage Collection Instructions32; CHECK-NEXT: Shadow Stack GC Lowering33; CHECK-NEXT: Remove unreachable blocks from the CFG34; CHECK-NEXT: Natural Loop Information35; CHECK-NEXT: Post-Dominator Tree Construction36; CHECK-NEXT: Branch Probability Analysis37; CHECK-NEXT: Block Frequency Analysis38; CHECK-NEXT: Constant Hoisting39; CHECK-NEXT: Replace intrinsics with calls to vector library40; CHECK-NEXT: Lazy Branch Probability Analysis41; CHECK-NEXT: Lazy Block Frequency Analysis42; CHECK-NEXT: Optimization Remark Emitter43; CHECK-NEXT: Partially inline calls to library functions44; CHECK-NEXT: Instrument function entry/exit with calls to e.g. mcount() (post inlining)45; CHECK-NEXT: Scalarize Masked Memory Intrinsics46; CHECK-NEXT: Expand reduction intrinsics47; CHECK-NEXT: Natural Loop Information48; CHECK-NEXT: Scalar Evolution Analysis49; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)50; CHECK-NEXT: Function Alias Analysis Results51; CHECK-NEXT: Transform functions to use DSP intrinsics52; CHECK-NEXT: Complex Deinterleaving Pass53; CHECK-NEXT: Interleaved Access Pass54; CHECK-NEXT: Type Promotion55; CHECK-NEXT: CodeGen Prepare56; CHECK-NEXT: Dominator Tree Construction57; CHECK-NEXT: Exception handling preparation58; CHECK-NEXT: Merge internal globals59; CHECK-NEXT: Natural Loop Information60; CHECK-NEXT: Scalar Evolution Analysis61; CHECK-NEXT: Lazy Branch Probability Analysis62; CHECK-NEXT: Lazy Block Frequency Analysis63; CHECK-NEXT: Optimization Remark Emitter64; CHECK-NEXT: Hardware Loop Insertion65; CHECK-NEXT: Loop Pass Manager66; CHECK-NEXT: Transform predicated vector loops to use MVE tail predication67; CHECK-NEXT: A No-Op Barrier Pass68; CHECK-NEXT: FunctionPass Manager69; CHECK-NEXT: Dominator Tree Construction70; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)71; CHECK-NEXT: Function Alias Analysis Results72; CHECK-NEXT: ObjC ARC contraction73; CHECK-NEXT: Prepare callbr74; CHECK-NEXT: Safe Stack instrumentation pass75; CHECK-NEXT: Insert stack protectors76; CHECK-NEXT: Module Verifier77; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)78; CHECK-NEXT: Function Alias Analysis Results79; CHECK-NEXT: Natural Loop Information80; CHECK-NEXT: Post-Dominator Tree Construction81; CHECK-NEXT: Branch Probability Analysis82; CHECK-NEXT: Assignment Tracking Analysis83; CHECK-NEXT: Lazy Branch Probability Analysis84; CHECK-NEXT: Lazy Block Frequency Analysis85; CHECK-NEXT: ARM Instruction Selection86; CHECK-NEXT: Finalize ISel and expand pseudo-instructions87; CHECK-NEXT: Lazy Machine Block Frequency Analysis88; CHECK-NEXT: Early Tail Duplication89; CHECK-NEXT: Optimize machine instruction PHIs90; CHECK-NEXT: Slot index numbering91; CHECK-NEXT: Merge disjoint stack slots92; CHECK-NEXT: Local Stack Slot Allocation93; CHECK-NEXT: Remove dead machine instructions94; CHECK-NEXT: MachineDominator Tree Construction95; CHECK-NEXT: Machine Natural Loop Construction96; CHECK-NEXT: Machine Block Frequency Analysis97; CHECK-NEXT: Early Machine Loop Invariant Code Motion98; CHECK-NEXT: MachineDominator Tree Construction99; CHECK-NEXT: Machine Block Frequency Analysis100; CHECK-NEXT: Machine Common Subexpression Elimination101; CHECK-NEXT: MachinePostDominator Tree Construction102; CHECK-NEXT: Machine Cycle Info Analysis103; CHECK-NEXT: Machine code sinking104; CHECK-NEXT: Peephole Optimizations105; CHECK-NEXT: Remove dead machine instructions106; CHECK-NEXT: MachineDominator Tree Construction107; CHECK-NEXT: Slot index numbering108; CHECK-NEXT: Live Interval Analysis109; CHECK-NEXT: Lazy Machine Block Frequency Analysis110; CHECK-NEXT: Machine Optimization Remark Emitter111; CHECK-NEXT: Modulo Software Pipelining112; CHECK-NEXT: MachineDominator Tree Construction113; CHECK-NEXT: Machine Natural Loop Construction114; CHECK-NEXT: MVE TailPred and VPT Optimisation Pass115; CHECK-NEXT: ARM MLA / MLS expansion pass116; CHECK-NEXT: MachineDominator Tree Construction117; CHECK-NEXT: ARM pre- register allocation load / store optimization pass118; CHECK-NEXT: ARM A15 S->D optimizer119; CHECK-NEXT: Detect Dead Lanes120; CHECK-NEXT: Init Undef Pass121; CHECK-NEXT: Process Implicit Definitions122; CHECK-NEXT: Remove unreachable machine basic blocks123; CHECK-NEXT: Live Variable Analysis124; CHECK-NEXT: MachineDominator Tree Construction125; CHECK-NEXT: Machine Natural Loop Construction126; CHECK-NEXT: Eliminate PHI nodes for register allocation127; CHECK-NEXT: Two-Address instruction pass128; CHECK-NEXT: Slot index numbering129; CHECK-NEXT: Live Interval Analysis130; CHECK-NEXT: Register Coalescer131; CHECK-NEXT: Rename Disconnected Subregister Components132; CHECK-NEXT: Machine Instruction Scheduler133; CHECK-NEXT: Machine Block Frequency Analysis134; CHECK-NEXT: Debug Variable Analysis135; CHECK-NEXT: Live Stack Slot Analysis136; CHECK-NEXT: Virtual Register Map137; CHECK-NEXT: Live Register Matrix138; CHECK-NEXT: Bundle Machine CFG Edges139; CHECK-NEXT: Spill Code Placement Analysis140; CHECK-NEXT: Lazy Machine Block Frequency Analysis141; CHECK-NEXT: Machine Optimization Remark Emitter142; CHECK-NEXT: Greedy Register Allocator143; CHECK-NEXT: Virtual Register Rewriter144; CHECK-NEXT: Register Allocation Pass Scoring145; CHECK-NEXT: Stack Slot Coloring146; CHECK-NEXT: Machine Copy Propagation Pass147; CHECK-NEXT: Machine Loop Invariant Code Motion148; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis149; CHECK-NEXT: Fixup Statepoint Caller Saved150; CHECK-NEXT: PostRA Machine Sink151; CHECK-NEXT: Machine Block Frequency Analysis152; CHECK-NEXT: MachineDominator Tree Construction153; CHECK-NEXT: MachinePostDominator Tree Construction154; CHECK-NEXT: Lazy Machine Block Frequency Analysis155; CHECK-NEXT: Machine Optimization Remark Emitter156; CHECK-NEXT: Shrink Wrapping analysis157; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization158; CHECK-NEXT: Machine Late Instructions Cleanup Pass159; CHECK-NEXT: Control Flow Optimizer160; CHECK-NEXT: Lazy Machine Block Frequency Analysis161; CHECK-NEXT: Tail Duplication162; CHECK-NEXT: Machine Copy Propagation Pass163; CHECK-NEXT: Post-RA pseudo instruction expansion pass164; CHECK-NEXT: ARM load / store optimization pass165; CHECK-NEXT: Reaching Definitions Analysis166; CHECK-NEXT: ARM Execution Domain Fix167; CHECK-NEXT: BreakFalseDeps168; CHECK-NEXT: ARM pseudo instruction expansion pass169; CHECK-NEXT: Insert KCFI indirect call checks170; CHECK-NEXT: Thumb2 instruction size reduce pass171; CHECK-NEXT: MachineDominator Tree Construction172; CHECK-NEXT: Machine Natural Loop Construction173; CHECK-NEXT: Machine Block Frequency Analysis174; CHECK-NEXT: If Converter175; CHECK-NEXT: Thumb IT blocks insertion pass176; CHECK-NEXT: MachineDominator Tree Construction177; CHECK-NEXT: Machine Natural Loop Construction178; CHECK-NEXT: PostRA Machine Instruction Scheduler179; CHECK-NEXT: Post RA top-down list latency scheduler180; CHECK-NEXT: MVE VPT block insertion pass181; CHECK-NEXT: ARM Indirect Thunks182; CHECK-NEXT: ARM sls hardening pass183; CHECK-NEXT: Analyze Machine Code For Garbage Collection184; CHECK-NEXT: MachineDominator Tree Construction185; CHECK-NEXT: Machine Natural Loop Construction186; CHECK-NEXT: Machine Block Frequency Analysis187; CHECK-NEXT: MachinePostDominator Tree Construction188; CHECK-NEXT: Branch Probability Basic Block Placement189; CHECK-NEXT: Insert fentry calls190; CHECK-NEXT: Insert XRay ops191; CHECK-NEXT: Implement the 'patchable-function' attribute192; CHECK-NEXT: Thumb2 instruction size reduce pass193; CHECK-NEXT: Unpack machine instruction bundles194; CHECK-NEXT: MachineDominator Tree Construction195; CHECK-NEXT: Machine Natural Loop Construction196; CHECK-NEXT: ARM block placement197; CHECK-NEXT: optimise barriers pass198; CHECK-NEXT: Contiguously Lay Out Funclets199; CHECK-NEXT: Remove Loads Into Fake Uses200; CHECK-NEXT: StackMap Liveness Analysis201; CHECK-NEXT: Live DEBUG_VALUE analysis202; CHECK-NEXT: Machine Sanitizer Binary Metadata203; CHECK-NEXT: Machine Outliner204; CHECK-NEXT: FunctionPass Manager205; CHECK-NEXT: Lazy Machine Block Frequency Analysis206; CHECK-NEXT: Machine Optimization Remark Emitter207; CHECK-NEXT: Stack Frame Layout Analysis208; CHECK-NEXT: Reaching Definitions Analysis209; CHECK-NEXT: ARM fix for Cortex-A57 AES Erratum 1742098210; CHECK-NEXT: ARM Branch Targets211; CHECK-NEXT: MachineDominator Tree Construction212; CHECK-NEXT: ARM constant island placement and branch shortening pass213; CHECK-NEXT: MachineDominator Tree Construction214; CHECK-NEXT: Machine Natural Loop Construction215; CHECK-NEXT: Reaching Definitions Analysis216; CHECK-NEXT: ARM Low Overhead Loops pass217; CHECK-NEXT: Lazy Machine Block Frequency Analysis218; CHECK-NEXT: Machine Optimization Remark Emitter219; CHECK-NEXT: ARM Assembly Printer220; CHECK-NEXT: Free MachineFunction221