414 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -arm-parallel-dsp -dce -mtriple=armv7-a -S %s -o - | FileCheck %s3 4define i32 @single_block(ptr %a, ptr %b, i32 %acc) {5; CHECK-LABEL: @single_block(6; CHECK-NEXT: entry:7; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A:%.*]], align 28; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[B:%.*]], align 29; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.arm.smlad(i32 [[TMP1]], i32 [[TMP3]], i32 [[ACC:%.*]])10; CHECK-NEXT: ret i32 [[TMP4]]11;12entry:13 %ld.a.0 = load i16, ptr %a14 %sext.a.0 = sext i16 %ld.a.0 to i3215 %ld.b.0 = load i16, ptr %b16 %sext.b.0 = sext i16 %ld.b.0 to i3217 %mul.0 = mul i32 %sext.a.0, %sext.b.018 %addr.a.1 = getelementptr i16, ptr %a, i32 119 %addr.b.1 = getelementptr i16, ptr %b, i32 120 %ld.a.1 = load i16, ptr %addr.a.121 %sext.a.1 = sext i16 %ld.a.1 to i3222 %ld.b.1 = load i16, ptr %addr.b.123 %sext.b.1 = sext i16 %ld.b.1 to i3224 %mul.1 = mul i32 %sext.a.1, %sext.b.125 %add = add i32 %mul.0, %mul.126 %res = add i32 %add, %acc27 ret i32 %res28}29 30define i64 @single_block_64(ptr %a, ptr %b, i64 %acc) {31; CHECK-LABEL: @single_block_64(32; CHECK-NEXT: entry:33; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A:%.*]], align 234; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[B:%.*]], align 235; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.arm.smlald(i32 [[TMP1]], i32 [[TMP3]], i64 [[ACC:%.*]])36; CHECK-NEXT: ret i64 [[TMP4]]37;38entry:39 %ld.a.0 = load i16, ptr %a40 %sext.a.0 = sext i16 %ld.a.0 to i3241 %ld.b.0 = load i16, ptr %b42 %sext.b.0 = sext i16 %ld.b.0 to i3243 %mul.0 = mul i32 %sext.a.0, %sext.b.044 %addr.a.1 = getelementptr i16, ptr %a, i32 145 %addr.b.1 = getelementptr i16, ptr %b, i32 146 %ld.a.1 = load i16, ptr %addr.a.147 %sext.a.1 = sext i16 %ld.a.1 to i3248 %ld.b.1 = load i16, ptr %addr.b.149 %sext.b.1 = sext i16 %ld.b.1 to i3250 %mul.1 = mul i32 %sext.a.1, %sext.b.151 %sext.mul.0 = sext i32 %mul.0 to i6452 %sext.mul.1 = sext i32 %mul.1 to i6453 %add = add i64 %sext.mul.0, %sext.mul.154 %res = add i64 %add, %acc55 ret i64 %res56}57 58define i32 @multi_block(ptr %a, ptr %b, i32 %acc) {59; CHECK-LABEL: @multi_block(60; CHECK-NEXT: entry:61; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A:%.*]], align 262; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[B:%.*]], align 263; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.arm.smlad(i32 [[TMP1]], i32 [[TMP3]], i32 0)64; CHECK-NEXT: br label [[BB_1:%.*]]65; CHECK: bb.1:66; CHECK-NEXT: [[RES:%.*]] = add i32 [[TMP4]], [[ACC:%.*]]67; CHECK-NEXT: ret i32 [[RES]]68;69entry:70 %ld.a.0 = load i16, ptr %a71 %sext.a.0 = sext i16 %ld.a.0 to i3272 %ld.b.0 = load i16, ptr %b73 %sext.b.0 = sext i16 %ld.b.0 to i3274 %mul.0 = mul i32 %sext.a.0, %sext.b.075 %addr.a.1 = getelementptr i16, ptr %a, i32 176 %addr.b.1 = getelementptr i16, ptr %b, i32 177 %ld.a.1 = load i16, ptr %addr.a.178 %sext.a.1 = sext i16 %ld.a.1 to i3279 %ld.b.1 = load i16, ptr %addr.b.180 %sext.b.1 = sext i16 %ld.b.1 to i3281 %mul.1 = mul i32 %sext.a.1, %sext.b.182 %add = add i32 %mul.0, %mul.183 br label %bb.184 85bb.1:86 %res = add i32 %add, %acc87 ret i32 %res88}89 90define i64 @multi_block_64(ptr %a, ptr %b, i64 %acc) {91; CHECK-LABEL: @multi_block_64(92; CHECK-NEXT: entry:93; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A:%.*]], align 294; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[B:%.*]], align 295; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.arm.smlald(i32 [[TMP1]], i32 [[TMP3]], i64 0)96; CHECK-NEXT: br label [[BB_1:%.*]]97; CHECK: bb.1:98; CHECK-NEXT: [[RES:%.*]] = add i64 [[TMP4]], [[ACC:%.*]]99; CHECK-NEXT: ret i64 [[RES]]100;101entry:102 %ld.a.0 = load i16, ptr %a103 %sext.a.0 = sext i16 %ld.a.0 to i32104 %ld.b.0 = load i16, ptr %b105 %sext.b.0 = sext i16 %ld.b.0 to i32106 %mul.0 = mul i32 %sext.a.0, %sext.b.0107 %addr.a.1 = getelementptr i16, ptr %a, i32 1108 %addr.b.1 = getelementptr i16, ptr %b, i32 1109 %ld.a.1 = load i16, ptr %addr.a.1110 %sext.a.1 = sext i16 %ld.a.1 to i32111 %ld.b.1 = load i16, ptr %addr.b.1112 %sext.b.1 = sext i16 %ld.b.1 to i32113 %mul.1 = mul i32 %sext.a.1, %sext.b.1114 %sext.mul.0 = sext i32 %mul.0 to i64115 %sext.mul.1 = sext i32 %mul.1 to i64116 %add = add i64 %sext.mul.0, %sext.mul.1117 br label %bb.1118 119bb.1:120 %res = add i64 %add, %acc121 ret i64 %res122}123 124define i32 @multi_block_1(ptr %a, ptr %b, i32 %acc) {125; CHECK-LABEL: @multi_block_1(126; CHECK-NEXT: entry:127; CHECK-NEXT: [[LD_A_0:%.*]] = load i16, ptr [[A:%.*]], align 2128; CHECK-NEXT: [[SEXT_A_0:%.*]] = sext i16 [[LD_A_0]] to i32129; CHECK-NEXT: [[LD_B_0:%.*]] = load i16, ptr [[B:%.*]], align 2130; CHECK-NEXT: [[SEXT_B_0:%.*]] = sext i16 [[LD_B_0]] to i32131; CHECK-NEXT: [[MUL_0:%.*]] = mul i32 [[SEXT_A_0]], [[SEXT_B_0]]132; CHECK-NEXT: br label [[BB_1:%.*]]133; CHECK: bb.1:134; CHECK-NEXT: [[ADDR_A_1:%.*]] = getelementptr i16, ptr [[A]], i32 1135; CHECK-NEXT: [[ADDR_B_1:%.*]] = getelementptr i16, ptr [[B]], i32 1136; CHECK-NEXT: [[LD_A_1:%.*]] = load i16, ptr [[ADDR_A_1]], align 2137; CHECK-NEXT: [[SEXT_A_1:%.*]] = sext i16 [[LD_A_1]] to i32138; CHECK-NEXT: [[LD_B_1:%.*]] = load i16, ptr [[ADDR_B_1]], align 2139; CHECK-NEXT: [[SEXT_B_1:%.*]] = sext i16 [[LD_B_1]] to i32140; CHECK-NEXT: [[MUL_1:%.*]] = mul i32 [[SEXT_A_1]], [[SEXT_B_1]]141; CHECK-NEXT: [[ADD:%.*]] = add i32 [[MUL_0]], [[MUL_1]]142; CHECK-NEXT: [[RES:%.*]] = add i32 [[ADD]], [[ACC:%.*]]143; CHECK-NEXT: ret i32 [[RES]]144;145entry:146 %ld.a.0 = load i16, ptr %a147 %sext.a.0 = sext i16 %ld.a.0 to i32148 %ld.b.0 = load i16, ptr %b149 %sext.b.0 = sext i16 %ld.b.0 to i32150 %mul.0 = mul i32 %sext.a.0, %sext.b.0151 br label %bb.1152 153bb.1:154 %addr.a.1 = getelementptr i16, ptr %a, i32 1155 %addr.b.1 = getelementptr i16, ptr %b, i32 1156 %ld.a.1 = load i16, ptr %addr.a.1157 %sext.a.1 = sext i16 %ld.a.1 to i32158 %ld.b.1 = load i16, ptr %addr.b.1159 %sext.b.1 = sext i16 %ld.b.1 to i32160 %mul.1 = mul i32 %sext.a.1, %sext.b.1161 %add = add i32 %mul.0, %mul.1162 %res = add i32 %add, %acc163 ret i32 %res164}165 166; TODO: Four smlads should be generated here, but mul.0 and mul.3 remain as167; scalars.168define i32 @num_load_limit(ptr %a, ptr %b, i32 %acc) {169; CHECK-LABEL: @num_load_limit(170; CHECK-NEXT: entry:171; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A:%.*]], align 2172; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16173; CHECK-NEXT: [[TMP3:%.*]] = sext i16 [[TMP2]] to i32174; CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP1]], 16175; CHECK-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16176; CHECK-NEXT: [[TMP6:%.*]] = sext i16 [[TMP5]] to i32177; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[B:%.*]], align 2178; CHECK-NEXT: [[TMP9:%.*]] = trunc i32 [[TMP8]] to i16179; CHECK-NEXT: [[TMP10:%.*]] = sext i16 [[TMP9]] to i32180; CHECK-NEXT: [[MUL_0:%.*]] = mul i32 [[TMP3]], [[TMP10]]181; CHECK-NEXT: [[ADDR_B_3:%.*]] = getelementptr i16, ptr [[B]], i32 3182; CHECK-NEXT: [[LD_B_3:%.*]] = load i16, ptr [[ADDR_B_3]], align 2183; CHECK-NEXT: [[SEXT_B_3:%.*]] = sext i16 [[LD_B_3]] to i32184; CHECK-NEXT: [[MUL_3:%.*]] = mul i32 [[TMP6]], [[SEXT_B_3]]185; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[MUL_3]], [[ACC:%.*]]186; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[MUL_0]], [[TMP11]]187; CHECK-NEXT: [[TMP13:%.*]] = call i32 @llvm.arm.smlad(i32 [[TMP1]], i32 [[TMP8]], i32 [[TMP12]])188; CHECK-NEXT: [[ADDR_A_4:%.*]] = getelementptr i16, ptr [[A]], i32 4189; CHECK-NEXT: [[ADDR_B_4:%.*]] = getelementptr i16, ptr [[B]], i32 4190; CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[ADDR_A_4]], align 2191; CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[ADDR_B_4]], align 2192; CHECK-NEXT: [[TMP18:%.*]] = call i32 @llvm.arm.smlad(i32 [[TMP15]], i32 [[TMP17]], i32 [[TMP13]])193; CHECK-NEXT: [[ADDR_A_6:%.*]] = getelementptr i16, ptr [[A]], i32 6194; CHECK-NEXT: [[ADDR_B_6:%.*]] = getelementptr i16, ptr [[B]], i32 6195; CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[ADDR_A_6]], align 2196; CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[ADDR_B_6]], align 2197; CHECK-NEXT: [[TMP23:%.*]] = call i32 @llvm.arm.smlad(i32 [[TMP20]], i32 [[TMP22]], i32 [[TMP18]])198; CHECK-NEXT: ret i32 [[TMP23]]199;200entry:201 %ld.a.0 = load i16, ptr %a202 %sext.a.0 = sext i16 %ld.a.0 to i32203 %ld.b.0 = load i16, ptr %b204 %sext.b.0 = sext i16 %ld.b.0 to i32205 %mul.0 = mul i32 %sext.a.0, %sext.b.0206 %addr.a.1 = getelementptr i16, ptr %a, i32 1207 %addr.b.1 = getelementptr i16, ptr %b, i32 1208 %ld.a.1 = load i16, ptr %addr.a.1209 %sext.a.1 = sext i16 %ld.a.1 to i32210 %ld.b.1 = load i16, ptr %addr.b.1211 %sext.b.1 = sext i16 %ld.b.1 to i32212 %mul.1 = mul i32 %sext.a.1, %sext.b.1213 %add.0 = add i32 %mul.0, %mul.1214 215 %addr.a.2 = getelementptr i16, ptr %a, i32 2216 %addr.b.2 = getelementptr i16, ptr %b, i32 2217 %ld.a.2 = load i16, ptr %addr.a.2218 %sext.a.2 = sext i16 %ld.a.2 to i32219 %ld.b.2 = load i16, ptr %addr.b.2220 %sext.b.2 = sext i16 %ld.b.2 to i32221 %mul.2 = mul i32 %sext.a.0, %sext.b.0222 %addr.a.3 = getelementptr i16, ptr %a, i32 3223 %addr.b.3 = getelementptr i16, ptr %b, i32 3224 %ld.a.3 = load i16, ptr %addr.a.3225 %sext.a.3 = sext i16 %ld.a.3 to i32226 %ld.b.3 = load i16, ptr %addr.b.3227 %sext.b.3 = sext i16 %ld.b.3 to i32228 %mul.3 = mul i32 %sext.a.1, %sext.b.3229 %add.3 = add i32 %mul.2, %mul.3230 231 %addr.a.4 = getelementptr i16, ptr %a, i32 4232 %addr.b.4 = getelementptr i16, ptr %b, i32 4233 %ld.a.4 = load i16, ptr %addr.a.4234 %sext.a.4 = sext i16 %ld.a.4 to i32235 %ld.b.4 = load i16, ptr %addr.b.4236 %sext.b.4 = sext i16 %ld.b.4 to i32237 %mul.4 = mul i32 %sext.a.4, %sext.b.4238 %addr.a.5 = getelementptr i16, ptr %a, i32 5239 %addr.b.5 = getelementptr i16, ptr %b, i32 5240 %ld.a.5 = load i16, ptr %addr.a.5241 %sext.a.5 = sext i16 %ld.a.5 to i32242 %ld.b.5 = load i16, ptr %addr.b.5243 %sext.b.5 = sext i16 %ld.b.5 to i32244 %mul.5 = mul i32 %sext.a.5, %sext.b.5245 %add.5 = add i32 %mul.4, %mul.5246 247 %addr.a.6 = getelementptr i16, ptr %a, i32 6248 %addr.b.6 = getelementptr i16, ptr %b, i32 6249 %ld.a.6 = load i16, ptr %addr.a.6250 %sext.a.6 = sext i16 %ld.a.6 to i32251 %ld.b.6 = load i16, ptr %addr.b.6252 %sext.b.6 = sext i16 %ld.b.6 to i32253 %mul.6 = mul i32 %sext.a.6, %sext.b.6254 %addr.a.7 = getelementptr i16, ptr %a, i32 7255 %addr.b.7 = getelementptr i16, ptr %b, i32 7256 %ld.a.7 = load i16, ptr %addr.a.7257 %sext.a.7 = sext i16 %ld.a.7 to i32258 %ld.b.7 = load i16, ptr %addr.b.7259 %sext.b.7 = sext i16 %ld.b.7 to i32260 %mul.7 = mul i32 %sext.a.7, %sext.b.7261 %add.7 = add i32 %mul.6, %mul.7262 263 %add.10 = add i32 %add.7, %add.5264 %add.11 = add i32 %add.3, %add.0265 %add.12 = add i32 %add.10, %add.11266 %res = add i32 %add.12, %acc267 ret i32 %res268}269 270define i32 @too_many_loads(ptr %a, ptr %b, i32 %acc) {271; CHECK-LABEL: @too_many_loads(272; CHECK-NEXT: entry:273; CHECK-NEXT: [[LD_A_0:%.*]] = load i16, ptr [[A:%.*]], align 2274; CHECK-NEXT: [[SEXT_A_0:%.*]] = sext i16 [[LD_A_0]] to i32275; CHECK-NEXT: [[LD_B_0:%.*]] = load i16, ptr [[B:%.*]], align 2276; CHECK-NEXT: [[SEXT_B_0:%.*]] = sext i16 [[LD_B_0]] to i32277; CHECK-NEXT: [[MUL_0:%.*]] = mul i32 [[SEXT_A_0]], [[SEXT_B_0]]278; CHECK-NEXT: [[ADDR_A_1:%.*]] = getelementptr i16, ptr [[A]], i32 1279; CHECK-NEXT: [[ADDR_B_1:%.*]] = getelementptr i16, ptr [[B]], i32 1280; CHECK-NEXT: [[LD_A_1:%.*]] = load i16, ptr [[ADDR_A_1]], align 2281; CHECK-NEXT: [[SEXT_A_1:%.*]] = sext i16 [[LD_A_1]] to i32282; CHECK-NEXT: [[LD_B_1:%.*]] = load i16, ptr [[ADDR_B_1]], align 2283; CHECK-NEXT: [[SEXT_B_1:%.*]] = sext i16 [[LD_B_1]] to i32284; CHECK-NEXT: [[MUL_1:%.*]] = mul i32 [[SEXT_A_1]], [[SEXT_B_1]]285; CHECK-NEXT: [[ADD_0:%.*]] = add i32 [[MUL_0]], [[MUL_1]]286; CHECK-NEXT: [[MUL_2:%.*]] = mul i32 [[SEXT_A_0]], [[SEXT_B_0]]287; CHECK-NEXT: [[ADDR_B_3:%.*]] = getelementptr i16, ptr [[B]], i32 3288; CHECK-NEXT: [[LD_B_3:%.*]] = load i16, ptr [[ADDR_B_3]], align 2289; CHECK-NEXT: [[SEXT_B_3:%.*]] = sext i16 [[LD_B_3]] to i32290; CHECK-NEXT: [[MUL_3:%.*]] = mul i32 [[SEXT_A_1]], [[SEXT_B_3]]291; CHECK-NEXT: [[ADD_3:%.*]] = add i32 [[MUL_2]], [[MUL_3]]292; CHECK-NEXT: [[ADDR_A_4:%.*]] = getelementptr i16, ptr [[A]], i32 4293; CHECK-NEXT: [[ADDR_B_4:%.*]] = getelementptr i16, ptr [[B]], i32 4294; CHECK-NEXT: [[LD_A_4:%.*]] = load i16, ptr [[ADDR_A_4]], align 2295; CHECK-NEXT: [[SEXT_A_4:%.*]] = sext i16 [[LD_A_4]] to i32296; CHECK-NEXT: [[LD_B_4:%.*]] = load i16, ptr [[ADDR_B_4]], align 2297; CHECK-NEXT: [[SEXT_B_4:%.*]] = sext i16 [[LD_B_4]] to i32298; CHECK-NEXT: [[MUL_4:%.*]] = mul i32 [[SEXT_A_4]], [[SEXT_B_4]]299; CHECK-NEXT: [[ADDR_A_5:%.*]] = getelementptr i16, ptr [[A]], i32 5300; CHECK-NEXT: [[ADDR_B_5:%.*]] = getelementptr i16, ptr [[B]], i32 5301; CHECK-NEXT: [[LD_A_5:%.*]] = load i16, ptr [[ADDR_A_5]], align 2302; CHECK-NEXT: [[SEXT_A_5:%.*]] = sext i16 [[LD_A_5]] to i32303; CHECK-NEXT: [[LD_B_5:%.*]] = load i16, ptr [[ADDR_B_5]], align 2304; CHECK-NEXT: [[SEXT_B_5:%.*]] = sext i16 [[LD_B_5]] to i32305; CHECK-NEXT: [[MUL_5:%.*]] = mul i32 [[SEXT_A_5]], [[SEXT_B_5]]306; CHECK-NEXT: [[ADD_5:%.*]] = add i32 [[MUL_4]], [[MUL_5]]307; CHECK-NEXT: [[ADDR_A_6:%.*]] = getelementptr i16, ptr [[A]], i32 6308; CHECK-NEXT: [[ADDR_B_6:%.*]] = getelementptr i16, ptr [[B]], i32 6309; CHECK-NEXT: [[LD_A_6:%.*]] = load i16, ptr [[ADDR_A_6]], align 2310; CHECK-NEXT: [[SEXT_A_6:%.*]] = sext i16 [[LD_A_6]] to i32311; CHECK-NEXT: [[LD_B_6:%.*]] = load i16, ptr [[ADDR_B_6]], align 2312; CHECK-NEXT: [[SEXT_B_6:%.*]] = sext i16 [[LD_B_6]] to i32313; CHECK-NEXT: [[MUL_6:%.*]] = mul i32 [[SEXT_A_6]], [[SEXT_B_6]]314; CHECK-NEXT: [[ADDR_A_7:%.*]] = getelementptr i16, ptr [[A]], i32 7315; CHECK-NEXT: [[ADDR_B_7:%.*]] = getelementptr i16, ptr [[B]], i32 7316; CHECK-NEXT: [[LD_A_7:%.*]] = load i16, ptr [[ADDR_A_7]], align 2317; CHECK-NEXT: [[SEXT_A_7:%.*]] = sext i16 [[LD_A_7]] to i32318; CHECK-NEXT: [[LD_B_7:%.*]] = load i16, ptr [[ADDR_B_7]], align 2319; CHECK-NEXT: [[SEXT_B_7:%.*]] = sext i16 [[LD_B_7]] to i32320; CHECK-NEXT: [[MUL_7:%.*]] = mul i32 [[SEXT_A_7]], [[SEXT_B_7]]321; CHECK-NEXT: [[ADD_7:%.*]] = add i32 [[MUL_6]], [[MUL_7]]322; CHECK-NEXT: [[ADDR_A_8:%.*]] = getelementptr i16, ptr [[A]], i32 7323; CHECK-NEXT: [[ADDR_B_8:%.*]] = getelementptr i16, ptr [[B]], i32 7324; CHECK-NEXT: [[LD_A_8:%.*]] = load i16, ptr [[ADDR_A_8]], align 2325; CHECK-NEXT: [[SEXT_A_8:%.*]] = sext i16 [[LD_A_8]] to i32326; CHECK-NEXT: [[LD_B_8:%.*]] = load i16, ptr [[ADDR_B_8]], align 2327; CHECK-NEXT: [[SEXT_B_8:%.*]] = sext i16 [[LD_B_8]] to i32328; CHECK-NEXT: [[MUL_8:%.*]] = mul i32 [[SEXT_A_8]], [[SEXT_B_8]]329; CHECK-NEXT: [[ADD_10:%.*]] = add i32 [[ADD_7]], [[ADD_5]]330; CHECK-NEXT: [[ADD_11:%.*]] = add i32 [[ADD_3]], [[ADD_0]]331; CHECK-NEXT: [[ADD_12:%.*]] = add i32 [[ADD_10]], [[ADD_11]]332; CHECK-NEXT: [[ADD_13:%.*]] = add i32 [[ADD_12]], [[ACC:%.*]]333; CHECK-NEXT: [[RES:%.*]] = add i32 [[ADD_13]], [[MUL_8]]334; CHECK-NEXT: ret i32 [[RES]]335;336entry:337 %ld.a.0 = load i16, ptr %a338 %sext.a.0 = sext i16 %ld.a.0 to i32339 %ld.b.0 = load i16, ptr %b340 %sext.b.0 = sext i16 %ld.b.0 to i32341 %mul.0 = mul i32 %sext.a.0, %sext.b.0342 %addr.a.1 = getelementptr i16, ptr %a, i32 1343 %addr.b.1 = getelementptr i16, ptr %b, i32 1344 %ld.a.1 = load i16, ptr %addr.a.1345 %sext.a.1 = sext i16 %ld.a.1 to i32346 %ld.b.1 = load i16, ptr %addr.b.1347 %sext.b.1 = sext i16 %ld.b.1 to i32348 %mul.1 = mul i32 %sext.a.1, %sext.b.1349 %add.0 = add i32 %mul.0, %mul.1350 351 %addr.a.2 = getelementptr i16, ptr %a, i32 2352 %addr.b.2 = getelementptr i16, ptr %b, i32 2353 %ld.a.2 = load i16, ptr %addr.a.2354 %sext.a.2 = sext i16 %ld.a.2 to i32355 %ld.b.2 = load i16, ptr %addr.b.2356 %sext.b.2 = sext i16 %ld.b.2 to i32357 %mul.2 = mul i32 %sext.a.0, %sext.b.0358 %addr.a.3 = getelementptr i16, ptr %a, i32 3359 %addr.b.3 = getelementptr i16, ptr %b, i32 3360 %ld.a.3 = load i16, ptr %addr.a.3361 %sext.a.3 = sext i16 %ld.a.3 to i32362 %ld.b.3 = load i16, ptr %addr.b.3363 %sext.b.3 = sext i16 %ld.b.3 to i32364 %mul.3 = mul i32 %sext.a.1, %sext.b.3365 %add.3 = add i32 %mul.2, %mul.3366 367 %addr.a.4 = getelementptr i16, ptr %a, i32 4368 %addr.b.4 = getelementptr i16, ptr %b, i32 4369 %ld.a.4 = load i16, ptr %addr.a.4370 %sext.a.4 = sext i16 %ld.a.4 to i32371 %ld.b.4 = load i16, ptr %addr.b.4372 %sext.b.4 = sext i16 %ld.b.4 to i32373 %mul.4 = mul i32 %sext.a.4, %sext.b.4374 %addr.a.5 = getelementptr i16, ptr %a, i32 5375 %addr.b.5 = getelementptr i16, ptr %b, i32 5376 %ld.a.5 = load i16, ptr %addr.a.5377 %sext.a.5 = sext i16 %ld.a.5 to i32378 %ld.b.5 = load i16, ptr %addr.b.5379 %sext.b.5 = sext i16 %ld.b.5 to i32380 %mul.5 = mul i32 %sext.a.5, %sext.b.5381 %add.5 = add i32 %mul.4, %mul.5382 383 %addr.a.6 = getelementptr i16, ptr %a, i32 6384 %addr.b.6 = getelementptr i16, ptr %b, i32 6385 %ld.a.6 = load i16, ptr %addr.a.6386 %sext.a.6 = sext i16 %ld.a.6 to i32387 %ld.b.6 = load i16, ptr %addr.b.6388 %sext.b.6 = sext i16 %ld.b.6 to i32389 %mul.6 = mul i32 %sext.a.6, %sext.b.6390 %addr.a.7 = getelementptr i16, ptr %a, i32 7391 %addr.b.7 = getelementptr i16, ptr %b, i32 7392 %ld.a.7 = load i16, ptr %addr.a.7393 %sext.a.7 = sext i16 %ld.a.7 to i32394 %ld.b.7 = load i16, ptr %addr.b.7395 %sext.b.7 = sext i16 %ld.b.7 to i32396 %mul.7 = mul i32 %sext.a.7, %sext.b.7397 %add.7 = add i32 %mul.6, %mul.7398 399 %addr.a.8 = getelementptr i16, ptr %a, i32 7400 %addr.b.8 = getelementptr i16, ptr %b, i32 7401 %ld.a.8 = load i16, ptr %addr.a.8402 %sext.a.8 = sext i16 %ld.a.8 to i32403 %ld.b.8 = load i16, ptr %addr.b.8404 %sext.b.8 = sext i16 %ld.b.8 to i32405 %mul.8 = mul i32 %sext.a.8, %sext.b.8406 407 %add.10 = add i32 %add.7, %add.5408 %add.11 = add i32 %add.3, %add.0409 %add.12 = add i32 %add.10, %add.11410 %add.13 = add i32 %add.12, %acc411 %res = add i32 %add.13, %mul.8412 ret i32 %res413}414