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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py3; RUN: llc -mtriple=thumbv7em -mcpu=cortex-m4 -O3 %s -o - | FileCheck %s --check-prefix=CHECK-LLC4; RUN: opt -S -mtriple=armv7-a -arm-parallel-dsp -dce %s -o - | FileCheck %s --check-prefix=CHECK-OPT5 6define dso_local arm_aapcscc void @complex_dot_prod(ptr nocapture readonly %pSrcA, ptr nocapture readonly %pSrcB, ptr nocapture %realResult, ptr nocapture %imagResult) {7; CHECK-LLC-LABEL: complex_dot_prod:8; CHECK-LLC: @ %bb.0: @ %entry9; CHECK-LLC-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}10; CHECK-LLC-NEXT: ldr r5, [r0]11; CHECK-LLC-NEXT: ldr r7, [r1]12; CHECK-LLC-NEXT: ldr.w r10, [r0, #4]13; CHECK-LLC-NEXT: ldr.w r8, [r0, #8]14; CHECK-LLC-NEXT: ldr.w r12, [r0, #12]15; CHECK-LLC-NEXT: ldr r4, [r1, #4]16; CHECK-LLC-NEXT: ldr.w r9, [r1, #8]17; CHECK-LLC-NEXT: ldr.w lr, [r1, #12]18; CHECK-LLC-NEXT: movs r0, #019; CHECK-LLC-NEXT: movs r1, #020; CHECK-LLC-NEXT: smlaldx r0, r1, r5, r721; CHECK-LLC-NEXT: smulbb r6, r7, r522; CHECK-LLC-NEXT: smultt r5, r7, r523; CHECK-LLC-NEXT: asr.w r11, r6, #3124; CHECK-LLC-NEXT: subs r6, r6, r525; CHECK-LLC-NEXT: sbc.w r5, r11, r5, asr #3126; CHECK-LLC-NEXT: smlaldx r0, r1, r10, r427; CHECK-LLC-NEXT: smlalbb r6, r5, r4, r1028; CHECK-LLC-NEXT: smultt r4, r4, r1029; CHECK-LLC-NEXT: subs r6, r6, r430; CHECK-LLC-NEXT: sbc.w r4, r5, r4, asr #3131; CHECK-LLC-NEXT: smlalbb r6, r4, r9, r832; CHECK-LLC-NEXT: smultt r5, r9, r833; CHECK-LLC-NEXT: subs r6, r6, r534; CHECK-LLC-NEXT: sbc.w r4, r4, r5, asr #3135; CHECK-LLC-NEXT: smlaldx r0, r1, r8, r936; CHECK-LLC-NEXT: smlalbb r6, r4, lr, r1237; CHECK-LLC-NEXT: smultt r7, lr, r1238; CHECK-LLC-NEXT: smlaldx r0, r1, r12, lr39; CHECK-LLC-NEXT: subs r6, r6, r740; CHECK-LLC-NEXT: sbc.w r7, r4, r7, asr #3141; CHECK-LLC-NEXT: lsrs r6, r6, #642; CHECK-LLC-NEXT: lsrs r0, r0, #643; CHECK-LLC-NEXT: orr.w r7, r6, r7, lsl #2644; CHECK-LLC-NEXT: orr.w r0, r0, r1, lsl #2645; CHECK-LLC-NEXT: str r7, [r2]46; CHECK-LLC-NEXT: str r0, [r3]47; CHECK-LLC-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}48; CHECK-LCC: pop.w {r4, r5, r6, r7, r8, r9, r10, pc}49;50; CHECK-OPT-LABEL: @complex_dot_prod(51; CHECK-OPT-NEXT: entry:52; CHECK-OPT-NEXT: [[TMP1:%.*]] = load i32, ptr [[PSRCA:%.*]], align 253; CHECK-OPT-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1654; CHECK-OPT-NEXT: [[TMP3:%.*]] = sext i16 [[TMP2]] to i3255; CHECK-OPT-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP1]], 1656; CHECK-OPT-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i1657; CHECK-OPT-NEXT: [[TMP6:%.*]] = sext i16 [[TMP5]] to i3258; CHECK-OPT-NEXT: [[INCDEC_PTR1:%.*]] = getelementptr inbounds i16, ptr [[PSRCA]], i32 259; CHECK-OPT-NEXT: [[TMP8:%.*]] = load i32, ptr [[PSRCB:%.*]], align 260; CHECK-OPT-NEXT: [[TMP9:%.*]] = trunc i32 [[TMP8]] to i1661; CHECK-OPT-NEXT: [[TMP10:%.*]] = call i64 @llvm.arm.smlaldx(i32 [[TMP1]], i32 [[TMP8]], i64 0)62; CHECK-OPT-NEXT: [[TMP11:%.*]] = sext i16 [[TMP9]] to i3263; CHECK-OPT-NEXT: [[TMP12:%.*]] = lshr i32 [[TMP8]], 1664; CHECK-OPT-NEXT: [[TMP13:%.*]] = trunc i32 [[TMP12]] to i1665; CHECK-OPT-NEXT: [[TMP14:%.*]] = sext i16 [[TMP13]] to i3266; CHECK-OPT-NEXT: [[INCDEC_PTR3:%.*]] = getelementptr inbounds i16, ptr [[PSRCB]], i32 267; CHECK-OPT-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], [[TMP3]]68; CHECK-OPT-NEXT: [[CONV5:%.*]] = sext i32 [[MUL]] to i6469; CHECK-OPT-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP14]], [[TMP6]]70; CHECK-OPT-NEXT: [[CONV14:%.*]] = sext i32 [[MUL13]] to i6471; CHECK-OPT-NEXT: [[SUB:%.*]] = sub nsw i64 [[CONV5]], [[CONV14]]72; CHECK-OPT-NEXT: [[TMP16:%.*]] = load i32, ptr [[INCDEC_PTR1]], align 273; CHECK-OPT-NEXT: [[TMP17:%.*]] = trunc i32 [[TMP16]] to i1674; CHECK-OPT-NEXT: [[TMP18:%.*]] = sext i16 [[TMP17]] to i3275; CHECK-OPT-NEXT: [[TMP19:%.*]] = lshr i32 [[TMP16]], 1676; CHECK-OPT-NEXT: [[TMP20:%.*]] = trunc i32 [[TMP19]] to i1677; CHECK-OPT-NEXT: [[TMP21:%.*]] = sext i16 [[TMP20]] to i3278; CHECK-OPT-NEXT: [[INCDEC_PTR21:%.*]] = getelementptr inbounds i16, ptr [[PSRCA]], i32 479; CHECK-OPT-NEXT: [[TMP23:%.*]] = load i32, ptr [[INCDEC_PTR3]], align 280; CHECK-OPT-NEXT: [[TMP24:%.*]] = trunc i32 [[TMP23]] to i1681; CHECK-OPT-NEXT: [[TMP25:%.*]] = call i64 @llvm.arm.smlaldx(i32 [[TMP16]], i32 [[TMP23]], i64 [[TMP10]])82; CHECK-OPT-NEXT: [[TMP26:%.*]] = sext i16 [[TMP24]] to i3283; CHECK-OPT-NEXT: [[TMP27:%.*]] = lshr i32 [[TMP23]], 1684; CHECK-OPT-NEXT: [[TMP28:%.*]] = trunc i32 [[TMP27]] to i1685; CHECK-OPT-NEXT: [[TMP29:%.*]] = sext i16 [[TMP28]] to i3286; CHECK-OPT-NEXT: [[INCDEC_PTR23:%.*]] = getelementptr inbounds i16, ptr [[PSRCB]], i32 487; CHECK-OPT-NEXT: [[MUL26:%.*]] = mul nsw i32 [[TMP26]], [[TMP18]]88; CHECK-OPT-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i6489; CHECK-OPT-NEXT: [[ADD28:%.*]] = add nsw i64 [[SUB]], [[CONV27]]90; CHECK-OPT-NEXT: [[MUL36:%.*]] = mul nsw i32 [[TMP29]], [[TMP21]]91; CHECK-OPT-NEXT: [[CONV37:%.*]] = sext i32 [[MUL36]] to i6492; CHECK-OPT-NEXT: [[SUB38:%.*]] = sub nsw i64 [[ADD28]], [[CONV37]]93; CHECK-OPT-NEXT: [[TMP31:%.*]] = load i32, ptr [[INCDEC_PTR21]], align 294; CHECK-OPT-NEXT: [[TMP32:%.*]] = trunc i32 [[TMP31]] to i1695; CHECK-OPT-NEXT: [[TMP33:%.*]] = sext i16 [[TMP32]] to i3296; CHECK-OPT-NEXT: [[TMP34:%.*]] = lshr i32 [[TMP31]], 1697; CHECK-OPT-NEXT: [[TMP35:%.*]] = trunc i32 [[TMP34]] to i1698; CHECK-OPT-NEXT: [[TMP36:%.*]] = sext i16 [[TMP35]] to i3299; CHECK-OPT-NEXT: [[INCDEC_PTR45:%.*]] = getelementptr inbounds i16, ptr [[PSRCA]], i32 6100; CHECK-OPT-NEXT: [[TMP38:%.*]] = load i32, ptr [[INCDEC_PTR23]], align 2101; CHECK-OPT-NEXT: [[TMP39:%.*]] = trunc i32 [[TMP38]] to i16102; CHECK-OPT-NEXT: [[TMP40:%.*]] = call i64 @llvm.arm.smlaldx(i32 [[TMP31]], i32 [[TMP38]], i64 [[TMP25]])103; CHECK-OPT-NEXT: [[TMP41:%.*]] = sext i16 [[TMP39]] to i32104; CHECK-OPT-NEXT: [[TMP42:%.*]] = lshr i32 [[TMP38]], 16105; CHECK-OPT-NEXT: [[TMP43:%.*]] = trunc i32 [[TMP42]] to i16106; CHECK-OPT-NEXT: [[TMP44:%.*]] = sext i16 [[TMP43]] to i32107; CHECK-OPT-NEXT: [[INCDEC_PTR47:%.*]] = getelementptr inbounds i16, ptr [[PSRCB]], i32 6108; CHECK-OPT-NEXT: [[MUL50:%.*]] = mul nsw i32 [[TMP41]], [[TMP33]]109; CHECK-OPT-NEXT: [[CONV51:%.*]] = sext i32 [[MUL50]] to i64110; CHECK-OPT-NEXT: [[ADD52:%.*]] = add nsw i64 [[SUB38]], [[CONV51]]111; CHECK-OPT-NEXT: [[MUL60:%.*]] = mul nsw i32 [[TMP44]], [[TMP36]]112; CHECK-OPT-NEXT: [[CONV61:%.*]] = sext i32 [[MUL60]] to i64113; CHECK-OPT-NEXT: [[SUB62:%.*]] = sub nsw i64 [[ADD52]], [[CONV61]]114; CHECK-OPT-NEXT: [[TMP46:%.*]] = load i32, ptr [[INCDEC_PTR45]], align 2115; CHECK-OPT-NEXT: [[TMP47:%.*]] = trunc i32 [[TMP46]] to i16116; CHECK-OPT-NEXT: [[TMP48:%.*]] = sext i16 [[TMP47]] to i32117; CHECK-OPT-NEXT: [[TMP49:%.*]] = lshr i32 [[TMP46]], 16118; CHECK-OPT-NEXT: [[TMP50:%.*]] = trunc i32 [[TMP49]] to i16119; CHECK-OPT-NEXT: [[TMP51:%.*]] = sext i16 [[TMP50]] to i32120; CHECK-OPT-NEXT: [[TMP53:%.*]] = load i32, ptr [[INCDEC_PTR47]], align 2121; CHECK-OPT-NEXT: [[TMP54:%.*]] = trunc i32 [[TMP53]] to i16122; CHECK-OPT-NEXT: [[TMP55:%.*]] = call i64 @llvm.arm.smlaldx(i32 [[TMP46]], i32 [[TMP53]], i64 [[TMP40]])123; CHECK-OPT-NEXT: [[TMP56:%.*]] = sext i16 [[TMP54]] to i32124; CHECK-OPT-NEXT: [[TMP57:%.*]] = lshr i32 [[TMP53]], 16125; CHECK-OPT-NEXT: [[TMP58:%.*]] = trunc i32 [[TMP57]] to i16126; CHECK-OPT-NEXT: [[TMP59:%.*]] = sext i16 [[TMP58]] to i32127; CHECK-OPT-NEXT: [[MUL74:%.*]] = mul nsw i32 [[TMP56]], [[TMP48]]128; CHECK-OPT-NEXT: [[CONV75:%.*]] = sext i32 [[MUL74]] to i64129; CHECK-OPT-NEXT: [[ADD76:%.*]] = add nsw i64 [[SUB62]], [[CONV75]]130; CHECK-OPT-NEXT: [[MUL84:%.*]] = mul nsw i32 [[TMP59]], [[TMP51]]131; CHECK-OPT-NEXT: [[CONV85:%.*]] = sext i32 [[MUL84]] to i64132; CHECK-OPT-NEXT: [[SUB86:%.*]] = sub nsw i64 [[ADD76]], [[CONV85]]133; CHECK-OPT-NEXT: [[TMP60:%.*]] = lshr i64 [[SUB86]], 6134; CHECK-OPT-NEXT: [[CONV92:%.*]] = trunc i64 [[TMP60]] to i32135; CHECK-OPT-NEXT: store i32 [[CONV92]], ptr [[REALRESULT:%.*]], align 4136; CHECK-OPT-NEXT: [[TMP61:%.*]] = lshr i64 [[TMP55]], 6137; CHECK-OPT-NEXT: [[CONV94:%.*]] = trunc i64 [[TMP61]] to i32138; CHECK-OPT-NEXT: store i32 [[CONV94]], ptr [[IMAGRESULT:%.*]], align 4139; CHECK-OPT-NEXT: ret void140entry:141 %incdec.ptr = getelementptr inbounds i16, ptr %pSrcA, i32 1142 %0 = load i16, ptr %pSrcA, align 2143 %incdec.ptr1 = getelementptr inbounds i16, ptr %pSrcA, i32 2144 %1 = load i16, ptr %incdec.ptr, align 2145 %incdec.ptr2 = getelementptr inbounds i16, ptr %pSrcB, i32 1146 %2 = load i16, ptr %pSrcB, align 2147 %incdec.ptr3 = getelementptr inbounds i16, ptr %pSrcB, i32 2148 %3 = load i16, ptr %incdec.ptr2, align 2149 %conv = sext i16 %0 to i32150 %conv4 = sext i16 %2 to i32151 %mul = mul nsw i32 %conv4, %conv152 %conv5 = sext i32 %mul to i64153 %conv7 = sext i16 %3 to i32154 %mul8 = mul nsw i32 %conv7, %conv155 %conv9 = sext i32 %mul8 to i64156 %conv11 = sext i16 %1 to i32157 %mul13 = mul nsw i32 %conv7, %conv11158 %conv14 = sext i32 %mul13 to i64159 %sub = sub nsw i64 %conv5, %conv14160 %mul17 = mul nsw i32 %conv4, %conv11161 %conv18 = sext i32 %mul17 to i64162 %add19 = add nsw i64 %conv9, %conv18163 %incdec.ptr20 = getelementptr inbounds i16, ptr %pSrcA, i32 3164 %4 = load i16, ptr %incdec.ptr1, align 2165 %incdec.ptr21 = getelementptr inbounds i16, ptr %pSrcA, i32 4166 %5 = load i16, ptr %incdec.ptr20, align 2167 %incdec.ptr22 = getelementptr inbounds i16, ptr %pSrcB, i32 3168 %6 = load i16, ptr %incdec.ptr3, align 2169 %incdec.ptr23 = getelementptr inbounds i16, ptr %pSrcB, i32 4170 %7 = load i16, ptr %incdec.ptr22, align 2171 %conv24 = sext i16 %4 to i32172 %conv25 = sext i16 %6 to i32173 %mul26 = mul nsw i32 %conv25, %conv24174 %conv27 = sext i32 %mul26 to i64175 %add28 = add nsw i64 %sub, %conv27176 %conv30 = sext i16 %7 to i32177 %mul31 = mul nsw i32 %conv30, %conv24178 %conv32 = sext i32 %mul31 to i64179 %conv34 = sext i16 %5 to i32180 %mul36 = mul nsw i32 %conv30, %conv34181 %conv37 = sext i32 %mul36 to i64182 %sub38 = sub nsw i64 %add28, %conv37183 %mul41 = mul nsw i32 %conv25, %conv34184 %conv42 = sext i32 %mul41 to i64185 %add33 = add nsw i64 %add19, %conv42186 %add43 = add nsw i64 %add33, %conv32187 %incdec.ptr44 = getelementptr inbounds i16, ptr %pSrcA, i32 5188 %8 = load i16, ptr %incdec.ptr21, align 2189 %incdec.ptr45 = getelementptr inbounds i16, ptr %pSrcA, i32 6190 %9 = load i16, ptr %incdec.ptr44, align 2191 %incdec.ptr46 = getelementptr inbounds i16, ptr %pSrcB, i32 5192 %10 = load i16, ptr %incdec.ptr23, align 2193 %incdec.ptr47 = getelementptr inbounds i16, ptr %pSrcB, i32 6194 %11 = load i16, ptr %incdec.ptr46, align 2195 %conv48 = sext i16 %8 to i32196 %conv49 = sext i16 %10 to i32197 %mul50 = mul nsw i32 %conv49, %conv48198 %conv51 = sext i32 %mul50 to i64199 %add52 = add nsw i64 %sub38, %conv51200 %conv54 = sext i16 %11 to i32201 %mul55 = mul nsw i32 %conv54, %conv48202 %conv56 = sext i32 %mul55 to i64203 %conv58 = sext i16 %9 to i32204 %mul60 = mul nsw i32 %conv54, %conv58205 %conv61 = sext i32 %mul60 to i64206 %sub62 = sub nsw i64 %add52, %conv61207 %mul65 = mul nsw i32 %conv49, %conv58208 %conv66 = sext i32 %mul65 to i64209 %add57 = add nsw i64 %add43, %conv66210 %add67 = add nsw i64 %add57, %conv56211 %incdec.ptr68 = getelementptr inbounds i16, ptr %pSrcA, i32 7212 %12 = load i16, ptr %incdec.ptr45, align 2213 %13 = load i16, ptr %incdec.ptr68, align 2214 %incdec.ptr70 = getelementptr inbounds i16, ptr %pSrcB, i32 7215 %14 = load i16, ptr %incdec.ptr47, align 2216 %15 = load i16, ptr %incdec.ptr70, align 2217 %conv72 = sext i16 %12 to i32218 %conv73 = sext i16 %14 to i32219 %mul74 = mul nsw i32 %conv73, %conv72220 %conv75 = sext i32 %mul74 to i64221 %add76 = add nsw i64 %sub62, %conv75222 %conv78 = sext i16 %15 to i32223 %mul79 = mul nsw i32 %conv78, %conv72224 %conv80 = sext i32 %mul79 to i64225 %conv82 = sext i16 %13 to i32226 %mul84 = mul nsw i32 %conv78, %conv82227 %conv85 = sext i32 %mul84 to i64228 %sub86 = sub nsw i64 %add76, %conv85229 %mul89 = mul nsw i32 %conv73, %conv82230 %conv90 = sext i32 %mul89 to i64231 %add81 = add nsw i64 %add67, %conv90232 %add91 = add nsw i64 %add81, %conv80233 %16 = lshr i64 %sub86, 6234 %conv92 = trunc i64 %16 to i32235 store i32 %conv92, ptr %realResult, align 4236 %17 = lshr i64 %add91, 6237 %conv94 = trunc i64 %17 to i32238 store i32 %conv94, ptr %imagResult, align 4239 ret void240}241