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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -arm-parallel-dsp -mtriple=armv7-a -S %s -o - | FileCheck %s3 4define i32 @overlap_1(ptr %a, ptr %b, i32 %acc) {5; CHECK-LABEL: @overlap_1(6; CHECK-NEXT: entry:7; CHECK-NEXT: [[ADDR_A_1:%.*]] = getelementptr i16, ptr [[A:%.*]], i32 18; CHECK-NEXT: [[ADDR_B_1:%.*]] = getelementptr i16, ptr [[B:%.*]], i32 19; CHECK-NEXT: [[LD_A_0:%.*]] = load i16, ptr [[A]], align 210; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 211; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1612; CHECK-NEXT: [[TMP3:%.*]] = sext i16 [[TMP2]] to i3213; CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP1]], 1614; CHECK-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i1615; CHECK-NEXT: [[TMP6:%.*]] = sext i16 [[TMP5]] to i3216; CHECK-NEXT: [[SEXT_A_0:%.*]] = sext i16 [[LD_A_0]] to i3217; CHECK-NEXT: [[LD_B_0:%.*]] = load i16, ptr [[B]], align 218; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 219; CHECK-NEXT: [[TMP9:%.*]] = trunc i32 [[TMP8]] to i1620; CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.arm.smlad(i32 [[TMP1]], i32 [[TMP8]], i32 [[ACC:%.*]])21; CHECK-NEXT: [[TMP11:%.*]] = sext i16 [[TMP9]] to i3222; CHECK-NEXT: [[TMP12:%.*]] = lshr i32 [[TMP8]], 1623; CHECK-NEXT: [[TMP13:%.*]] = trunc i32 [[TMP12]] to i1624; CHECK-NEXT: [[TMP14:%.*]] = sext i16 [[TMP13]] to i3225; CHECK-NEXT: [[LD_A_1:%.*]] = load i16, ptr [[ADDR_A_1]], align 226; CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[ADDR_A_1]], align 227; CHECK-NEXT: [[TMP17:%.*]] = trunc i32 [[TMP16]] to i1628; CHECK-NEXT: [[TMP18:%.*]] = sext i16 [[TMP17]] to i3229; CHECK-NEXT: [[TMP19:%.*]] = lshr i32 [[TMP16]], 1630; CHECK-NEXT: [[TMP20:%.*]] = trunc i32 [[TMP19]] to i1631; CHECK-NEXT: [[TMP21:%.*]] = sext i16 [[TMP20]] to i3232; CHECK-NEXT: [[LD_B_1:%.*]] = load i16, ptr [[ADDR_B_1]], align 233; CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[ADDR_B_1]], align 234; CHECK-NEXT: [[TMP24:%.*]] = trunc i32 [[TMP23]] to i1635; CHECK-NEXT: [[TMP25:%.*]] = call i32 @llvm.arm.smlad(i32 [[TMP16]], i32 [[TMP23]], i32 [[TMP10]])36; CHECK-NEXT: [[TMP26:%.*]] = sext i16 [[TMP24]] to i3237; CHECK-NEXT: [[TMP27:%.*]] = lshr i32 [[TMP23]], 1638; CHECK-NEXT: [[TMP28:%.*]] = trunc i32 [[TMP27]] to i1639; CHECK-NEXT: [[TMP29:%.*]] = sext i16 [[TMP28]] to i3240; CHECK-NEXT: [[SEXT_A_1:%.*]] = sext i16 [[LD_A_1]] to i3241; CHECK-NEXT: [[SEXT_B_1:%.*]] = sext i16 [[LD_B_1]] to i3242; CHECK-NEXT: [[SEXT_B_0:%.*]] = sext i16 [[LD_B_0]] to i3243; CHECK-NEXT: [[MUL_0:%.*]] = mul i32 [[TMP3]], [[TMP11]]44; CHECK-NEXT: [[MUL_1:%.*]] = mul i32 [[TMP6]], [[TMP14]]45; CHECK-NEXT: [[ADDR_A_2:%.*]] = getelementptr i16, ptr [[A]], i32 246; CHECK-NEXT: [[ADDR_B_2:%.*]] = getelementptr i16, ptr [[B]], i32 247; CHECK-NEXT: [[LD_A_2:%.*]] = load i16, ptr [[ADDR_A_2]], align 248; CHECK-NEXT: [[LD_B_2:%.*]] = load i16, ptr [[ADDR_B_2]], align 249; CHECK-NEXT: [[SEXT_A_2:%.*]] = sext i16 [[LD_A_2]] to i3250; CHECK-NEXT: [[SEXT_B_2:%.*]] = sext i16 [[LD_B_2]] to i3251; CHECK-NEXT: [[MUL_2:%.*]] = mul i32 [[TMP21]], [[TMP29]]52; CHECK-NEXT: [[ADD:%.*]] = add i32 [[MUL_0]], [[MUL_1]]53; CHECK-NEXT: [[ADD_1:%.*]] = add i32 [[MUL_1]], [[MUL_2]]54; CHECK-NEXT: [[ADD_2:%.*]] = add i32 [[ADD_1]], [[ADD]]55; CHECK-NEXT: [[RES:%.*]] = add i32 [[ADD_2]], [[ACC]]56; CHECK-NEXT: ret i32 [[TMP25]]57;58entry:59 %addr.a.1 = getelementptr i16, ptr %a, i32 160 %addr.b.1 = getelementptr i16, ptr %b, i32 161 %ld.a.0 = load i16, ptr %a62 %sext.a.0 = sext i16 %ld.a.0 to i3263 %ld.b.0 = load i16, ptr %b64 %ld.a.1 = load i16, ptr %addr.a.165 %ld.b.1 = load i16, ptr %addr.b.166 %sext.a.1 = sext i16 %ld.a.1 to i3267 %sext.b.1 = sext i16 %ld.b.1 to i3268 %sext.b.0 = sext i16 %ld.b.0 to i3269 %mul.0 = mul i32 %sext.a.0, %sext.b.070 %mul.1 = mul i32 %sext.a.1, %sext.b.171 %addr.a.2 = getelementptr i16, ptr %a, i32 272 %addr.b.2 = getelementptr i16, ptr %b, i32 273 %ld.a.2 = load i16, ptr %addr.a.274 %ld.b.2 = load i16, ptr %addr.b.275 %sext.a.2 = sext i16 %ld.a.2 to i3276 %sext.b.2 = sext i16 %ld.b.2 to i3277 %mul.2 = mul i32 %sext.a.2, %sext.b.278 %add = add i32 %mul.0, %mul.179 %add.1 = add i32 %mul.1, %mul.280 %add.2 = add i32 %add.1, %add81 %res = add i32 %add.2, %acc82 ret i32 %res83}84 85; TODO: Is it really best to generate smlald for the first instruction? Does86; this just increase register pressure unnecessarily?87define i64 @overlap_64_1(ptr %a, ptr %b, i64 %acc) {88; CHECK-LABEL: @overlap_64_1(89; CHECK-NEXT: entry:90; CHECK-NEXT: [[ADDR_A_1:%.*]] = getelementptr i16, ptr [[A:%.*]], i32 191; CHECK-NEXT: [[ADDR_B_1:%.*]] = getelementptr i16, ptr [[B:%.*]], i32 192; CHECK-NEXT: [[LD_A_0:%.*]] = load i16, ptr [[A]], align 293; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 294; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1695; CHECK-NEXT: [[TMP3:%.*]] = sext i16 [[TMP2]] to i3296; CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP1]], 1697; CHECK-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i1698; CHECK-NEXT: [[TMP6:%.*]] = sext i16 [[TMP5]] to i3299; CHECK-NEXT: [[SEXT_A_0:%.*]] = sext i16 [[LD_A_0]] to i32100; CHECK-NEXT: [[LD_B_0:%.*]] = load i16, ptr [[B]], align 2101; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 2102; CHECK-NEXT: [[TMP9:%.*]] = trunc i32 [[TMP8]] to i16103; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.arm.smlald(i32 [[TMP1]], i32 [[TMP8]], i64 [[ACC:%.*]])104; CHECK-NEXT: [[TMP11:%.*]] = sext i16 [[TMP9]] to i32105; CHECK-NEXT: [[TMP12:%.*]] = lshr i32 [[TMP8]], 16106; CHECK-NEXT: [[TMP13:%.*]] = trunc i32 [[TMP12]] to i16107; CHECK-NEXT: [[TMP14:%.*]] = sext i16 [[TMP13]] to i32108; CHECK-NEXT: [[LD_A_1:%.*]] = load i16, ptr [[ADDR_A_1]], align 2109; CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[ADDR_A_1]], align 2110; CHECK-NEXT: [[TMP17:%.*]] = trunc i32 [[TMP16]] to i16111; CHECK-NEXT: [[TMP18:%.*]] = sext i16 [[TMP17]] to i32112; CHECK-NEXT: [[TMP19:%.*]] = lshr i32 [[TMP16]], 16113; CHECK-NEXT: [[TMP20:%.*]] = trunc i32 [[TMP19]] to i16114; CHECK-NEXT: [[TMP21:%.*]] = sext i16 [[TMP20]] to i32115; CHECK-NEXT: [[LD_B_1:%.*]] = load i16, ptr [[ADDR_B_1]], align 2116; CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[ADDR_B_1]], align 2117; CHECK-NEXT: [[TMP24:%.*]] = trunc i32 [[TMP23]] to i16118; CHECK-NEXT: [[TMP25:%.*]] = call i64 @llvm.arm.smlald(i32 [[TMP16]], i32 [[TMP23]], i64 [[TMP10]])119; CHECK-NEXT: [[TMP26:%.*]] = sext i16 [[TMP24]] to i32120; CHECK-NEXT: [[TMP27:%.*]] = lshr i32 [[TMP23]], 16121; CHECK-NEXT: [[TMP28:%.*]] = trunc i32 [[TMP27]] to i16122; CHECK-NEXT: [[TMP29:%.*]] = sext i16 [[TMP28]] to i32123; CHECK-NEXT: [[SEXT_A_1:%.*]] = sext i16 [[LD_A_1]] to i32124; CHECK-NEXT: [[SEXT_B_1:%.*]] = sext i16 [[LD_B_1]] to i32125; CHECK-NEXT: [[SEXT_B_0:%.*]] = sext i16 [[LD_B_0]] to i32126; CHECK-NEXT: [[MUL_0:%.*]] = mul i32 [[TMP3]], [[TMP11]]127; CHECK-NEXT: [[MUL_1:%.*]] = mul i32 [[TMP6]], [[TMP14]]128; CHECK-NEXT: [[ADDR_A_2:%.*]] = getelementptr i16, ptr [[A]], i32 2129; CHECK-NEXT: [[ADDR_B_2:%.*]] = getelementptr i16, ptr [[B]], i32 2130; CHECK-NEXT: [[LD_A_2:%.*]] = load i16, ptr [[ADDR_A_2]], align 2131; CHECK-NEXT: [[LD_B_2:%.*]] = load i16, ptr [[ADDR_B_2]], align 2132; CHECK-NEXT: [[SEXT_A_2:%.*]] = sext i16 [[LD_A_2]] to i32133; CHECK-NEXT: [[SEXT_B_2:%.*]] = sext i16 [[LD_B_2]] to i32134; CHECK-NEXT: [[MUL_2:%.*]] = mul i32 [[TMP21]], [[TMP29]]135; CHECK-NEXT: [[ADD:%.*]] = add i32 [[MUL_0]], [[MUL_1]]136; CHECK-NEXT: [[ADD_1:%.*]] = add i32 [[MUL_1]], [[MUL_2]]137; CHECK-NEXT: [[SEXT_ADD:%.*]] = sext i32 [[ADD]] to i64138; CHECK-NEXT: [[SEXT_ADD_1:%.*]] = sext i32 [[ADD_1]] to i64139; CHECK-NEXT: [[ADD_2:%.*]] = add i64 [[SEXT_ADD_1]], [[SEXT_ADD]]140; CHECK-NEXT: [[RES:%.*]] = add i64 [[ADD_2]], [[ACC]]141; CHECK-NEXT: ret i64 [[TMP25]]142;143entry:144 %addr.a.1 = getelementptr i16, ptr %a, i32 1145 %addr.b.1 = getelementptr i16, ptr %b, i32 1146 %ld.a.0 = load i16, ptr %a147 %sext.a.0 = sext i16 %ld.a.0 to i32148 %ld.b.0 = load i16, ptr %b149 %ld.a.1 = load i16, ptr %addr.a.1150 %ld.b.1 = load i16, ptr %addr.b.1151 %sext.a.1 = sext i16 %ld.a.1 to i32152 %sext.b.1 = sext i16 %ld.b.1 to i32153 %sext.b.0 = sext i16 %ld.b.0 to i32154 %mul.0 = mul i32 %sext.a.0, %sext.b.0155 %mul.1 = mul i32 %sext.a.1, %sext.b.1156 %addr.a.2 = getelementptr i16, ptr %a, i32 2157 %addr.b.2 = getelementptr i16, ptr %b, i32 2158 %ld.a.2 = load i16, ptr %addr.a.2159 %ld.b.2 = load i16, ptr %addr.b.2160 %sext.a.2 = sext i16 %ld.a.2 to i32161 %sext.b.2 = sext i16 %ld.b.2 to i32162 %mul.2 = mul i32 %sext.a.2, %sext.b.2163 %add = add i32 %mul.0, %mul.1164 %add.1 = add i32 %mul.1, %mul.2165 %sext.add = sext i32 %add to i64166 %sext.add.1 = sext i32 %add.1 to i64167 %add.2 = add i64 %sext.add.1, %sext.add168 %res = add i64 %add.2, %acc169 ret i64 %res170}171 172define i32 @overlap_2(ptr %a, ptr %b, i32 %acc) {173; CHECK-LABEL: @overlap_2(174; CHECK-NEXT: entry:175; CHECK-NEXT: [[ADDR_A_1:%.*]] = getelementptr i16, ptr [[A:%.*]], i32 1176; CHECK-NEXT: [[ADDR_B_1:%.*]] = getelementptr i16, ptr [[B:%.*]], i32 1177; CHECK-NEXT: [[LD_A_0:%.*]] = load i16, ptr [[A]], align 2178; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 2179; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16180; CHECK-NEXT: [[TMP3:%.*]] = sext i16 [[TMP2]] to i32181; CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP1]], 16182; CHECK-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16183; CHECK-NEXT: [[TMP6:%.*]] = sext i16 [[TMP5]] to i32184; CHECK-NEXT: [[SEXT_A_0:%.*]] = sext i16 [[LD_A_0]] to i32185; CHECK-NEXT: [[LD_B_0:%.*]] = load i16, ptr [[B]], align 2186; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 2187; CHECK-NEXT: [[TMP9:%.*]] = trunc i32 [[TMP8]] to i16188; CHECK-NEXT: [[TMP10:%.*]] = sext i16 [[TMP9]] to i32189; CHECK-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP8]], 16190; CHECK-NEXT: [[TMP12:%.*]] = trunc i32 [[TMP11]] to i16191; CHECK-NEXT: [[TMP13:%.*]] = sext i16 [[TMP12]] to i32192; CHECK-NEXT: [[LD_A_1:%.*]] = load i16, ptr [[ADDR_A_1]], align 2193; CHECK-NEXT: [[LD_B_1:%.*]] = load i16, ptr [[ADDR_B_1]], align 2194; CHECK-NEXT: [[SEXT_A_1:%.*]] = sext i16 [[LD_A_1]] to i32195; CHECK-NEXT: [[SEXT_B_1:%.*]] = sext i16 [[LD_B_1]] to i32196; CHECK-NEXT: [[SEXT_B_0:%.*]] = sext i16 [[LD_B_0]] to i32197; CHECK-NEXT: [[MUL_0:%.*]] = mul i32 [[TMP3]], [[TMP10]]198; CHECK-NEXT: [[MUL_1:%.*]] = mul i32 [[TMP6]], [[TMP13]]199; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[MUL_1]], [[ACC:%.*]]200; CHECK-NEXT: [[ADDR_A_2:%.*]] = getelementptr i16, ptr [[A]], i32 2201; CHECK-NEXT: [[ADDR_B_2:%.*]] = getelementptr i16, ptr [[B]], i32 2202; CHECK-NEXT: [[LD_A_2:%.*]] = load i16, ptr [[ADDR_A_2]], align 2203; CHECK-NEXT: [[LD_B_2:%.*]] = load i16, ptr [[ADDR_B_2]], align 2204; CHECK-NEXT: [[SEXT_A_2:%.*]] = sext i16 [[LD_A_2]] to i32205; CHECK-NEXT: [[SEXT_B_2:%.*]] = sext i16 [[LD_B_2]] to i32206; CHECK-NEXT: [[MUL_2:%.*]] = mul i32 [[SEXT_B_2]], [[SEXT_A_2]]207; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[MUL_2]], [[TMP14]]208; CHECK-NEXT: [[TMP16:%.*]] = call i32 @llvm.arm.smlad(i32 [[TMP1]], i32 [[TMP8]], i32 [[TMP15]])209; CHECK-NEXT: [[ADD:%.*]] = add i32 [[MUL_0]], [[MUL_1]]210; CHECK-NEXT: [[ADD_1:%.*]] = add i32 [[MUL_1]], [[MUL_2]]211; CHECK-NEXT: [[ADD_2:%.*]] = add i32 [[ADD]], [[ADD_1]]212; CHECK-NEXT: [[RES:%.*]] = add i32 [[ADD_2]], [[ACC]]213; CHECK-NEXT: ret i32 [[TMP16]]214;215entry:216 %addr.a.1 = getelementptr i16, ptr %a, i32 1217 %addr.b.1 = getelementptr i16, ptr %b, i32 1218 %ld.a.0 = load i16, ptr %a219 %sext.a.0 = sext i16 %ld.a.0 to i32220 %ld.b.0 = load i16, ptr %b221 %ld.a.1 = load i16, ptr %addr.a.1222 %ld.b.1 = load i16, ptr %addr.b.1223 %sext.a.1 = sext i16 %ld.a.1 to i32224 %sext.b.1 = sext i16 %ld.b.1 to i32225 %sext.b.0 = sext i16 %ld.b.0 to i32226 %mul.0 = mul i32 %sext.a.0, %sext.b.0227 %mul.1 = mul i32 %sext.a.1, %sext.b.1228 %addr.a.2 = getelementptr i16, ptr %a, i32 2229 %addr.b.2 = getelementptr i16, ptr %b, i32 2230 %ld.a.2 = load i16, ptr %addr.a.2231 %ld.b.2 = load i16, ptr %addr.b.2232 %sext.a.2 = sext i16 %ld.a.2 to i32233 %sext.b.2 = sext i16 %ld.b.2 to i32234 %mul.2 = mul i32 %sext.b.2, %sext.a.2235 %add = add i32 %mul.0, %mul.1236 %add.1 = add i32 %mul.1, %mul.2237 %add.2 = add i32 %add, %add.1238 %res = add i32 %add.2, %acc239 ret i32 %res240}241 242define i32 @overlap_3(ptr %a, ptr %b, i32 %acc) {243; CHECK-LABEL: @overlap_3(244; CHECK-NEXT: entry:245; CHECK-NEXT: [[ADDR_A_1:%.*]] = getelementptr i16, ptr [[A:%.*]], i32 1246; CHECK-NEXT: [[ADDR_B_1:%.*]] = getelementptr i16, ptr [[B:%.*]], i32 1247; CHECK-NEXT: [[LD_A_0:%.*]] = load i16, ptr [[A]], align 2248; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 2249; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16250; CHECK-NEXT: [[TMP3:%.*]] = sext i16 [[TMP2]] to i32251; CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP1]], 16252; CHECK-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16253; CHECK-NEXT: [[TMP6:%.*]] = sext i16 [[TMP5]] to i32254; CHECK-NEXT: [[SEXT_A_0:%.*]] = sext i16 [[LD_A_0]] to i32255; CHECK-NEXT: [[LD_B_0:%.*]] = load i16, ptr [[B]], align 2256; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 2257; CHECK-NEXT: [[TMP9:%.*]] = trunc i32 [[TMP8]] to i16258; CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.arm.smlad(i32 [[TMP1]], i32 [[TMP8]], i32 [[ACC:%.*]])259; CHECK-NEXT: [[TMP11:%.*]] = sext i16 [[TMP9]] to i32260; CHECK-NEXT: [[TMP12:%.*]] = lshr i32 [[TMP8]], 16261; CHECK-NEXT: [[TMP13:%.*]] = trunc i32 [[TMP12]] to i16262; CHECK-NEXT: [[TMP14:%.*]] = sext i16 [[TMP13]] to i32263; CHECK-NEXT: [[LD_A_1:%.*]] = load i16, ptr [[ADDR_A_1]], align 2264; CHECK-NEXT: [[LD_B_1:%.*]] = load i16, ptr [[ADDR_B_1]], align 2265; CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[ADDR_B_1]], align 2266; CHECK-NEXT: [[TMP17:%.*]] = trunc i32 [[TMP16]] to i16267; CHECK-NEXT: [[TMP18:%.*]] = sext i16 [[TMP17]] to i32268; CHECK-NEXT: [[TMP19:%.*]] = lshr i32 [[TMP16]], 16269; CHECK-NEXT: [[TMP20:%.*]] = trunc i32 [[TMP19]] to i16270; CHECK-NEXT: [[TMP21:%.*]] = sext i16 [[TMP20]] to i32271; CHECK-NEXT: [[SEXT_A_1:%.*]] = sext i16 [[LD_A_1]] to i32272; CHECK-NEXT: [[SEXT_B_1:%.*]] = sext i16 [[LD_B_1]] to i32273; CHECK-NEXT: [[SEXT_B_0:%.*]] = sext i16 [[LD_B_0]] to i32274; CHECK-NEXT: [[MUL_0:%.*]] = mul i32 [[TMP3]], [[TMP11]]275; CHECK-NEXT: [[MUL_1:%.*]] = mul i32 [[TMP6]], [[TMP14]]276; CHECK-NEXT: [[ADDR_A_2:%.*]] = getelementptr i16, ptr [[A]], i32 2277; CHECK-NEXT: [[ADDR_B_2:%.*]] = getelementptr i16, ptr [[B]], i32 2278; CHECK-NEXT: [[ADDR_A_3:%.*]] = getelementptr i16, ptr [[A]], i32 3279; CHECK-NEXT: [[LD_A_2:%.*]] = load i16, ptr [[ADDR_A_2]], align 2280; CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[ADDR_A_2]], align 2281; CHECK-NEXT: [[TMP24:%.*]] = trunc i32 [[TMP23]] to i16282; CHECK-NEXT: [[TMP25:%.*]] = call i32 @llvm.arm.smlad(i32 [[TMP23]], i32 [[TMP16]], i32 [[TMP10]])283; CHECK-NEXT: [[TMP26:%.*]] = sext i16 [[TMP24]] to i32284; CHECK-NEXT: [[TMP27:%.*]] = lshr i32 [[TMP23]], 16285; CHECK-NEXT: [[TMP28:%.*]] = trunc i32 [[TMP27]] to i16286; CHECK-NEXT: [[TMP29:%.*]] = sext i16 [[TMP28]] to i32287; CHECK-NEXT: [[LD_B_2:%.*]] = load i16, ptr [[ADDR_B_2]], align 2288; CHECK-NEXT: [[LD_A_3:%.*]] = load i16, ptr [[ADDR_A_3]], align 2289; CHECK-NEXT: [[SEXT_A_2:%.*]] = sext i16 [[LD_A_2]] to i32290; CHECK-NEXT: [[SEXT_B_2:%.*]] = sext i16 [[LD_B_2]] to i32291; CHECK-NEXT: [[SEXT_A_3:%.*]] = sext i16 [[LD_A_3]] to i32292; CHECK-NEXT: [[MUL_2:%.*]] = mul i32 [[TMP26]], [[TMP14]]293; CHECK-NEXT: [[MUL_3:%.*]] = mul i32 [[TMP29]], [[TMP21]]294; CHECK-NEXT: [[ADD:%.*]] = add i32 [[MUL_0]], [[MUL_1]]295; CHECK-NEXT: [[ADD_1:%.*]] = add i32 [[MUL_2]], [[MUL_3]]296; CHECK-NEXT: [[ADD_2:%.*]] = add i32 [[ADD_1]], [[ADD]]297; CHECK-NEXT: [[RES:%.*]] = add i32 [[ADD_2]], [[ACC]]298; CHECK-NEXT: ret i32 [[TMP25]]299;300entry:301 %addr.a.1 = getelementptr i16, ptr %a, i32 1302 %addr.b.1 = getelementptr i16, ptr %b, i32 1303 %ld.a.0 = load i16, ptr %a304 %sext.a.0 = sext i16 %ld.a.0 to i32305 %ld.b.0 = load i16, ptr %b306 %ld.a.1 = load i16, ptr %addr.a.1307 %ld.b.1 = load i16, ptr %addr.b.1308 %sext.a.1 = sext i16 %ld.a.1 to i32309 %sext.b.1 = sext i16 %ld.b.1 to i32310 %sext.b.0 = sext i16 %ld.b.0 to i32311 %mul.0 = mul i32 %sext.a.0, %sext.b.0312 %mul.1 = mul i32 %sext.a.1, %sext.b.1313 %addr.a.2 = getelementptr i16, ptr %a, i32 2314 %addr.b.2 = getelementptr i16, ptr %b, i32 2315 %addr.a.3 = getelementptr i16, ptr %a, i32 3316 %ld.a.2 = load i16, ptr %addr.a.2317 %ld.b.2 = load i16, ptr %addr.b.2318 %ld.a.3 = load i16, ptr %addr.a.3319 %sext.a.2 = sext i16 %ld.a.2 to i32320 %sext.b.2 = sext i16 %ld.b.2 to i32321 %sext.a.3 = sext i16 %ld.a.3 to i32322 %mul.2 = mul i32 %sext.a.2, %sext.b.1323 %mul.3 = mul i32 %sext.a.3, %sext.b.2324 %add = add i32 %mul.0, %mul.1325 %add.1 = add i32 %mul.2, %mul.3326 %add.2 = add i32 %add.1, %add327 %res = add i32 %add.2, %acc328 ret i32 %res329}330 331define i32 @overlap_4(ptr %a, ptr %b, i32 %acc) {332; CHECK-LABEL: @overlap_4(333; CHECK-NEXT: entry:334; CHECK-NEXT: [[ADDR_A_1:%.*]] = getelementptr i16, ptr [[A:%.*]], i32 1335; CHECK-NEXT: [[ADDR_B_1:%.*]] = getelementptr i16, ptr [[B:%.*]], i32 1336; CHECK-NEXT: [[LD_A_0:%.*]] = load i16, ptr [[A]], align 2337; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 2338; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16339; CHECK-NEXT: [[TMP3:%.*]] = sext i16 [[TMP2]] to i32340; CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP1]], 16341; CHECK-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16342; CHECK-NEXT: [[TMP6:%.*]] = sext i16 [[TMP5]] to i32343; CHECK-NEXT: [[SEXT_A_0:%.*]] = sext i16 [[LD_A_0]] to i32344; CHECK-NEXT: [[LD_B_0:%.*]] = load i16, ptr [[B]], align 2345; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 2346; CHECK-NEXT: [[TMP9:%.*]] = trunc i32 [[TMP8]] to i16347; CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.arm.smlad(i32 [[TMP1]], i32 [[TMP8]], i32 [[ACC:%.*]])348; CHECK-NEXT: [[TMP11:%.*]] = sext i16 [[TMP9]] to i32349; CHECK-NEXT: [[TMP12:%.*]] = lshr i32 [[TMP8]], 16350; CHECK-NEXT: [[TMP13:%.*]] = trunc i32 [[TMP12]] to i16351; CHECK-NEXT: [[TMP14:%.*]] = sext i16 [[TMP13]] to i32352; CHECK-NEXT: [[LD_A_1:%.*]] = load i16, ptr [[ADDR_A_1]], align 2353; CHECK-NEXT: [[LD_B_1:%.*]] = load i16, ptr [[ADDR_B_1]], align 2354; CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[ADDR_B_1]], align 2355; CHECK-NEXT: [[TMP17:%.*]] = trunc i32 [[TMP16]] to i16356; CHECK-NEXT: [[TMP18:%.*]] = sext i16 [[TMP17]] to i32357; CHECK-NEXT: [[TMP19:%.*]] = lshr i32 [[TMP16]], 16358; CHECK-NEXT: [[TMP20:%.*]] = trunc i32 [[TMP19]] to i16359; CHECK-NEXT: [[TMP21:%.*]] = sext i16 [[TMP20]] to i32360; CHECK-NEXT: [[SEXT_A_1:%.*]] = sext i16 [[LD_A_1]] to i32361; CHECK-NEXT: [[SEXT_B_1:%.*]] = sext i16 [[LD_B_1]] to i32362; CHECK-NEXT: [[SEXT_B_0:%.*]] = sext i16 [[LD_B_0]] to i32363; CHECK-NEXT: [[MUL_0:%.*]] = mul i32 [[TMP3]], [[TMP11]]364; CHECK-NEXT: [[MUL_1:%.*]] = mul i32 [[TMP6]], [[TMP14]]365; CHECK-NEXT: [[ADDR_A_2:%.*]] = getelementptr i16, ptr [[A]], i32 2366; CHECK-NEXT: [[ADDR_B_2:%.*]] = getelementptr i16, ptr [[B]], i32 2367; CHECK-NEXT: [[ADDR_A_3:%.*]] = getelementptr i16, ptr [[A]], i32 3368; CHECK-NEXT: [[LD_A_2:%.*]] = load i16, ptr [[ADDR_A_2]], align 2369; CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[ADDR_A_2]], align 2370; CHECK-NEXT: [[TMP24:%.*]] = trunc i32 [[TMP23]] to i16371; CHECK-NEXT: [[TMP25:%.*]] = call i32 @llvm.arm.smladx(i32 [[TMP23]], i32 [[TMP16]], i32 [[TMP10]])372; CHECK-NEXT: [[TMP26:%.*]] = sext i16 [[TMP24]] to i32373; CHECK-NEXT: [[TMP27:%.*]] = lshr i32 [[TMP23]], 16374; CHECK-NEXT: [[TMP28:%.*]] = trunc i32 [[TMP27]] to i16375; CHECK-NEXT: [[TMP29:%.*]] = sext i16 [[TMP28]] to i32376; CHECK-NEXT: [[LD_B_2:%.*]] = load i16, ptr [[ADDR_B_2]], align 2377; CHECK-NEXT: [[LD_A_3:%.*]] = load i16, ptr [[ADDR_A_3]], align 2378; CHECK-NEXT: [[SEXT_A_2:%.*]] = sext i16 [[LD_A_2]] to i32379; CHECK-NEXT: [[SEXT_B_2:%.*]] = sext i16 [[LD_B_2]] to i32380; CHECK-NEXT: [[SEXT_A_3:%.*]] = sext i16 [[LD_A_3]] to i32381; CHECK-NEXT: [[MUL_2:%.*]] = mul i32 [[TMP21]], [[TMP26]]382; CHECK-NEXT: [[MUL_3:%.*]] = mul i32 [[TMP14]], [[TMP29]]383; CHECK-NEXT: [[ADD:%.*]] = add i32 [[MUL_0]], [[MUL_1]]384; CHECK-NEXT: [[ADD_1:%.*]] = add i32 [[MUL_2]], [[MUL_3]]385; CHECK-NEXT: [[ADD_2:%.*]] = add i32 [[ADD_1]], [[ADD]]386; CHECK-NEXT: [[RES:%.*]] = add i32 [[ADD_2]], [[ACC]]387; CHECK-NEXT: ret i32 [[TMP25]]388;389entry:390 %addr.a.1 = getelementptr i16, ptr %a, i32 1391 %addr.b.1 = getelementptr i16, ptr %b, i32 1392 %ld.a.0 = load i16, ptr %a393 %sext.a.0 = sext i16 %ld.a.0 to i32394 %ld.b.0 = load i16, ptr %b395 %ld.a.1 = load i16, ptr %addr.a.1396 %ld.b.1 = load i16, ptr %addr.b.1397 %sext.a.1 = sext i16 %ld.a.1 to i32398 %sext.b.1 = sext i16 %ld.b.1 to i32399 %sext.b.0 = sext i16 %ld.b.0 to i32400 %mul.0 = mul i32 %sext.a.0, %sext.b.0401 %mul.1 = mul i32 %sext.a.1, %sext.b.1402 %addr.a.2 = getelementptr i16, ptr %a, i32 2403 %addr.b.2 = getelementptr i16, ptr %b, i32 2404 %addr.a.3 = getelementptr i16, ptr %a, i32 3405 %ld.a.2 = load i16, ptr %addr.a.2406 %ld.b.2 = load i16, ptr %addr.b.2407 %ld.a.3 = load i16, ptr %addr.a.3408 %sext.a.2 = sext i16 %ld.a.2 to i32409 %sext.b.2 = sext i16 %ld.b.2 to i32410 %sext.a.3 = sext i16 %ld.a.3 to i32411 %mul.2 = mul i32 %sext.b.2, %sext.a.2412 %mul.3 = mul i32 %sext.b.1, %sext.a.3413 %add = add i32 %mul.0, %mul.1414 %add.1 = add i32 %mul.2, %mul.3415 %add.2 = add i32 %add.1, %add416 %res = add i32 %add.2, %acc417 ret i32 %res418}419