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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -mtriple=thumbv7-unknown-linux-gnueabihf < %s -arm-parallel-dsp -verify -S | FileCheck %s3 4target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"5 6define i32 @test(ptr %b) {7; CHECK-LABEL: @test(8; CHECK-NEXT: entry:9; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[B:%.*]], align 210; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B]], align 211; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1612; CHECK-NEXT: [[TMP3:%.*]] = sext i16 [[TMP2]] to i3213; CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP1]], 1614; CHECK-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i1615; CHECK-NEXT: [[TMP6:%.*]] = sext i16 [[TMP5]] to i3216; CHECK-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i3217; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i16, ptr [[B]], i32 318; CHECK-NEXT: [[TMP7:%.*]] = load i16, ptr [[ARRAYIDX1]], align 219; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX1]], align 220; CHECK-NEXT: [[TMP9:%.*]] = trunc i32 [[TMP8]] to i1621; CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.arm.smlad(i32 [[TMP8]], i32 [[TMP1]], i32 0)22; CHECK-NEXT: [[TMP11:%.*]] = sext i16 [[TMP9]] to i3223; CHECK-NEXT: [[TMP12:%.*]] = lshr i32 [[TMP8]], 1624; CHECK-NEXT: [[TMP13:%.*]] = trunc i32 [[TMP12]] to i1625; CHECK-NEXT: [[TMP14:%.*]] = sext i16 [[TMP13]] to i3226; CHECK-NEXT: [[CONV2:%.*]] = sext i16 [[TMP7]] to i3227; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], [[TMP3]]28; CHECK-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i16, ptr [[B]], i32 129; CHECK-NEXT: [[TMP15:%.*]] = load i16, ptr [[INCDEC_PTR]], align 230; CHECK-NEXT: [[CONV4:%.*]] = sext i16 [[TMP15]] to i3231; CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[B]], i32 432; CHECK-NEXT: [[TMP16:%.*]] = load i16, ptr [[ARRAYIDX5]], align 233; CHECK-NEXT: [[CONV6:%.*]] = sext i16 [[TMP16]] to i3234; CHECK-NEXT: [[MUL7:%.*]] = mul nsw i32 [[TMP14]], [[TMP6]]35; CHECK-NEXT: [[ADD9:%.*]] = add nsw i32 [[MUL7]], [[MUL]]36; CHECK-NEXT: [[MUL13:%.*]] = mul nsw i32 0, 037; CHECK-NEXT: [[ADD15:%.*]] = add nsw i32 [[MUL13]], [[TMP10]]38; CHECK-NEXT: ret i32 [[ADD15]]39;40entry:41 %0 = load i16, ptr %b, align 242 %conv = sext i16 %0 to i3243 %arrayidx1 = getelementptr inbounds i16, ptr %b, i32 344 %1 = load i16, ptr %arrayidx1, align 245 %conv2 = sext i16 %1 to i3246 %mul = mul nsw i32 %conv2, %conv47 %incdec.ptr = getelementptr inbounds i16, ptr %b, i32 148 %2 = load i16, ptr %incdec.ptr, align 249 %conv4 = sext i16 %2 to i3250 %arrayidx5 = getelementptr inbounds i16, ptr %b, i32 451 %3 = load i16, ptr %arrayidx5, align 252 %conv6 = sext i16 %3 to i3253 %mul7 = mul nsw i32 %conv6, %conv454 %add9 = add nsw i32 %mul7, %mul55 %mul13 = mul nsw i32 0, 056 %add15 = add nsw i32 %mul13, %add957 ret i32 %add1558}59