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1; RUN: opt -mtriple=armv8m.main-none-none-eabi -mattr=+dsp < %s -arm-parallel-dsp -S | FileCheck %s2;3; The loads are not consecutive: check that the rewrite isn't triggered.4;5; CHECK-NOT: call i32 @llvm.arm.smlad6;7define dso_local i32 @test(i32 %arg, ptr nocapture readnone %arg1, ptr nocapture readonly %arg2, ptr nocapture readonly %arg3) {8entry:9 %cmp24 = icmp sgt i32 %arg, 010 br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup11 12for.body.preheader:13 %.pre = load i16, ptr %arg3, align 214 %.pre27 = load i16, ptr %arg2, align 215 br label %for.body16 17for.cond.cleanup:18 %mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add11, %for.body ]19 ret i32 %mac1.0.lcssa20 21for.body:22 %mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]23 %i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]24 %arrayidx = getelementptr inbounds i16, ptr %arg3, i32 %i.02525 %0 = load i16, ptr %arrayidx, align 226 %add = add nuw nsw i32 %i.025, 127 %arrayidx1 = getelementptr inbounds i16, ptr %arg3, i32 %add28 %1 = load i16, ptr %arrayidx1, align 229 %arrayidx3 = getelementptr inbounds i16, ptr %arg2, i32 %i.02530 %2 = load i16, ptr %arrayidx3, align 231 %conv = sext i16 %2 to i3232 %conv4 = sext i16 %0 to i3233 %mul = mul nsw i32 %conv, %conv434 35; Here we add another constants offset of 2, to make sure the36; loads to %3 and %2 are not consecutive:37 38 %add5 = add nuw nsw i32 %i.025, 239 %arrayidx6 = getelementptr inbounds i16, ptr %arg2, i32 %add540 %3 = load i16, ptr %arrayidx6, align 241 42 %conv7 = sext i16 %3 to i3243 %conv8 = sext i16 %1 to i3244 %mul9 = mul nsw i32 %conv7, %conv845 %add10 = add i32 %mul, %mac1.02646 %add11 = add i32 %add10, %mul947 %exitcond = icmp ne i32 %add, %arg48 br i1 %exitcond, label %for.body, label %for.cond.cleanup49}50 51