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1; RUN: llc -mtriple thumbv7--windows-itanium -print-after=finalize-isel -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-DIV2 3; int f(int n, int d) {4; if (n / d)5; return 1;6; return 0;7; }8 9define arm_aapcs_vfpcc i32 @f(i32 %n, i32 %d) {10entry:11 %retval = alloca i32, align 412 %n.addr = alloca i32, align 413 %d.addr = alloca i32, align 414 store i32 %n, ptr %n.addr, align 415 store i32 %d, ptr %d.addr, align 416 %0 = load i32, ptr %n.addr, align 417 %1 = load i32, ptr %d.addr, align 418 %div = sdiv i32 %0, %119 %tobool = icmp ne i32 %div, 020 br i1 %tobool, label %if.then, label %if.end21 22if.then:23 store i32 1, ptr %retval, align 424 br label %return25 26if.end:27 store i32 0, ptr %retval, align 428 br label %return29 30return:31 %2 = load i32, ptr %retval, align 432 ret i32 %233}34 35; CHECK-DIV-DAG: %bb.036; CHECK-DIV-DAG: successors: %bb.1({{.*}}), %bb.237; CHECK-DIV-DAG: %bb.138; CHECK-DIV-DAG: successors: %bb.339; CHECK-DIV-DAG: %bb.240; CHECK-DIV-DAG: successors: %bb.341; CHECK-DIV-DAG: %bb.342 43; RUN: llc -mtriple thumbv7--windows-itanium -print-after=finalize-isel -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-MOD44 45; int r;46; int g(int l, int m) {47; if (m <= 0)48; return 0;49; return (r = l % m);50; }51 52@r = common global i32 0, align 453 54define arm_aapcs_vfpcc i32 @g(i32 %l, i32 %m) {55entry:56 %cmp = icmp eq i32 %m, 057 br i1 %cmp, label %return, label %if.end58 59if.end:60 %rem = urem i32 %l, %m61 store i32 %rem, ptr @r, align 462 br label %return63 64return:65 %retval.0 = phi i32 [ %rem, %if.end ], [ 0, %entry ]66 ret i32 %retval.067}68 69; CHECK-MOD-DAG: %bb.070; CHECK-MOD-DAG: successors: %bb.2({{.*}}), %bb.171; CHECK-MOD-DAG: %bb.172; CHECK-MOD-DAG: successors: %bb.373; CHECK-MOD-DAG: %bb.374; CHECK-MOD-DAG: successors: %bb.275; CHECK-MOD-DAG: %bb.276 77; RUN: llc -mtriple thumbv7--windows-itanium -print-after=finalize-isel -verify-machineinstrs -filetype asm -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-CFG78; RUN: llc -mtriple thumbv7--windows-itanium -verify-machineinstrs -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-CFG-ASM79 80; unsigned c;81; extern unsigned long g(void);82; int f(unsigned u, signed char b) {83; if (b)84; c = g() % u;85; return c;86; }87 88@c = common global i32 0, align 489 90declare arm_aapcs_vfpcc i32 @i()91 92define arm_aapcs_vfpcc i32 @h(i32 %u, i8 signext %b) #0 {93entry:94 %tobool = icmp eq i8 %b, 095 br i1 %tobool, label %entry.if.end_crit_edge, label %if.then96 97entry.if.end_crit_edge:98 %.pre = load i32, ptr @c, align 499 br label %if.end100 101if.then:102 %call = tail call arm_aapcs_vfpcc i32 @i()103 %rem = urem i32 %call, %u104 store i32 %rem, ptr @c, align 4105 br label %if.end106 107if.end:108 %0 = phi i32 [ %.pre, %entry.if.end_crit_edge ], [ %rem, %if.then ]109 ret i32 %0110}111 112attributes #0 = { optsize }113 114; CHECK-CFG-DAG: %bb.0115; CHECK-CFG-DAG: t2Bcc %bb.2116; CHECK-CFG-DAG: t2B %bb.1117 118; CHECK-CFG-DAG: %bb.1119; CHECK-CFG-DAG: t2B %bb.3120 121; CHECK-CFG-DAG: %bb.2122; CHECK-CFG-DAG: tCMPi8 %{{[0-9]}}{{[^,]*}}, 0123; CHECK-CFG-DAG: t2Bcc %bb.5124 125; CHECK-CFG-DAG: %bb.4126 127; CHECK-CFG-DAG: %bb.3128; CHECK-CFG-DAG: tBX_RET129 130; CHECK-CFG-DAG: %bb.5131; CHECK-CFG-DAG: t__brkdiv0132 133; CHECK-CFG-ASM-LABEL: h:134; CHECK-CFG-ASM: cbz r{{[0-9]}}, .LBB2_5135; CHECK-CFG-ASM: bl __rt_udiv136; CHECK-CFG-ASM-LABEL: .LBB2_5:137; CHECK-CFG-ASM: __brkdiv0138 139; RUN: llc -O1 -mtriple thumbv7--windows-itanium -verify-machineinstrs -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-WIN__DBZCHK140 141; long k(void);142; int l(void);143; int j(int i) {144; if (l() == -1)145; return 0;146; return k() % i;147; }148 149declare arm_aapcs_vfpcc i32 @k()150declare arm_aapcs_vfpcc i32 @l()151 152define arm_aapcs_vfpcc i32 @j(i32 %i) {153entry:154 %retval = alloca i32, align 4155 %i.addr = alloca i32, align 4156 store i32 %i, ptr %i.addr, align 4157 %call = call arm_aapcs_vfpcc i32 @l()158 %cmp = icmp eq i32 %call, -1159 br i1 %cmp, label %if.then, label %if.end160 161if.then:162 store i32 0, ptr %retval, align 4163 br label %return164 165if.end:166 %call1 = call arm_aapcs_vfpcc i32 @k()167 %0 = load i32, ptr %i.addr, align 4168 %rem = srem i32 %call1, %0169 store i32 %rem, ptr %retval, align 4170 br label %return171 172return:173 %1 = load i32, ptr %retval, align 4174 ret i32 %1175}176 177; CHECK-WIN__DBZCHK-LABEL: j:178; CHECK-WIN__DBZCHK: cbz r{{[0-7]}}, .LBB179; CHECK-WIN__DBZCHK-NOT: cbz r8, .LBB180; CHECK-WIN__DBZCHK-NOT: cbz r9, .LBB181; CHECK-WIN__DBZCHK-NOT: cbz r10, .LBB182; CHECK-WIN__DBZCHK-NOT: cbz r11, .LBB183; CHECK-WIN__DBZCHK-NOT: cbz ip, .LBB184; CHECK-WIN__DBZCHK-NOT: cbz lr, .LBB185 186