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1; RUN: llc -mtriple thumbv7--windows-itanium -filetype asm -o - %s | FileCheck %s2 3declare double @llvm.powi.f64.i32(double, i32)4declare float @llvm.powi.f32.i32(float, i32)5 6define arm_aapcs_vfpcc double @d(double %d, i32 %i) {7entry:8 %0 = tail call double @llvm.powi.f64.i32(double %d, i32 %i)9 ret double %010}11 12; CHECK-LABEL: d:13; CHECK: vmov s[[REGISTER:[0-9]+]], r014; CHECK-NEXT: vcvt.f64.s32 d1, s[[REGISTER]]15; CHECK-NEXT: b.w pow16; CHECK-NOT: __powisf217 18define arm_aapcs_vfpcc float @f(float %f, i32 %i) {19entry:20 %0 = tail call float @llvm.powi.f32.i32(float %f, i32 %i)21 ret float %022}23 24; CHECK-LABEL: f:25; CHECK: vmov s[[REGISTER:[0-9]+]], r026; CHECK-NEXT: vcvt.f32.s32 s1, s[[REGISTER]]27; CHECK-NEXT: b.w pow28; CHECK-NOT: __powisf229 30define arm_aapcs_vfpcc float @g(double %d, i32 %i) {31entry:32 %0 = tail call double @llvm.powi.f64.i32(double %d, i32 %i)33 %conv = fptrunc double %0 to float34 ret float %conv35}36 37; CHECK-LABEL: g:38; CHECK: vmov s[[REGISTER:[0-9]+]], r039; CHECK-NEXT: vcvt.f64.s32 d1, s[[REGISTER]]40; CHECK-NEXT: bl pow41; CHECK-NOT: bl __powidf242; CHECK-NEXT: vcvt.f32.f64 s0, d043 44define arm_aapcs_vfpcc double @h(float %f, i32 %i) {45entry:46 %0 = tail call float @llvm.powi.f32.i32(float %f, i32 %i)47 %conv = fpext float %0 to double48 ret double %conv49}50 51; CHECK-LABEL: h:52; CHECK: vmov s[[REGISTER:[0-9]+]], r053; CHECK-NEXT: vcvt.f32.s32 s1, s[[REGISTER]]54; CHECK-NEXT: bl powf55; CHECK-NOT: bl __powisf256; CHECK-NEXT: vcvt.f64.f32 d0, s057 58