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1; RUN: llc -mtriple=thumbv7-windows-itanium -mcpu=cortex-a9 -o - %s \2; RUN: | FileCheck %s -check-prefix CHECK-SMALL-CODE3; RUN: llc -mtriple=thumbv7-windows-itanium -mcpu=cortex-a9 -code-model=large -o - %s \4; RUN: | FileCheck %s -check-prefix CHECK-LARGE-CODE5; RUN: llc -mtriple=thumbv7-windows-msvc -mcpu=cortex-a9 -o - %s \6; RUN: | FileCheck %s -check-prefix CHECK-SMALL-CODE7 8define arm_aapcs_vfpcc i8 @function(i32 %sz, i32 %idx) {9entry:10 %vla = alloca i8, i32 %sz, align 111 %arrayidx = getelementptr inbounds i8, ptr %vla, i32 %idx12 %0 = load volatile i8, ptr %arrayidx, align 113 ret i8 %014}15 16; CHECK-SMALL-CODE: adds [[R4:r[0-9]+]], #717; CHECK-SMALL-CODE: bic [[R4]], [[R4]], #418; CHECK-SMALL-CODE: lsrs r4, [[R4]], #219; CHECK-SMALL-CODE: bl __chkstk20; CHECK-SMALL-CODE: sub.w sp, sp, r421 22; CHECK-LARGE-CODE: adds [[R4:r[0-9]+]], #723; CHECK-LARGE-CODE: bic [[R4]], [[R4]], #424; CHECK-LARGE-CODE: lsrs r4, [[R4]], #225; CHECK-LARGE-CODE: movw [[IP:r[0-9]+]], :lower16:__chkstk26; CHECK-LARGE-CODE: movt [[IP]], :upper16:__chkstk27; CHECK-LARGE-CODE: blx [[IP]]28; CHECK-LARGE-CODE: sub.w sp, sp, r429