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1; RUN: llc -mtriple=arm-eabi -float-abi=hard -mcpu=cortex-a15 -mattr=+neon,+neonfp %s -o - \2; RUN: | FileCheck %s3 4; This test checks that the VMLxForwarting feature is disabled for A15.5; CHECK: fun_a:6define <4 x i32> @fun_a(<4 x i32> %x, <4 x i32> %y) nounwind{7 %1 = add <4 x i32> %x, %y8; CHECK-NOT: vmul9; CHECK: vmla10 %2 = mul <4 x i32> %1, %111 %3 = add <4 x i32> %y, %212 ret <4 x i32> %313}14 15; This tests checks that VMLA FP patterns can be matched in instruction selection when targeting16; Cortex-A15.17; CHECK: fun_b:18define <4 x float> @fun_b(<4 x float> %x, <4 x float> %y, <4 x float> %z) nounwind{19; CHECK: vmla.f3220 %t = fmul <4 x float> %x, %y21 %r = fadd <4 x float> %t, %z22 ret <4 x float> %r23}24 25; This tests checks that FP VMLA instructions are not expanded into separate multiply/addition26; operations when targeting Cortex-A15.27; CHECK: fun_c:28define <4 x float> @fun_c(<4 x float> %x, <4 x float> %y, <4 x float> %z, <4 x float> %u, <4 x float> %v) nounwind{29; CHECK: vmla.f3230 %t1 = fmul <4 x float> %x, %y31 %r1 = fadd <4 x float> %t1, %z32; CHECK: vmla.f3233 %t2 = fmul <4 x float> %u, %v34 %r2 = fadd <4 x float> %t2, %r135 ret <4 x float> %r236}37 38