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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s3 4; The generated code for this test uses a vld1.32 instruction5; to write the lane 1 of a D register containing the value of6; <2 x float> %B. Since the D register is defined, it would7; be incorrect to fully write it (with a vmov.f64) before the8; vld1.32 instruction. The test checks that a vmov.f64 was not9; generated.10 11define <2 x float> @t1(ptr %A, <2 x float> %B) {12; CHECK-LABEL: t1:13; CHECK: @ %bb.0:14; CHECK-NEXT: vmov d16, r2, r315; CHECK-NEXT: vld1.32 {d16[1]}, [r0:32]16; CHECK-NEXT: vmov r0, r1, d1617; CHECK-NEXT: bx lr18 %tmp2 = load float, ptr %A, align 419 %tmp3 = insertelement <2 x float> %B, float %tmp2, i32 120 ret <2 x float> %tmp321}22 23; The code generated by this test uses a vld1.32 instruction.24; We check that a dependency breaking vmov* instruction was25; generated.26 27define void @t2(ptr %in, ptr %out, i32 %n) {28; CHECK-LABEL: t2:29; CHECK: @ %bb.0: @ %entry30; CHECK-NEXT: add r0, r0, #431; CHECK-NEXT: add r1, r1, #432; CHECK-NEXT: .LBB1_1: @ %loop33; CHECK-NEXT: @ =>This Inner Loop Header: Depth=134; CHECK-NEXT: vmov.f64 d16, #5.000000e-0135; CHECK-NEXT: vld1.32 {d16[0]}, [r0:32]36; CHECK-NEXT: vmovl.u8 q8, d1637; CHECK-NEXT: vuzp.8 d16, d1838; CHECK-NEXT: vst1.32 {d16[0]}, [r1:32]!39; CHECK-NEXT: add r0, r0, #440; CHECK-NEXT: subs r2, r2, #141; CHECK-NEXT: beq .LBB1_142; CHECK-NEXT: @ %bb.2: @ %ret43; CHECK-NEXT: bx lr44entry:45 br label %loop46loop:47 %oldcount = phi i32 [0, %entry], [%newcount, %loop]48 %newcount = add i32 %oldcount, 149 %p1 = getelementptr <4 x i8>, ptr %in, i32 %newcount50 %p2 = getelementptr <4 x i8>, ptr %out, i32 %newcount51 %tmp1 = load <4 x i8> , ptr %p1, align 452 store <4 x i8> %tmp1, ptr %p253 %cmp = icmp eq i32 %newcount, %n54 br i1 %cmp, label %loop, label %ret55ret:56 ret void57}58 59; If minimizing size, that overrides perf, so no extra vmov.f64 here.60 61; TODO: This (and above) could use a splat load to remove the false62; dependence with no extra instruction.63 64define void @t2_minsize(ptr %in, ptr %out, i32 %n) minsize {65; CHECK-LABEL: t2_minsize:66; CHECK: @ %bb.0: @ %entry67; CHECK-NEXT: add r0, r0, #468; CHECK-NEXT: add r1, r1, #469; CHECK-NEXT: .LBB2_1: @ %loop70; CHECK-NEXT: @ =>This Inner Loop Header: Depth=171; CHECK-NEXT: vld1.32 {d16[0]}, [r0:32]72; CHECK-NEXT: vmovl.u8 q8, d1673; CHECK-NEXT: vuzp.8 d16, d1874; CHECK-NEXT: vst1.32 {d16[0]}, [r1:32]!75; CHECK-NEXT: add r0, r0, #476; CHECK-NEXT: subs r2, r2, #177; CHECK-NEXT: beq .LBB2_178; CHECK-NEXT: @ %bb.2: @ %ret79; CHECK-NEXT: bx lr80entry:81 br label %loop82loop:83 %oldcount = phi i32 [0, %entry], [%newcount, %loop]84 %newcount = add i32 %oldcount, 185 %p1 = getelementptr <4 x i8>, ptr %in, i32 %newcount86 %p2 = getelementptr <4 x i8>, ptr %out, i32 %newcount87 %tmp1 = load <4 x i8> , ptr %p1, align 488 store <4 x i8> %tmp1, ptr %p289 %cmp = icmp eq i32 %newcount, %n90 br i1 %cmp, label %loop, label %ret91ret:92 ret void93}94