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1; RUN: llc < %s -float-abi=hard -debug-only arm-isel 2>&1 | FileCheck %s2; RUN: llc < %s -float-abi=soft -debug-only arm-isel 2>&1 | FileCheck %s --check-prefix=SOFT3; REQUIRES: asserts4 5target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"6target triple = "armv7-none--eabi"7 8; SOFT-NOT: isHA9 10; CHECK: isHA: 1 { float }11define void @f0b({ float } %a) {12 ret void13}14 15; CHECK: isHA: 1 { float, float }16define void @f1({ float, float } %a) {17 ret void18}19 20; CHECK: isHA: 1 { float, float, float }21define void @f1b({ float, float, float } %a) {22 ret void23}24 25; CHECK: isHA: 1 { float, float, float, float }26define void @f1c({ float, float, float, float } %a) {27 ret void28}29 30; CHECK: isHA: 0 { float, float, float, float, float }31define void @f2({ float, float, float, float, float } %a) {32 ret void33}34 35; CHECK: isHA: 1 { double }36define void @f3({ double } %a) {37 ret void38}39 40; CHECK: isHA: 1 { double, double, double, double }41define void @f4({ double, double, double, double } %a) {42 ret void43}44 45; CHECK: isHA: 0 { double, double, double, double, double }46define void @f5({ double, double, double, double, double } %a) {47 ret void48}49 50; CHECK: isHA: 0 { i32, i32 }51define void @f5b({ i32, i32 } %a) {52 ret void53}54 55; CHECK: isHA: 1 { [1 x float] }56define void @f6({ [1 x float] } %a) {57 ret void58}59 60; CHECK: isHA: 1 { [4 x float] }61define void @f7({ [4 x float] } %a) {62 ret void63}64 65; CHECK: isHA: 0 { [5 x float] }66define void @f8({ [5 x float] } %a) {67 ret void68}69 70; CHECK: isHA: 1 [1 x float]71define void @f6b([1 x float] %a) {72 ret void73}74 75; CHECK: isHA: 1 [4 x float]76define void @f7b([4 x float] %a) {77 ret void78}79 80; CHECK: isHA: 0 [5 x float]81define void @f8b([5 x float] %a) {82 ret void83}84 85; CHECK: isHA: 1 { [2 x float], [2 x float] }86define void @f9({ [2 x float], [2 x float] } %a) {87 ret void88}89 90; CHECK: isHA: 1 { [1 x float], [3 x float] }91define void @f9b({ [1 x float], [3 x float] } %a) {92 ret void93}94 95; CHECK: isHA: 0 { [3 x float], [3 x float] }96define void @f10({ [3 x float], [3 x float] } %a) {97 ret void98}99 100; CHECK: isHA: 1 { <2 x float> }101define void @f11({ <2 x float> } %a) {102 ret void103}104 105; CHECK: isHA: 0 { <3 x float> }106define void @f12({ <3 x float> } %a) {107 ret void108}109 110; CHECK: isHA: 1 { <4 x float> }111define void @f13({ <4 x float> } %a) {112 ret void113}114 115; CHECK: isHA: 1 { <2 x float>, <2 x float> }116define void @f15({ <2 x float>, <2 x float> } %a) {117 ret void118}119 120; CHECK: isHA: 0 { <2 x float>, float }121define void @f15b({ <2 x float>, float } %a) {122 ret void123}124 125; CHECK: isHA: 0 { <2 x float>, [2 x float] }126define void @f15c({ <2 x float>, [2 x float] } %a) {127 ret void128}129 130; CHECK: isHA: 0 { <2 x float>, <4 x float> }131define void @f16({ <2 x float>, <4 x float> } %a) {132 ret void133}134 135; CHECK: isHA: 1 { <2 x double> }136define void @f17({ <2 x double> } %a) {137 ret void138}139 140; CHECK: isHA: 1 { <2 x i32> }141define void @f18({ <2 x i32> } %a) {142 ret void143}144 145; CHECK: isHA: 1 { <2 x i64>, <4 x i32> }146define void @f19({ <2 x i64>, <4 x i32> } %a) {147 ret void148}149 150; CHECK: isHA: 1 { [4 x <4 x float>] }151define void @f20({ [4 x <4 x float>] } %a) {152 ret void153}154 155; CHECK: isHA: 0 { [5 x <4 x float>] }156define void @f21({ [5 x <4 x float>] } %a) {157 ret void158}159 160; CHECK-NOT: isHA161define void @f22({ float } %a, ...) {162 ret void163}164 165