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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv7m-eabi %s -o - | FileCheck %s --check-prefix V7M3; RUN: llc -mtriple=armv7a-eabi %s -o - | FileCheck %s --check-prefix V7A4; RUN: llc -mtriple=thumbv7a-eabi %s -o - | FileCheck %s --check-prefix V7A-T5; RUN: llc -mtriple=armv6m-eabi %s -o - | FileCheck %s --check-prefix V6M6 7define i32 @mask_pair(i32 %x, i32 %y) {8; V7M-LABEL: mask_pair:9; V7M: @ %bb.0:10; V7M-NEXT: lsrs r0, r111; V7M-NEXT: lsls r0, r112; V7M-NEXT: bx lr13;14; V7A-LABEL: mask_pair:15; V7A: @ %bb.0:16; V7A-NEXT: lsr r0, r0, r117; V7A-NEXT: lsl r0, r0, r118; V7A-NEXT: bx lr19;20; V7A-T-LABEL: mask_pair:21; V7A-T: @ %bb.0:22; V7A-T-NEXT: lsrs r0, r123; V7A-T-NEXT: lsls r0, r124; V7A-T-NEXT: bx lr25;26; V6M-LABEL: mask_pair:27; V6M: @ %bb.0:28; V6M-NEXT: lsrs r0, r129; V6M-NEXT: lsls r0, r130; V6M-NEXT: bx lr31 %shl = shl nsw i32 -1, %y32 %and = and i32 %shl, %x33 ret i32 %and34}35 36define i64 @mask_pair_64(i64 %x, i64 %y) {37; V7M-LABEL: mask_pair_64:38; V7M: @ %bb.0:39; V7M-NEXT: mov.w r3, #-140; V7M-NEXT: lsl.w r12, r3, r241; V7M-NEXT: subs r2, #3242; V7M-NEXT: it pl43; V7M-NEXT: movpl.w r12, #044; V7M-NEXT: it pl45; V7M-NEXT: lslpl r3, r246; V7M-NEXT: and.w r0, r0, r1247; V7M-NEXT: ands r1, r348; V7M-NEXT: bx lr49;50; V7A-LABEL: mask_pair_64:51; V7A: @ %bb.0:52; V7A-NEXT: subs r12, r2, #3253; V7A-NEXT: mvn r3, #054; V7A-NEXT: lsl r2, r3, r255; V7A-NEXT: lslpl r3, r3, r1256; V7A-NEXT: movwpl r2, #057; V7A-NEXT: and r1, r3, r158; V7A-NEXT: and r0, r2, r059; V7A-NEXT: bx lr60;61; V7A-T-LABEL: mask_pair_64:62; V7A-T: @ %bb.0:63; V7A-T-NEXT: mov.w r3, #-164; V7A-T-NEXT: lsl.w r12, r3, r265; V7A-T-NEXT: subs r2, #3266; V7A-T-NEXT: it pl67; V7A-T-NEXT: movpl.w r12, #068; V7A-T-NEXT: it pl69; V7A-T-NEXT: lslpl r3, r270; V7A-T-NEXT: and.w r0, r0, r1271; V7A-T-NEXT: ands r1, r372; V7A-T-NEXT: bx lr73;74; V6M-LABEL: mask_pair_64:75; V6M: @ %bb.0:76; V6M-NEXT: .save {r4, r5, r7, lr}77; V6M-NEXT: push {r4, r5, r7, lr}78; V6M-NEXT: mov r4, r179; V6M-NEXT: mov r5, r080; V6M-NEXT: movs r0, #081; V6M-NEXT: mvns r0, r082; V6M-NEXT: mov r1, r083; V6M-NEXT: bl __aeabi_llsl84; V6M-NEXT: ands r0, r585; V6M-NEXT: ands r1, r486; V6M-NEXT: pop {r4, r5, r7, pc}87 %shl = shl nsw i64 -1, %y88 %and = and i64 %shl, %x89 ret i64 %and90}91