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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=arm-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - -O3 \3; RUN: -asm-verbose=0 | FileCheck %s4 5; This tests exerts the folding of `VT = (and (sign_extend NarrowVT to6; VT) #bitmask)` into `VT = (zero_extend NarrowVT to VT)` when7; #bitmask value is the mask made by all ones that selects the value8; of type NarrowVT inside the value of type VT. The folding is9; implemented in `DAGCombiner::visitAND`.10 11; With this the folding, the `and` of the "signed extended load" of12; `%b` in `f_i16_i32` is rendered as a zero extended load.13 14define i32 @f_i16_i32(ptr %a, ptr %b) {15; CHECK-LABEL: f_i16_i32:16; CHECK: ldrh r1, [r1]17; CHECK-NEXT: ldrsh r0, [r0]18; CHECK-NEXT: smulbb r0, r0, r119; CHECK-NEXT: mul r0, r0, r120; CHECK-NEXT: bx lr21 %1 = load i16, ptr %a, align 222 %sext.1 = sext i16 %1 to i3223 %2 = load i16, ptr %b, align 224 %sext.2 = sext i16 %2 to i3225 %masked = and i32 %sext.2, 6553526 %mul = mul nsw i32 %sext.2, %sext.127 %count.next = mul i32 %mul, %masked28 ret i32 %count.next29}30