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1; RUN: llc -mtriple=armv7k-apple-watchos2.0 < %s | FileCheck %s2 3define arm_aapcs_vfpcc float @t1(float %a, float %b) {4entry:5; CHECK: t16; CHECK-NOT: vmov7; CHECK: vadd.f32 8 %a.addr = alloca float, align 49 %b.addr = alloca float, align 410 store float %a, ptr %a.addr, align 411 store float %b, ptr %b.addr, align 412 %0 = load float, ptr %a.addr, align 413 %1 = load float, ptr %b.addr, align 414 %add = fadd float %0, %115 ret float %add16}17 18define arm_aapcs_vfpcc double @t2(double %a, double %b) {19entry:20; CHECK: t221; CHECK-NOT: vmov22; CHECK: vadd.f6423 %a.addr = alloca double, align 824 %b.addr = alloca double, align 825 store double %a, ptr %a.addr, align 826 store double %b, ptr %b.addr, align 827 %0 = load double, ptr %a.addr, align 828 %1 = load double, ptr %b.addr, align 829 %add = fadd double %0, %130 ret double %add31}32 33define arm_aapcs_vfpcc i64 @t3(double %ti) {34entry:35; CHECK-LABEL: t3:36; CHECK-NOT: vmov37; CHECK: bl ___fixunsdfdi38 %conv = fptoui double %ti to i6439 ret i64 %conv40}41 42define arm_aapcs_vfpcc i64 @t4(double %ti) {43entry:44; CHECK-LABEL: t4:45; CHECK-NOT: vmov46; CHECK: bl ___fixdfdi47 %conv = fptosi double %ti to i6448 ret i64 %conv49}50 51define arm_aapcs_vfpcc double @t5(i64 %ti) {52entry:53; CHECK-LABEL: t5:54; CHECK: bl ___floatundidf55; CHECK-NOT: vmov56; CHECK: pop57 %conv = uitofp i64 %ti to double58 ret double %conv59}60 61define arm_aapcs_vfpcc double @t6(i64 %ti) {62entry:63; CHECK-LABEL: t6:64; CHECK: bl ___floatdidf65; CHECK-NOT: vmov66; CHECK: pop67 %conv = sitofp i64 %ti to double68 ret double %conv69}70 71define arm_aapcs_vfpcc float @t7(i64 %ti) {72entry:73; CHECK-LABEL: t7:74; CHECK: bl ___floatundisf75; CHECK-NOT: vmov76; CHECK: pop77 %conv = uitofp i64 %ti to float78 ret float %conv79}80 81define arm_aapcs_vfpcc float @t8(i64 %ti) {82entry:83; CHECK-LABEL: t8:84; CHECK: bl ___floatdisf85; CHECK-NOT: vmov86; CHECK: pop87 %conv = sitofp i64 %ti to float88 ret float %conv89}90 91define arm_aapcs_vfpcc double @t9(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, float %a, float %b) {92entry:93; CHECK-LABEL: t9:94; CHECK-NOT: vmov95; CHECK: vldr96 %add = fadd float %a, %b97 %conv = fpext float %add to double98 ret double %conv99}100 101define arm_aapcs_vfpcc double @t10(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5, double %a, float %b, double %c) {102entry:103; CHECK-LABEL: t10:104; CHECK-NOT: vmov105; CHECK: vldr106 %add = fadd double %a, %c107 ret double %add108}109 110define arm_aapcs_vfpcc float @t11(double %d0, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, float %a, double %b, float %c) {111entry:112; CHECK-LABEL: t11:113; CHECK: vldr114 %add = fadd float %a, %c115 ret float %add116}117 118define arm_aapcs_vfpcc double @t12(double %a, double %b) {119entry:120; CHECK-LABEL: t12:121; CHECK: vstr122 %add = fadd double %a, %b123 %sub = fsub double %a, %b124 %call = tail call arm_aapcs_vfpcc double @x(double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double %add, float 0.000000e+00, double %sub)125 ret double %call126}127 128define arm_aapcs_vfpcc double @t13(double %x) {129entry:130; CHECK-LABEL: t13:131; CHECK-NOT: vmov132; CHECK: bl ___sincos_stret133 %call = tail call arm_aapcs_vfpcc double @cos(double %x)134 %call1 = tail call arm_aapcs_vfpcc double @sin(double %x)135 %mul = fmul double %call, %call1136 ret double %mul137}138 139define arm_aapcs_vfpcc double @t14(double %x) {140; CHECK-LABEL: t14:141; CHECK-NOT: vmov142; CHECK: b ___exp10143 %__exp10 = tail call double @__exp10(double %x) #1144 ret double %__exp10145}146 147declare arm_aapcs_vfpcc double @x(double, double, double, double, double, double, double, float, double)148declare arm_aapcs_vfpcc double @cos(double) #0149declare arm_aapcs_vfpcc double @sin(double) #0150declare double @__exp10(double)151 152attributes #0 = { readnone }153attributes #1 = { readonly }154