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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple armv8.6a-arm-none-eabi -mattr=+neon,+bf16 -float-abi=hard -verify-machineinstrs < %s -o - | FileCheck %s3 4define arm_aapcs_vfpcc <2 x float> @test_vbfdot_f32(<2 x float> %r, <4 x bfloat> %a, <4 x bfloat> %b) {5; CHECK-LABEL: test_vbfdot_f32:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: vdot.bf16 d0, d1, d28; CHECK-NEXT: bx lr9entry:10 %vbfdot3.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %r, <4 x bfloat> %a, <4 x bfloat> %b) #311 ret <2 x float> %vbfdot3.i12}13 14define <4 x float> @test_vbfdotq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {15; CHECK-LABEL: test_vbfdotq_f32:16; CHECK: @ %bb.0: @ %entry17; CHECK-NEXT: vdot.bf16 q0, q1, q218; CHECK-NEXT: bx lr19entry:20 %vbfdot3.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) #321 ret <4 x float> %vbfdot3.i22}23 24define <2 x float> @test_vbfdot_lane_f32(<2 x float> %r, <4 x bfloat> %a, <4 x bfloat> %b) {25; CHECK-LABEL: test_vbfdot_lane_f32:26; CHECK: @ %bb.0: @ %entry27; CHECK-NEXT: vdot.bf16 d0, d1, d2[0]28; CHECK-NEXT: bx lr29entry:30 %.cast = bitcast <4 x bfloat> %b to <2 x float>31 %lane = shufflevector <2 x float> %.cast, <2 x float> undef, <2 x i32> zeroinitializer32 %.cast1 = bitcast <2 x float> %lane to <4 x bfloat>33 %vbfdot3.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %r, <4 x bfloat> %a, <4 x bfloat> %.cast1) #334 ret <2 x float> %vbfdot3.i35}36 37define <4 x float> @test_vbfdotq_laneq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {38; CHECK-LABEL: test_vbfdotq_laneq_f32:39; CHECK: @ %bb.0: @ %entry40; CHECK-NEXT: vdup.32 q8, d5[1]41; CHECK-NEXT: vdot.bf16 q0, q1, q842; CHECK-NEXT: bx lr43entry:44 %.cast = bitcast <8 x bfloat> %b to <4 x float>45 %lane = shufflevector <4 x float> %.cast, <4 x float> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>46 %.cast1 = bitcast <4 x float> %lane to <8 x bfloat>47 %vbfdot3.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %.cast1) #348 ret <4 x float> %vbfdot3.i49}50 51define <2 x float> @test_vbfdot_laneq_f32(<2 x float> %r, <4 x bfloat> %a, <8 x bfloat> %b) {52; CHECK-LABEL: test_vbfdot_laneq_f32:53; CHECK: @ %bb.0: @ %entry54; CHECK-NEXT: vdot.bf16 d0, d1, d3[1]55; CHECK-NEXT: bx lr56entry:57 %.cast = bitcast <8 x bfloat> %b to <4 x float>58 %lane = shufflevector <4 x float> %.cast, <4 x float> undef, <2 x i32> <i32 3, i32 3>59 %.cast1 = bitcast <2 x float> %lane to <4 x bfloat>60 %vbfdot3.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %r, <4 x bfloat> %a, <4 x bfloat> %.cast1) #361 ret <2 x float> %vbfdot3.i62}63 64define <4 x float> @test_vbfdotq_lane_f32(<4 x float> %r, <8 x bfloat> %a, <4 x bfloat> %b) {65; CHECK-LABEL: test_vbfdotq_lane_f32:66; CHECK: @ %bb.0: @ %entry67; CHECK-NEXT: vdot.bf16 q0, q1, d4[0]68; CHECK-NEXT: bx lr69entry:70 %.cast = bitcast <4 x bfloat> %b to <2 x float>71 %lane = shufflevector <2 x float> %.cast, <2 x float> undef, <4 x i32> zeroinitializer72 %.cast1 = bitcast <4 x float> %lane to <8 x bfloat>73 %vbfdot3.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %.cast1) #374 ret <4 x float> %vbfdot3.i75}76 77define <4 x float> @test_vbfmmlaq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {78; CHECK-LABEL: test_vbfmmlaq_f32:79; CHECK: @ %bb.0: @ %entry80; CHECK-NEXT: vmmla.bf16 q0, q1, q281; CHECK-NEXT: bx lr82entry:83 %vbfmmlaq_v3.i = call <4 x float> @llvm.arm.neon.bfmmla(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b)84 ret <4 x float> %vbfmmlaq_v3.i85}86 87define <4 x float> @test_vbfmlalbq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {88; CHECK-LABEL: test_vbfmlalbq_f32:89; CHECK: @ %bb.0: @ %entry90; CHECK-NEXT: vfmab.bf16 q0, q1, q291; CHECK-NEXT: bx lr92entry:93 %vbfmlalbq_v3.i = call <4 x float> @llvm.arm.neon.bfmlalb(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b)94 ret <4 x float> %vbfmlalbq_v3.i95}96 97define <4 x float> @test_vbfmlaltq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {98; CHECK-LABEL: test_vbfmlaltq_f32:99; CHECK: @ %bb.0: @ %entry100; CHECK-NEXT: vfmat.bf16 q0, q1, q2101; CHECK-NEXT: bx lr102entry:103 %vbfmlaltq_v3.i = call <4 x float> @llvm.arm.neon.bfmlalt(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b)104 ret <4 x float> %vbfmlaltq_v3.i105}106 107define <4 x float> @test_vbfmlalbq_lane_f32(<4 x float> %r, <8 x bfloat> %a, <4 x bfloat> %b) {108; CHECK-LABEL: test_vbfmlalbq_lane_f32:109; CHECK: @ %bb.0: @ %entry110; CHECK-NEXT: vfmab.bf16 q0, q1, d4[0]111; CHECK-NEXT: bx lr112entry:113 %vecinit35 = shufflevector <4 x bfloat> %b, <4 x bfloat> undef, <8 x i32> zeroinitializer114 %vbfmlalbq_v3.i = call <4 x float> @llvm.arm.neon.bfmlalb(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %vecinit35)115 ret <4 x float> %vbfmlalbq_v3.i116}117 118define <4 x float> @test_vbfmlalbq_laneq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {119; CHECK-LABEL: test_vbfmlalbq_laneq_f32:120; CHECK: @ %bb.0: @ %entry121; CHECK-NEXT: vfmab.bf16 q0, q1, d4[3]122; CHECK-NEXT: bx lr123entry:124 %vecinit35 = shufflevector <8 x bfloat> %b, <8 x bfloat> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>125 %vbfmlalbq_v3.i = call <4 x float> @llvm.arm.neon.bfmlalb(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %vecinit35)126 ret <4 x float> %vbfmlalbq_v3.i127}128 129define <4 x float> @test_vbfmlaltq_lane_f32(<4 x float> %r, <8 x bfloat> %a, <4 x bfloat> %b) {130; CHECK-LABEL: test_vbfmlaltq_lane_f32:131; CHECK: @ %bb.0: @ %entry132; CHECK-NEXT: vfmat.bf16 q0, q1, d4[0]133; CHECK-NEXT: bx lr134entry:135 %vecinit35 = shufflevector <4 x bfloat> %b, <4 x bfloat> undef, <8 x i32> zeroinitializer136 %vbfmlaltq_v3.i = call <4 x float> @llvm.arm.neon.bfmlalt(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %vecinit35)137 ret <4 x float> %vbfmlaltq_v3.i138}139 140define <4 x float> @test_vbfmlaltq_laneq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {141; CHECK-LABEL: test_vbfmlaltq_laneq_f32:142; CHECK: @ %bb.0: @ %entry143; CHECK-NEXT: vfmat.bf16 q0, q1, d4[3]144; CHECK-NEXT: bx lr145entry:146 %vecinit35 = shufflevector <8 x bfloat> %b, <8 x bfloat> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>147 %vbfmlaltq_v3.i = call <4 x float> @llvm.arm.neon.bfmlalt(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %vecinit35)148 ret <4 x float> %vbfmlaltq_v3.i149}150 151define <4 x float> @test_vbfmlaltq_laneq_f32_v2(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {152; CHECK-LABEL: test_vbfmlaltq_laneq_f32_v2:153; CHECK: @ %bb.0: @ %entry154; CHECK-NEXT: vdup.16 q8, d5[2]155; CHECK-NEXT: vfmat.bf16 q0, q1, q8156; CHECK-NEXT: bx lr157entry:158 %vecinit35 = shufflevector <8 x bfloat> %b, <8 x bfloat> undef, <8 x i32> <i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6>159 %vbfmlalt1.i = call <4 x float> @llvm.arm.neon.bfmlalt(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %vecinit35)160 ret <4 x float> %vbfmlalt1.i161}162 163declare <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float>, <4 x bfloat>, <4 x bfloat>)164declare <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float>, <8 x bfloat>, <8 x bfloat>)165declare <4 x float> @llvm.arm.neon.bfmmla(<4 x float>, <8 x bfloat>, <8 x bfloat>)166declare <4 x float> @llvm.arm.neon.bfmlalb(<4 x float>, <8 x bfloat>, <8 x bfloat>)167declare <4 x float> @llvm.arm.neon.bfmlalt(<4 x float>, <8 x bfloat>, <8 x bfloat>)168