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1; RUN: llc -mtriple=arm-none-linux-gnu -mattr=+neon,+i8mm -float-abi=hard < %s -o -| FileCheck %s2 3define <4 x i32> @smmla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) {4entry:5; CHECK-LABEL: smmla.v4i32.v16i86; CHECK: vsmmla.s8 q0, q1, q27 %vmmla1.i = tail call <4 x i32> @llvm.arm.neon.smmla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) #38 ret <4 x i32> %vmmla1.i9}10 11define <4 x i32> @ummla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) {12entry:13; CHECK-LABEL: ummla.v4i32.v16i814; CHECK: vummla.u8 q0, q1, q215 %vmmla1.i = tail call <4 x i32> @llvm.arm.neon.ummla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) #316 ret <4 x i32> %vmmla1.i17}18 19define <4 x i32> @usmmla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) {20entry:21; CHECK-LABEL: usmmla.v4i32.v16i822; CHECK: vusmmla.s8 q0, q1, q223 %vusmmla1.i = tail call <4 x i32> @llvm.arm.neon.usmmla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) #324 ret <4 x i32> %vusmmla1.i25}26 27define <2 x i32> @usdot.v2i32.v8i8(<2 x i32> %r, <8 x i8> %a, <8 x i8> %b) {28entry:29; CHECK-LABEL: usdot.v2i32.v8i830; CHECK: vusdot.s8 d0, d1, d231 %vusdot1.i = tail call <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32> %r, <8 x i8> %a, <8 x i8> %b) #332 ret <2 x i32> %vusdot1.i33}34 35define <2 x i32> @usdot_lane.v2i32.v8i8(<2 x i32> %r, <8 x i8> %a, <8 x i8> %b) {36entry:37; CHECK-LABEL: usdot_lane.v2i32.v8i838; CHECK: vusdot.s8 d0, d1, d2[0]39 %0 = bitcast <8 x i8> %b to <2 x i32>40 %shuffle = shufflevector <2 x i32> %0, <2 x i32> undef, <2 x i32> zeroinitializer41 %1 = bitcast <2 x i32> %shuffle to <8 x i8>42 %vusdot1.i = tail call <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32> %r, <8 x i8> %a, <8 x i8> %1) #343 ret <2 x i32> %vusdot1.i44}45 46define <2 x i32> @sudot_lane.v2i32.v8i8(<2 x i32> %r, <8 x i8> %a, <8 x i8> %b) {47entry:48; CHECK-LABEL: sudot_lane.v2i32.v8i849; CHECK: vsudot.u8 d0, d1, d2[0]50 %0 = bitcast <8 x i8> %b to <2 x i32>51 %shuffle = shufflevector <2 x i32> %0, <2 x i32> undef, <2 x i32> zeroinitializer52 %1 = bitcast <2 x i32> %shuffle to <8 x i8>53 %vusdot1.i = tail call <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32> %r, <8 x i8> %1, <8 x i8> %a) #354 ret <2 x i32> %vusdot1.i55}56 57define <4 x i32> @usdotq_lane.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <8 x i8> %b) {58entry:59; CHECK-LABEL: usdotq_lane.v4i32.v16i860; CHECK: vusdot.s8 q0, q1, d4[0]61 %0 = bitcast <8 x i8> %b to <2 x i32>62 %shuffle = shufflevector <2 x i32> %0, <2 x i32> undef, <4 x i32> zeroinitializer63 %1 = bitcast <4 x i32> %shuffle to <16 x i8>64 %vusdot1.i = tail call <4 x i32> @llvm.arm.neon.usdot.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %1) #365 ret <4 x i32> %vusdot1.i66}67 68define <4 x i32> @sudotq_lane.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <8 x i8> %b) {69entry:70; CHECK-LABEL: sudotq_lane.v4i32.v16i871; CHECK: vsudot.u8 q0, q1, d4[0]72 %0 = bitcast <8 x i8> %b to <2 x i32>73 %shuffle = shufflevector <2 x i32> %0, <2 x i32> undef, <4 x i32> zeroinitializer74 %1 = bitcast <4 x i32> %shuffle to <16 x i8>75 %vusdot1.i = tail call <4 x i32> @llvm.arm.neon.usdot.v4i32.v16i8(<4 x i32> %r, <16 x i8> %1, <16 x i8> %a) #376 ret <4 x i32> %vusdot1.i77}78 79declare <4 x i32> @llvm.arm.neon.smmla.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>) #280declare <4 x i32> @llvm.arm.neon.ummla.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>) #281declare <4 x i32> @llvm.arm.neon.usmmla.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>) #282declare <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32>, <8 x i8>, <8 x i8>) #283declare <4 x i32> @llvm.arm.neon.usdot.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>) #284