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1; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 -no-integrated-as %s -o - | FileCheck %s2 3define i32 @foo(float %scale, float %scale2) nounwind {4entry:5 %scale.addr = alloca float, align 46 %scale2.addr = alloca float, align 47 store float %scale, ptr %scale.addr, align 48 store float %scale2, ptr %scale2.addr, align 49 %tmp = load float, ptr %scale.addr, align 410 %tmp1 = load float, ptr %scale2.addr, align 411 call void asm sideeffect "vmul.f32 q0, q0, ${0:y} \0A\09vmul.f32 q1, q1, ${0:y} \0A\09vmul.f32 q1, q0, ${1:y} \0A\09", "w,w,~{q0},~{q1}"(float %tmp, float %tmp1) nounwind12 ret i32 013}14 15define void @f0() nounwind {16entry:17; CHECK: f018; CHECK: .word -119call void asm sideeffect ".word ${0:B} \0A\09", "i"(i32 0) nounwind20ret void21}22 23define void @f1() nounwind {24entry:25; CHECK: f126; CHECK: .word 6553527call void asm sideeffect ".word ${0:L} \0A\09", "i"(i32 -1) nounwind28ret void29}30 31@f2_ptr = internal global ptr @f2_var, align 432@f2_var = external global i3233 34define void @f2() nounwind {35entry:36; CHECK: f237; CHECK: ldr r0, [r{{[0-9]+}}]38call void asm sideeffect "ldr r0, [${0:m}]\0A\09", "*m,~{r0}"(ptr elementtype(ptr) @f2_ptr) nounwind39ret void40}41 42@f3_ptr = internal global ptr @f3_var, align 443@f3_var = external global i6444@f3_var2 = external global i6445 46define void @f3() nounwind {47entry:48; CHECK: f349; CHECK: stm {{lr|r[0-9]+}}, {[[REG1:(r[0-9]+)]], r{{[0-9]+}}}50; CHECK: adds {{lr|r[0-9]+}}, [[REG1]]51; CHECK: ldm {{lr|r[0-9]+}}, {r{{[0-9]+}}, r{{[0-9]+}}}52%tmp = load i64, ptr @f3_var, align 453%tmp1 = load i64, ptr @f3_var2, align 454%0 = call i64 asm sideeffect "stm ${0:m}, ${1:M}\0A\09adds $3, $1\0A\09", "=*m,=r,1,r"(ptr elementtype(ptr) @f3_ptr, i64 %tmp, i64 %tmp1) nounwind55store i64 %0, ptr @f3_var, align 456%1 = call i64 asm sideeffect "ldm ${1:m}, ${0:M}\0A\09", "=r,*m"(ptr elementtype(ptr) @f3_ptr) nounwind57store i64 %1, ptr @f3_var, align 458ret void59}60 61define i64 @f4(ptr %val) nounwind {62entry:63 ;CHECK-LABEL: f4:64 ;CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]65 %0 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [$1]", "=&r,r,*Qo"(ptr %val, ptr elementtype(i64) %val) nounwind66 ret i64 %067}68 69; PR1649070define void @f5(i64 %__pu_val) {71 call void asm sideeffect "$1", "r,i"(i64 %__pu_val, i32 -14)72 ret void73}74