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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=arm-eabi -mattr=+v8.2a,+neon,+fullfp16 -float-abi=hard < %s | FileCheck %s3 4%struct.float16x4x2_t = type { [2 x <4 x half>] }5%struct.float16x8x2_t = type { [2 x <8 x half>] }6 7define dso_local <4 x half> @test_vabs_f16(<4 x half> %a) {8; CHECKLABEL: test_vabs_f16:9; CHECK-LABEL: test_vabs_f16:10; CHECK: @ %bb.0: @ %entry11; CHECK-NEXT: vabs.f16 d0, d012; CHECK-NEXT: bx lr13entry:14 %vabs1.i = tail call <4 x half> @llvm.fabs.v4f16(<4 x half> %a)15 ret <4 x half> %vabs1.i16}17 18define dso_local <8 x half> @test_vabsq_f16(<8 x half> %a) {19; CHECKLABEL: test_vabsq_f16:20; CHECK-LABEL: test_vabsq_f16:21; CHECK: @ %bb.0: @ %entry22; CHECK-NEXT: vabs.f16 q0, q023; CHECK-NEXT: bx lr24entry:25 %vabs1.i = tail call <8 x half> @llvm.fabs.v8f16(<8 x half> %a)26 ret <8 x half> %vabs1.i27}28 29define dso_local <4 x i16> @test_vceqz_f16(<4 x half> %a) {30; CHECKLABEL: test_vceqz_f16:31; CHECK-LABEL: test_vceqz_f16:32; CHECK: @ %bb.0: @ %entry33; CHECK-NEXT: vceq.f16 d0, d0, #034; CHECK-NEXT: bx lr35entry:36 %0 = fcmp oeq <4 x half> %a, zeroinitializer37 %vceqz.i = sext <4 x i1> %0 to <4 x i16>38 ret <4 x i16> %vceqz.i39}40 41define dso_local <8 x i16> @test_vceqzq_f16(<8 x half> %a) {42; CHECKLABEL: test_vceqzq_f16:43; CHECK-LABEL: test_vceqzq_f16:44; CHECK: @ %bb.0: @ %entry45; CHECK-NEXT: vceq.f16 q0, q0, #046; CHECK-NEXT: bx lr47entry:48 %0 = fcmp oeq <8 x half> %a, zeroinitializer49 %vceqz.i = sext <8 x i1> %0 to <8 x i16>50 ret <8 x i16> %vceqz.i51}52 53define dso_local <4 x i16> @test_vcgez_f16(<4 x half> %a) {54; CHECKLABEL: test_vcgez_f16:55; CHECK-LABEL: test_vcgez_f16:56; CHECK: @ %bb.0: @ %entry57; CHECK-NEXT: vcge.f16 d0, d0, #058; CHECK-NEXT: bx lr59entry:60 %0 = fcmp oge <4 x half> %a, zeroinitializer61 %vcgez.i = sext <4 x i1> %0 to <4 x i16>62 ret <4 x i16> %vcgez.i63}64 65define dso_local <8 x i16> @test_vcgezq_f16(<8 x half> %a) {66; CHECKLABEL: test_vcgezq_f16:67; CHECK-LABEL: test_vcgezq_f16:68; CHECK: @ %bb.0: @ %entry69; CHECK-NEXT: vcge.f16 q0, q0, #070; CHECK-NEXT: bx lr71entry:72 %0 = fcmp oge <8 x half> %a, zeroinitializer73 %vcgez.i = sext <8 x i1> %0 to <8 x i16>74 ret <8 x i16> %vcgez.i75}76 77define dso_local <4 x i16> @test_vcgtz_f16(<4 x half> %a) {78; CHECKLABEL: test_vcgtz_f16:79; CHECK-LABEL: test_vcgtz_f16:80; CHECK: @ %bb.0: @ %entry81; CHECK-NEXT: vcgt.f16 d0, d0, #082; CHECK-NEXT: bx lr83entry:84 %0 = fcmp ogt <4 x half> %a, zeroinitializer85 %vcgtz.i = sext <4 x i1> %0 to <4 x i16>86 ret <4 x i16> %vcgtz.i87}88 89define dso_local <8 x i16> @test_vcgtzq_f16(<8 x half> %a) {90; CHECKLABEL: test_vcgtzq_f16:91; CHECK-LABEL: test_vcgtzq_f16:92; CHECK: @ %bb.0: @ %entry93; CHECK-NEXT: vcgt.f16 q0, q0, #094; CHECK-NEXT: bx lr95entry:96 %0 = fcmp ogt <8 x half> %a, zeroinitializer97 %vcgtz.i = sext <8 x i1> %0 to <8 x i16>98 ret <8 x i16> %vcgtz.i99}100 101define dso_local <4 x i16> @test_vclez_f16(<4 x half> %a) {102; CHECKLABEL: test_vclez_f16:103; CHECK-LABEL: test_vclez_f16:104; CHECK: @ %bb.0: @ %entry105; CHECK-NEXT: vcle.f16 d0, d0, #0106; CHECK-NEXT: bx lr107entry:108 %0 = fcmp ole <4 x half> %a, zeroinitializer109 %vclez.i = sext <4 x i1> %0 to <4 x i16>110 ret <4 x i16> %vclez.i111}112 113define dso_local <8 x i16> @test_vclezq_f16(<8 x half> %a) {114; CHECKLABEL: test_vclezq_f16:115; CHECK-LABEL: test_vclezq_f16:116; CHECK: @ %bb.0: @ %entry117; CHECK-NEXT: vcle.f16 q0, q0, #0118; CHECK-NEXT: bx lr119entry:120 %0 = fcmp ole <8 x half> %a, zeroinitializer121 %vclez.i = sext <8 x i1> %0 to <8 x i16>122 ret <8 x i16> %vclez.i123}124 125define dso_local <4 x i16> @test_vcltz_f16(<4 x half> %a) {126; CHECKLABEL: test_vcltz_f16:127; CHECK-LABEL: test_vcltz_f16:128; CHECK: @ %bb.0: @ %entry129; CHECK-NEXT: vclt.f16 d0, d0, #0130; CHECK-NEXT: bx lr131entry:132 %0 = fcmp olt <4 x half> %a, zeroinitializer133 %vcltz.i = sext <4 x i1> %0 to <4 x i16>134 ret <4 x i16> %vcltz.i135}136 137define dso_local <8 x i16> @test_vcltzq_f16(<8 x half> %a) {138; CHECKLABEL: test_vcltzq_f16:139; CHECK-LABEL: test_vcltzq_f16:140; CHECK: @ %bb.0: @ %entry141; CHECK-NEXT: vclt.f16 q0, q0, #0142; CHECK-NEXT: bx lr143entry:144 %0 = fcmp olt <8 x half> %a, zeroinitializer145 %vcltz.i = sext <8 x i1> %0 to <8 x i16>146 ret <8 x i16> %vcltz.i147}148 149define dso_local <4 x half> @test_vcvt_f16_s16(<4 x i16> %a) {150; CHECK-LABEL: test_vcvt_f16_s16:151; CHECK: @ %bb.0: @ %entry152; CHECK-NEXT: vcvt.f16.s16 d0, d0153; CHECK-NEXT: bx lr154entry:155 %vcvt.i = sitofp <4 x i16> %a to <4 x half>156 ret <4 x half> %vcvt.i157}158 159define dso_local <8 x half> @test_vcvtq_f16_s16(<8 x i16> %a) {160; CHECK-LABEL: test_vcvtq_f16_s16:161; CHECK: @ %bb.0: @ %entry162; CHECK-NEXT: vcvt.f16.s16 q0, q0163; CHECK-NEXT: bx lr164entry:165 %vcvt.i = sitofp <8 x i16> %a to <8 x half>166 ret <8 x half> %vcvt.i167}168 169define dso_local <4 x half> @test_vcvt_f16_u16(<4 x i16> %a) {170; CHECK-LABEL: test_vcvt_f16_u16:171; CHECK: @ %bb.0: @ %entry172; CHECK-NEXT: vcvt.f16.u16 d0, d0173; CHECK-NEXT: bx lr174entry:175 %vcvt.i = uitofp <4 x i16> %a to <4 x half>176 ret <4 x half> %vcvt.i177}178 179define dso_local <8 x half> @test_vcvtq_f16_u16(<8 x i16> %a) {180; CHECK-LABEL: test_vcvtq_f16_u16:181; CHECK: @ %bb.0: @ %entry182; CHECK-NEXT: vcvt.f16.u16 q0, q0183; CHECK-NEXT: bx lr184entry:185 %vcvt.i = uitofp <8 x i16> %a to <8 x half>186 ret <8 x half> %vcvt.i187}188 189define dso_local <4 x i16> @test_vcvt_s16_f16(<4 x half> %a) {190; CHECK-LABEL: test_vcvt_s16_f16:191; CHECK: @ %bb.0: @ %entry192; CHECK-NEXT: vcvt.s16.f16 d0, d0193; CHECK-NEXT: bx lr194entry:195 %vcvt.i = fptosi <4 x half> %a to <4 x i16>196 ret <4 x i16> %vcvt.i197}198 199define dso_local <8 x i16> @test_vcvtq_s16_f16(<8 x half> %a) {200; CHECK-LABEL: test_vcvtq_s16_f16:201; CHECK: @ %bb.0: @ %entry202; CHECK-NEXT: vcvt.s16.f16 q0, q0203; CHECK-NEXT: bx lr204entry:205 %vcvt.i = fptosi <8 x half> %a to <8 x i16>206 ret <8 x i16> %vcvt.i207}208 209define dso_local <4 x i16> @test_vcvt_u16_f16(<4 x half> %a) {210; CHECK-LABEL: test_vcvt_u16_f16:211; CHECK: @ %bb.0: @ %entry212; CHECK-NEXT: vcvt.u16.f16 d0, d0213; CHECK-NEXT: bx lr214entry:215 %vcvt.i = fptoui <4 x half> %a to <4 x i16>216 ret <4 x i16> %vcvt.i217}218 219define dso_local <8 x i16> @test_vcvtq_u16_f16(<8 x half> %a) {220; CHECK-LABEL: test_vcvtq_u16_f16:221; CHECK: @ %bb.0: @ %entry222; CHECK-NEXT: vcvt.u16.f16 q0, q0223; CHECK-NEXT: bx lr224entry:225 %vcvt.i = fptoui <8 x half> %a to <8 x i16>226 ret <8 x i16> %vcvt.i227}228 229define dso_local <4 x i16> @test_vcvta_s16_f16(<4 x half> %a) {230; CHECK-LABEL: test_vcvta_s16_f16:231; CHECK: @ %bb.0: @ %entry232; CHECK-NEXT: vcvta.s16.f16 d0, d0233; CHECK-NEXT: bx lr234entry:235 %vcvta_s16_v1.i = tail call <4 x i16> @llvm.arm.neon.vcvtas.v4i16.v4f16(<4 x half> %a)236 ret <4 x i16> %vcvta_s16_v1.i237}238 239define dso_local <4 x i16> @test_vcvta_u16_f16(<4 x half> %a) {240; CHECK-LABEL: test_vcvta_u16_f16:241; CHECK: @ %bb.0: @ %entry242; CHECK-NEXT: vcvta.u16.f16 d0, d0243; CHECK-NEXT: bx lr244entry:245 %vcvta_u16_v1.i = tail call <4 x i16> @llvm.arm.neon.vcvtau.v4i16.v4f16(<4 x half> %a)246 ret <4 x i16> %vcvta_u16_v1.i247}248 249define dso_local <8 x i16> @test_vcvtaq_s16_f16(<8 x half> %a) {250; CHECK-LABEL: test_vcvtaq_s16_f16:251; CHECK: @ %bb.0: @ %entry252; CHECK-NEXT: vcvta.s16.f16 q0, q0253; CHECK-NEXT: bx lr254entry:255 %vcvtaq_s16_v1.i = tail call <8 x i16> @llvm.arm.neon.vcvtas.v8i16.v8f16(<8 x half> %a)256 ret <8 x i16> %vcvtaq_s16_v1.i257}258 259define dso_local <4 x i16> @test_vcvtm_s16_f16(<4 x half> %a) {260; CHECK-LABEL: test_vcvtm_s16_f16:261; CHECK: @ %bb.0: @ %entry262; CHECK-NEXT: vcvtm.s16.f16 d0, d0263; CHECK-NEXT: bx lr264entry:265 %vcvtm_s16_v1.i = tail call <4 x i16> @llvm.arm.neon.vcvtms.v4i16.v4f16(<4 x half> %a)266 ret <4 x i16> %vcvtm_s16_v1.i267}268 269define dso_local <8 x i16> @test_vcvtmq_s16_f16(<8 x half> %a) {270; CHECK-LABEL: test_vcvtmq_s16_f16:271; CHECK: @ %bb.0: @ %entry272; CHECK-NEXT: vcvtm.s16.f16 q0, q0273; CHECK-NEXT: bx lr274entry:275 %vcvtmq_s16_v1.i = tail call <8 x i16> @llvm.arm.neon.vcvtms.v8i16.v8f16(<8 x half> %a)276 ret <8 x i16> %vcvtmq_s16_v1.i277}278 279define dso_local <4 x i16> @test_vcvtm_u16_f16(<4 x half> %a) {280; CHECK-LABEL: test_vcvtm_u16_f16:281; CHECK: @ %bb.0: @ %entry282; CHECK-NEXT: vcvtm.u16.f16 d0, d0283; CHECK-NEXT: bx lr284entry:285 %vcvtm_u16_v1.i = tail call <4 x i16> @llvm.arm.neon.vcvtmu.v4i16.v4f16(<4 x half> %a)286 ret <4 x i16> %vcvtm_u16_v1.i287}288 289define dso_local <8 x i16> @test_vcvtmq_u16_f16(<8 x half> %a) {290; CHECK-LABEL: test_vcvtmq_u16_f16:291; CHECK: @ %bb.0: @ %entry292; CHECK-NEXT: vcvtm.u16.f16 q0, q0293; CHECK-NEXT: bx lr294entry:295 %vcvtmq_u16_v1.i = tail call <8 x i16> @llvm.arm.neon.vcvtmu.v8i16.v8f16(<8 x half> %a)296 ret <8 x i16> %vcvtmq_u16_v1.i297}298 299define dso_local <4 x i16> @test_vcvtn_s16_f16(<4 x half> %a) {300; CHECK-LABEL: test_vcvtn_s16_f16:301; CHECK: @ %bb.0: @ %entry302; CHECK-NEXT: vcvtn.s16.f16 d0, d0303; CHECK-NEXT: bx lr304entry:305 %vcvtn_s16_v1.i = tail call <4 x i16> @llvm.arm.neon.vcvtns.v4i16.v4f16(<4 x half> %a)306 ret <4 x i16> %vcvtn_s16_v1.i307}308 309define dso_local <8 x i16> @test_vcvtnq_s16_f16(<8 x half> %a) {310; CHECK-LABEL: test_vcvtnq_s16_f16:311; CHECK: @ %bb.0: @ %entry312; CHECK-NEXT: vcvtn.s16.f16 q0, q0313; CHECK-NEXT: bx lr314entry:315 %vcvtnq_s16_v1.i = tail call <8 x i16> @llvm.arm.neon.vcvtns.v8i16.v8f16(<8 x half> %a)316 ret <8 x i16> %vcvtnq_s16_v1.i317}318 319define dso_local <4 x i16> @test_vcvtn_u16_f16(<4 x half> %a) {320; CHECK-LABEL: test_vcvtn_u16_f16:321; CHECK: @ %bb.0: @ %entry322; CHECK-NEXT: vcvtn.u16.f16 d0, d0323; CHECK-NEXT: bx lr324entry:325 %vcvtn_u16_v1.i = tail call <4 x i16> @llvm.arm.neon.vcvtnu.v4i16.v4f16(<4 x half> %a)326 ret <4 x i16> %vcvtn_u16_v1.i327}328 329define dso_local <8 x i16> @test_vcvtnq_u16_f16(<8 x half> %a) {330; CHECK-LABEL: test_vcvtnq_u16_f16:331; CHECK: @ %bb.0: @ %entry332; CHECK-NEXT: vcvtn.u16.f16 q0, q0333; CHECK-NEXT: bx lr334entry:335 %vcvtnq_u16_v1.i = tail call <8 x i16> @llvm.arm.neon.vcvtnu.v8i16.v8f16(<8 x half> %a)336 ret <8 x i16> %vcvtnq_u16_v1.i337}338 339define dso_local <4 x i16> @test_vcvtp_s16_f16(<4 x half> %a) {340; CHECK-LABEL: test_vcvtp_s16_f16:341; CHECK: @ %bb.0: @ %entry342; CHECK-NEXT: vcvtp.s16.f16 d0, d0343; CHECK-NEXT: bx lr344entry:345 %vcvtp_s16_v1.i = tail call <4 x i16> @llvm.arm.neon.vcvtps.v4i16.v4f16(<4 x half> %a)346 ret <4 x i16> %vcvtp_s16_v1.i347}348 349define dso_local <8 x i16> @test_vcvtpq_s16_f16(<8 x half> %a) {350; CHECK-LABEL: test_vcvtpq_s16_f16:351; CHECK: @ %bb.0: @ %entry352; CHECK-NEXT: vcvtp.s16.f16 q0, q0353; CHECK-NEXT: bx lr354entry:355 %vcvtpq_s16_v1.i = tail call <8 x i16> @llvm.arm.neon.vcvtps.v8i16.v8f16(<8 x half> %a)356 ret <8 x i16> %vcvtpq_s16_v1.i357}358 359define dso_local <4 x i16> @test_vcvtp_u16_f16(<4 x half> %a) {360; CHECK-LABEL: test_vcvtp_u16_f16:361; CHECK: @ %bb.0: @ %entry362; CHECK-NEXT: vcvtp.u16.f16 d0, d0363; CHECK-NEXT: bx lr364entry:365 %vcvtp_u16_v1.i = tail call <4 x i16> @llvm.arm.neon.vcvtpu.v4i16.v4f16(<4 x half> %a)366 ret <4 x i16> %vcvtp_u16_v1.i367}368 369define dso_local <8 x i16> @test_vcvtpq_u16_f16(<8 x half> %a) {370; CHECK-LABEL: test_vcvtpq_u16_f16:371; CHECK: @ %bb.0: @ %entry372; CHECK-NEXT: vcvtp.u16.f16 q0, q0373; CHECK-NEXT: bx lr374entry:375 %vcvtpq_u16_v1.i = tail call <8 x i16> @llvm.arm.neon.vcvtpu.v8i16.v8f16(<8 x half> %a)376 ret <8 x i16> %vcvtpq_u16_v1.i377}378 379define dso_local <4 x half> @test_vneg_f16(<4 x half> %a) {380; CHECKLABEL: test_vneg_f16:381; CHECK-LABEL: test_vneg_f16:382; CHECK: @ %bb.0: @ %entry383; CHECK-NEXT: vneg.f16 d0, d0384; CHECK-NEXT: bx lr385entry:386 %sub.i = fsub <4 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %a387 ret <4 x half> %sub.i388}389 390define dso_local <8 x half> @test_vnegq_f16(<8 x half> %a) {391; CHECKLABEL: test_vnegq_f16:392; CHECK-LABEL: test_vnegq_f16:393; CHECK: @ %bb.0: @ %entry394; CHECK-NEXT: vneg.f16 q0, q0395; CHECK-NEXT: bx lr396entry:397 %sub.i = fsub <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %a398 ret <8 x half> %sub.i399}400 401define dso_local <4 x half> @test_vrecpe_f16(<4 x half> %a) {402; CHECKLABEL: test_vrecpe_f16:403; CHECK-LABEL: test_vrecpe_f16:404; CHECK: @ %bb.0: @ %entry405; CHECK-NEXT: vrecpe.f16 d0, d0406; CHECK-NEXT: bx lr407entry:408 %vrecpe_v1.i = tail call <4 x half> @llvm.arm.neon.vrecpe.v4f16(<4 x half> %a)409 ret <4 x half> %vrecpe_v1.i410}411 412define dso_local <8 x half> @test_vrecpeq_f16(<8 x half> %a) {413; CHECKLABEL: test_vrecpeq_f16:414; CHECK-LABEL: test_vrecpeq_f16:415; CHECK: @ %bb.0: @ %entry416; CHECK-NEXT: vrecpe.f16 q0, q0417; CHECK-NEXT: bx lr418entry:419 %vrecpeq_v1.i = tail call <8 x half> @llvm.arm.neon.vrecpe.v8f16(<8 x half> %a)420 ret <8 x half> %vrecpeq_v1.i421}422 423define dso_local <4 x half> @test_vrnd_f16(<4 x half> %a) {424; CHECKLABEL: test_vrnd_f16:425; CHECK-LABEL: test_vrnd_f16:426; CHECK: @ %bb.0: @ %entry427; CHECK-NEXT: vrintz.f16 d0, d0428; CHECK-NEXT: bx lr429entry:430 %vrnd_v1.i = tail call <4 x half> @llvm.arm.neon.vrintz.v4f16(<4 x half> %a)431 ret <4 x half> %vrnd_v1.i432}433 434define dso_local <8 x half> @test_vrndq_f16(<8 x half> %a) {435; CHECKLABEL: test_vrndq_f16:436; CHECK-LABEL: test_vrndq_f16:437; CHECK: @ %bb.0: @ %entry438; CHECK-NEXT: vrintz.f16 q0, q0439; CHECK-NEXT: bx lr440entry:441 %vrndq_v1.i = tail call <8 x half> @llvm.arm.neon.vrintz.v8f16(<8 x half> %a)442 ret <8 x half> %vrndq_v1.i443}444 445define dso_local <4 x half> @test_vrnda_f16(<4 x half> %a) {446; CHECKLABEL: test_vrnda_f16:447; CHECK-LABEL: test_vrnda_f16:448; CHECK: @ %bb.0: @ %entry449; CHECK-NEXT: vrinta.f16 d0, d0450; CHECK-NEXT: bx lr451entry:452 %vrnda_v1.i = tail call <4 x half> @llvm.arm.neon.vrinta.v4f16(<4 x half> %a)453 ret <4 x half> %vrnda_v1.i454}455 456define dso_local <8 x half> @test_vrndaq_f16(<8 x half> %a) {457; CHECKLABEL: test_vrndaq_f16:458; CHECK-LABEL: test_vrndaq_f16:459; CHECK: @ %bb.0: @ %entry460; CHECK-NEXT: vrinta.f16 q0, q0461; CHECK-NEXT: bx lr462entry:463 %vrndaq_v1.i = tail call <8 x half> @llvm.arm.neon.vrinta.v8f16(<8 x half> %a)464 ret <8 x half> %vrndaq_v1.i465}466 467define dso_local <4 x half> @test_vrndm_f16(<4 x half> %a) {468; CHECKLABEL: test_vrndm_f16:469; CHECK-LABEL: test_vrndm_f16:470; CHECK: @ %bb.0: @ %entry471; CHECK-NEXT: vrintm.f16 d0, d0472; CHECK-NEXT: bx lr473entry:474 %vrndm_v1.i = tail call <4 x half> @llvm.arm.neon.vrintm.v4f16(<4 x half> %a)475 ret <4 x half> %vrndm_v1.i476}477 478define dso_local <8 x half> @test_vrndmq_f16(<8 x half> %a) {479; CHECKLABEL: test_vrndmq_f16:480; CHECK-LABEL: test_vrndmq_f16:481; CHECK: @ %bb.0: @ %entry482; CHECK-NEXT: vrintm.f16 q0, q0483; CHECK-NEXT: bx lr484entry:485 %vrndmq_v1.i = tail call <8 x half> @llvm.arm.neon.vrintm.v8f16(<8 x half> %a)486 ret <8 x half> %vrndmq_v1.i487}488 489define dso_local <4 x half> @test_vrndn_f16(<4 x half> %a) {490; CHECKLABEL: test_vrndn_f16:491; CHECK-LABEL: test_vrndn_f16:492; CHECK: @ %bb.0: @ %entry493; CHECK-NEXT: vrintn.f16 d0, d0494; CHECK-NEXT: bx lr495entry:496 %vrndn_v1.i = tail call <4 x half> @llvm.arm.neon.vrintn.v4f16(<4 x half> %a)497 ret <4 x half> %vrndn_v1.i498}499 500define dso_local <8 x half> @test_vrndnq_f16(<8 x half> %a) {501; CHECKLABEL: test_vrndnq_f16:502; CHECK-LABEL: test_vrndnq_f16:503; CHECK: @ %bb.0: @ %entry504; CHECK-NEXT: vrintn.f16 q0, q0505; CHECK-NEXT: bx lr506entry:507 %vrndnq_v1.i = tail call <8 x half> @llvm.arm.neon.vrintn.v8f16(<8 x half> %a)508 ret <8 x half> %vrndnq_v1.i509}510 511define dso_local <4 x half> @test_vrndp_f16(<4 x half> %a) {512; CHECKLABEL: test_vrndp_f16:513; CHECK-LABEL: test_vrndp_f16:514; CHECK: @ %bb.0: @ %entry515; CHECK-NEXT: vrintp.f16 d0, d0516; CHECK-NEXT: bx lr517entry:518 %vrndp_v1.i = tail call <4 x half> @llvm.arm.neon.vrintp.v4f16(<4 x half> %a)519 ret <4 x half> %vrndp_v1.i520}521 522define dso_local <8 x half> @test_vrndpq_f16(<8 x half> %a) {523; CHECKLABEL: test_vrndpq_f16:524; CHECK-LABEL: test_vrndpq_f16:525; CHECK: @ %bb.0: @ %entry526; CHECK-NEXT: vrintp.f16 q0, q0527; CHECK-NEXT: bx lr528entry:529 %vrndpq_v1.i = tail call <8 x half> @llvm.arm.neon.vrintp.v8f16(<8 x half> %a)530 ret <8 x half> %vrndpq_v1.i531}532 533define dso_local <4 x half> @test_vrndx_f16(<4 x half> %a) {534; CHECKLABEL: test_vrndx_f16:535; CHECK-LABEL: test_vrndx_f16:536; CHECK: @ %bb.0: @ %entry537; CHECK-NEXT: vrintx.f16 d0, d0538; CHECK-NEXT: bx lr539entry:540 %vrndx_v1.i = tail call <4 x half> @llvm.arm.neon.vrintx.v4f16(<4 x half> %a)541 ret <4 x half> %vrndx_v1.i542}543 544define dso_local <8 x half> @test_vrndxq_f16(<8 x half> %a) {545; CHECKLABEL: test_vrndxq_f16:546; CHECK-LABEL: test_vrndxq_f16:547; CHECK: @ %bb.0: @ %entry548; CHECK-NEXT: vrintx.f16 q0, q0549; CHECK-NEXT: bx lr550entry:551 %vrndxq_v1.i = tail call <8 x half> @llvm.arm.neon.vrintx.v8f16(<8 x half> %a)552 ret <8 x half> %vrndxq_v1.i553}554 555define dso_local <4 x half> @test_vrsqrte_f16(<4 x half> %a) {556; CHECKLABEL: test_vrsqrte_f16:557; CHECK-LABEL: test_vrsqrte_f16:558; CHECK: @ %bb.0: @ %entry559; CHECK-NEXT: vrsqrte.f16 d0, d0560; CHECK-NEXT: bx lr561entry:562 %vrsqrte_v1.i = tail call <4 x half> @llvm.arm.neon.vrsqrte.v4f16(<4 x half> %a)563 ret <4 x half> %vrsqrte_v1.i564}565 566define dso_local <8 x half> @test_vrsqrteq_f16(<8 x half> %a) {567; CHECKLABEL: test_vrsqrteq_f16:568; CHECK-LABEL: test_vrsqrteq_f16:569; CHECK: @ %bb.0: @ %entry570; CHECK-NEXT: vrsqrte.f16 q0, q0571; CHECK-NEXT: bx lr572entry:573 %vrsqrteq_v1.i = tail call <8 x half> @llvm.arm.neon.vrsqrte.v8f16(<8 x half> %a)574 ret <8 x half> %vrsqrteq_v1.i575}576 577define dso_local <4 x half> @test_vadd_f16(<4 x half> %a, <4 x half> %b) {578; CHECKLABEL: test_vadd_f16:579; CHECK-LABEL: test_vadd_f16:580; CHECK: @ %bb.0: @ %entry581; CHECK-NEXT: vadd.f16 d0, d0, d1582; CHECK-NEXT: bx lr583entry:584 %add.i = fadd <4 x half> %a, %b585 ret <4 x half> %add.i586}587 588define dso_local <8 x half> @test_vaddq_f16(<8 x half> %a, <8 x half> %b) {589; CHECKLABEL: test_vaddq_f16:590; CHECK-LABEL: test_vaddq_f16:591; CHECK: @ %bb.0: @ %entry592; CHECK-NEXT: vadd.f16 q0, q0, q1593; CHECK-NEXT: bx lr594entry:595 %add.i = fadd <8 x half> %a, %b596 ret <8 x half> %add.i597}598 599define dso_local <4 x half> @test_vabd_f16(<4 x half> %a, <4 x half> %b) {600; CHECKLABEL: test_vabd_f16:601; CHECK-LABEL: test_vabd_f16:602; CHECK: @ %bb.0: @ %entry603; CHECK-NEXT: vabd.f16 d0, d0, d1604; CHECK-NEXT: bx lr605entry:606 %vabd_v2.i = tail call <4 x half> @llvm.arm.neon.vabds.v4f16(<4 x half> %a, <4 x half> %b)607 ret <4 x half> %vabd_v2.i608}609 610define dso_local <8 x half> @test_vabdq_f16(<8 x half> %a, <8 x half> %b) {611; CHECKLABEL: test_vabdq_f16:612; CHECK-LABEL: test_vabdq_f16:613; CHECK: @ %bb.0: @ %entry614; CHECK-NEXT: vabd.f16 q0, q0, q1615; CHECK-NEXT: bx lr616entry:617 %vabdq_v2.i = tail call <8 x half> @llvm.arm.neon.vabds.v8f16(<8 x half> %a, <8 x half> %b)618 ret <8 x half> %vabdq_v2.i619}620 621define dso_local <4 x i16> @test_vcage_f16(<4 x half> %a, <4 x half> %b) {622; CHECKLABEL: test_vcage_f16:623; CHECK-LABEL: test_vcage_f16:624; CHECK: @ %bb.0: @ %entry625; CHECK-NEXT: vacge.f16 d0, d0, d1626; CHECK-NEXT: bx lr627entry:628 %vcage_v2.i = tail call <4 x i16> @llvm.arm.neon.vacge.v4i16.v4f16(<4 x half> %a, <4 x half> %b)629 ret <4 x i16> %vcage_v2.i630}631 632define dso_local <8 x i16> @test_vcageq_f16(<8 x half> %a, <8 x half> %b) {633; CHECKLABEL: test_vcageq_f16:634; CHECK-LABEL: test_vcageq_f16:635; CHECK: @ %bb.0: @ %entry636; CHECK-NEXT: vacge.f16 q0, q0, q1637; CHECK-NEXT: bx lr638entry:639 %vcageq_v2.i = tail call <8 x i16> @llvm.arm.neon.vacge.v8i16.v8f16(<8 x half> %a, <8 x half> %b)640 ret <8 x i16> %vcageq_v2.i641}642 643define dso_local <4 x i16> @test_vcagt_f16(<4 x half> %a, <4 x half> %b) {644; CHECK-LABEL: test_vcagt_f16:645; CHECK: @ %bb.0: @ %entry646; CHECK-NEXT: vacgt.f16 d0, d0, d1647; CHECK-NEXT: bx lr648entry:649 %vcagt_v2.i = tail call <4 x i16> @llvm.arm.neon.vacgt.v4i16.v4f16(<4 x half> %a, <4 x half> %b)650 ret <4 x i16> %vcagt_v2.i651}652 653define dso_local <8 x i16> @test_vcagtq_f16(<8 x half> %a, <8 x half> %b) {654; CHECK-LABEL: test_vcagtq_f16:655; CHECK: @ %bb.0: @ %entry656; CHECK-NEXT: vacgt.f16 q0, q0, q1657; CHECK-NEXT: bx lr658entry:659 %vcagtq_v2.i = tail call <8 x i16> @llvm.arm.neon.vacgt.v8i16.v8f16(<8 x half> %a, <8 x half> %b)660 ret <8 x i16> %vcagtq_v2.i661}662 663define dso_local <4 x i16> @test_vcale_f16(<4 x half> %a, <4 x half> %b) {664; CHECKLABEL: test_vcale_f16:665; CHECK-LABEL: test_vcale_f16:666; CHECK: @ %bb.0: @ %entry667; CHECK-NEXT: vacge.f16 d0, d1, d0668; CHECK-NEXT: bx lr669entry:670 %vcale_v2.i = tail call <4 x i16> @llvm.arm.neon.vacge.v4i16.v4f16(<4 x half> %b, <4 x half> %a)671 ret <4 x i16> %vcale_v2.i672}673 674define dso_local <8 x i16> @test_vcaleq_f16(<8 x half> %a, <8 x half> %b) {675; CHECKLABEL: test_vcaleq_f16:676; CHECK-LABEL: test_vcaleq_f16:677; CHECK: @ %bb.0: @ %entry678; CHECK-NEXT: vacge.f16 q0, q1, q0679; CHECK-NEXT: bx lr680entry:681 %vcaleq_v2.i = tail call <8 x i16> @llvm.arm.neon.vacge.v8i16.v8f16(<8 x half> %b, <8 x half> %a)682 ret <8 x i16> %vcaleq_v2.i683}684 685define dso_local <4 x i16> @test_vceq_f16(<4 x half> %a, <4 x half> %b) {686; CHECKLABEL: test_vceq_f16:687; CHECK-LABEL: test_vceq_f16:688; CHECK: @ %bb.0: @ %entry689; CHECK-NEXT: vceq.f16 d0, d0, d1690; CHECK-NEXT: bx lr691entry:692 %cmp.i = fcmp oeq <4 x half> %a, %b693 %sext.i = sext <4 x i1> %cmp.i to <4 x i16>694 ret <4 x i16> %sext.i695}696 697define dso_local <8 x i16> @test_vceqq_f16(<8 x half> %a, <8 x half> %b) {698; CHECKLABEL: test_vceqq_f16:699; CHECK-LABEL: test_vceqq_f16:700; CHECK: @ %bb.0: @ %entry701; CHECK-NEXT: vceq.f16 q0, q0, q1702; CHECK-NEXT: bx lr703entry:704 %cmp.i = fcmp oeq <8 x half> %a, %b705 %sext.i = sext <8 x i1> %cmp.i to <8 x i16>706 ret <8 x i16> %sext.i707}708 709define dso_local <4 x i16> @test_vcge_f16(<4 x half> %a, <4 x half> %b) {710; CHECKLABEL: test_vcge_f16:711; CHECK-LABEL: test_vcge_f16:712; CHECK: @ %bb.0: @ %entry713; CHECK-NEXT: vcge.f16 d0, d0, d1714; CHECK-NEXT: bx lr715entry:716 %cmp.i = fcmp oge <4 x half> %a, %b717 %sext.i = sext <4 x i1> %cmp.i to <4 x i16>718 ret <4 x i16> %sext.i719}720 721define dso_local <8 x i16> @test_vcgeq_f16(<8 x half> %a, <8 x half> %b) {722; CHECKLABEL: test_vcgeq_f16:723; CHECK-LABEL: test_vcgeq_f16:724; CHECK: @ %bb.0: @ %entry725; CHECK-NEXT: vcge.f16 q0, q0, q1726; CHECK-NEXT: bx lr727entry:728 %cmp.i = fcmp oge <8 x half> %a, %b729 %sext.i = sext <8 x i1> %cmp.i to <8 x i16>730 ret <8 x i16> %sext.i731}732 733define dso_local <4 x i16> @test_vcgt_f16(<4 x half> %a, <4 x half> %b) {734; CHECKLABEL: test_vcgt_f16:735; CHECK-LABEL: test_vcgt_f16:736; CHECK: @ %bb.0: @ %entry737; CHECK-NEXT: vcgt.f16 d0, d0, d1738; CHECK-NEXT: bx lr739entry:740 %cmp.i = fcmp ogt <4 x half> %a, %b741 %sext.i = sext <4 x i1> %cmp.i to <4 x i16>742 ret <4 x i16> %sext.i743}744 745define dso_local <8 x i16> @test_vcgtq_f16(<8 x half> %a, <8 x half> %b) {746; CHECKLABEL: test_vcgtq_f16:747; CHECK-LABEL: test_vcgtq_f16:748; CHECK: @ %bb.0: @ %entry749; CHECK-NEXT: vcgt.f16 q0, q0, q1750; CHECK-NEXT: bx lr751entry:752 %cmp.i = fcmp ogt <8 x half> %a, %b753 %sext.i = sext <8 x i1> %cmp.i to <8 x i16>754 ret <8 x i16> %sext.i755}756 757define dso_local <4 x i16> @test_vcle_f16(<4 x half> %a, <4 x half> %b) {758; CHECKLABEL: test_vcle_f16:759; CHECK-LABEL: test_vcle_f16:760; CHECK: @ %bb.0: @ %entry761; CHECK-NEXT: vcge.f16 d0, d1, d0762; CHECK-NEXT: bx lr763entry:764 %cmp.i = fcmp ole <4 x half> %a, %b765 %sext.i = sext <4 x i1> %cmp.i to <4 x i16>766 ret <4 x i16> %sext.i767}768 769define dso_local <8 x i16> @test_vcleq_f16(<8 x half> %a, <8 x half> %b) {770; CHECKLABEL: test_vcleq_f16:771; CHECK-LABEL: test_vcleq_f16:772; CHECK: @ %bb.0: @ %entry773; CHECK-NEXT: vcge.f16 q0, q1, q0774; CHECK-NEXT: bx lr775entry:776 %cmp.i = fcmp ole <8 x half> %a, %b777 %sext.i = sext <8 x i1> %cmp.i to <8 x i16>778 ret <8 x i16> %sext.i779}780 781define dso_local <4 x i16> @test_vclt_f16(<4 x half> %a, <4 x half> %b) {782; CHECKLABEL: test_vclt_f16:783; CHECK-LABEL: test_vclt_f16:784; CHECK: @ %bb.0: @ %entry785; CHECK-NEXT: vcgt.f16 d0, d1, d0786; CHECK-NEXT: bx lr787entry:788 %cmp.i = fcmp olt <4 x half> %a, %b789 %sext.i = sext <4 x i1> %cmp.i to <4 x i16>790 ret <4 x i16> %sext.i791}792 793define dso_local <8 x i16> @test_vcltq_f16(<8 x half> %a, <8 x half> %b) {794; CHECKLABEL: test_vcltq_f16:795; CHECK-LABEL: test_vcltq_f16:796; CHECK: @ %bb.0: @ %entry797; CHECK-NEXT: vcgt.f16 q0, q1, q0798; CHECK-NEXT: bx lr799entry:800 %cmp.i = fcmp olt <8 x half> %a, %b801 %sext.i = sext <8 x i1> %cmp.i to <8 x i16>802 ret <8 x i16> %sext.i803}804 805define dso_local <4 x half> @test_vcvt_n_f16_s16(<4 x i16> %a) {806; CHECKLABEL: test_vcvt_n_f16_s16:807; CHECK-LABEL: test_vcvt_n_f16_s16:808; CHECK: @ %bb.0: @ %entry809; CHECK-NEXT: vcvt.f16.s16 d0, d0, #2810; CHECK-NEXT: bx lr811entry:812 %vcvt_n1 = tail call <4 x half> @llvm.arm.neon.vcvtfxs2fp.v4f16.v4i16(<4 x i16> %a, i32 2)813 ret <4 x half> %vcvt_n1814}815 816declare <4 x half> @llvm.arm.neon.vcvtfxs2fp.v4f16.v4i16(<4 x i16>, i32) #2817 818define dso_local <8 x half> @test_vcvtq_n_f16_s16(<8 x i16> %a) {819; CHECKLABEL: test_vcvtq_n_f16_s16:820; CHECK-LABEL: test_vcvtq_n_f16_s16:821; CHECK: @ %bb.0: @ %entry822; CHECK-NEXT: vcvt.f16.s16 q0, q0, #2823; CHECK-NEXT: bx lr824entry:825 %vcvt_n1 = tail call <8 x half> @llvm.arm.neon.vcvtfxs2fp.v8f16.v8i16(<8 x i16> %a, i32 2)826 ret <8 x half> %vcvt_n1827}828 829declare <8 x half> @llvm.arm.neon.vcvtfxs2fp.v8f16.v8i16(<8 x i16>, i32) #2830 831define dso_local <4 x half> @test_vcvt_n_f16_u16(<4 x i16> %a) {832; CHECKLABEL: test_vcvt_n_f16_u16:833; CHECK-LABEL: test_vcvt_n_f16_u16:834; CHECK: @ %bb.0: @ %entry835; CHECK-NEXT: vcvt.f16.u16 d0, d0, #2836; CHECK-NEXT: bx lr837entry:838 %vcvt_n1 = tail call <4 x half> @llvm.arm.neon.vcvtfxu2fp.v4f16.v4i16(<4 x i16> %a, i32 2)839 ret <4 x half> %vcvt_n1840}841 842declare <4 x half> @llvm.arm.neon.vcvtfxu2fp.v4f16.v4i16(<4 x i16>, i32) #2843 844define dso_local <8 x half> @test_vcvtq_n_f16_u16(<8 x i16> %a) {845; CHECKLABEL: test_vcvtq_n_f16_u16:846; CHECK-LABEL: test_vcvtq_n_f16_u16:847; CHECK: @ %bb.0: @ %entry848; CHECK-NEXT: vcvt.f16.u16 q0, q0, #2849; CHECK-NEXT: bx lr850entry:851 %vcvt_n1 = tail call <8 x half> @llvm.arm.neon.vcvtfxu2fp.v8f16.v8i16(<8 x i16> %a, i32 2)852 ret <8 x half> %vcvt_n1853}854 855declare <8 x half> @llvm.arm.neon.vcvtfxu2fp.v8f16.v8i16(<8 x i16>, i32) #2856 857define dso_local <4 x i16> @test_vcvt_n_s16_f16(<4 x half> %a) {858; CHECKLABEL: test_vcvt_n_s16_f16:859; CHECK-LABEL: test_vcvt_n_s16_f16:860; CHECK: @ %bb.0: @ %entry861; CHECK-NEXT: vcvt.s16.f16 d0, d0, #2862; CHECK-NEXT: bx lr863entry:864 %vcvt_n1 = tail call <4 x i16> @llvm.arm.neon.vcvtfp2fxs.v4i16.v4f16(<4 x half> %a, i32 2)865 ret <4 x i16> %vcvt_n1866}867 868declare <4 x i16> @llvm.arm.neon.vcvtfp2fxs.v4i16.v4f16(<4 x half>, i32) #2869 870define dso_local <8 x i16> @test_vcvtq_n_s16_f16(<8 x half> %a) {871; CHECKLABEL: test_vcvtq_n_s16_f16:872; CHECK-LABEL: test_vcvtq_n_s16_f16:873; CHECK: @ %bb.0: @ %entry874; CHECK-NEXT: vcvt.s16.f16 q0, q0, #2875; CHECK-NEXT: bx lr876entry:877 %vcvt_n1 = tail call <8 x i16> @llvm.arm.neon.vcvtfp2fxs.v8i16.v8f16(<8 x half> %a, i32 2)878 ret <8 x i16> %vcvt_n1879}880 881declare <8 x i16> @llvm.arm.neon.vcvtfp2fxs.v8i16.v8f16(<8 x half>, i32) #2882 883define dso_local <4 x i16> @test_vcvt_n_u16_f16(<4 x half> %a) {884; CHECKLABEL: test_vcvt_n_u16_f16:885; CHECK-LABEL: test_vcvt_n_u16_f16:886; CHECK: @ %bb.0: @ %entry887; CHECK-NEXT: vcvt.u16.f16 d0, d0, #2888; CHECK-NEXT: bx lr889entry:890 %vcvt_n1 = tail call <4 x i16> @llvm.arm.neon.vcvtfp2fxu.v4i16.v4f16(<4 x half> %a, i32 2)891 ret <4 x i16> %vcvt_n1892}893 894declare <4 x i16> @llvm.arm.neon.vcvtfp2fxu.v4i16.v4f16(<4 x half>, i32) #2895 896define dso_local <8 x i16> @test_vcvtq_n_u16_f16(<8 x half> %a) {897; CHECKLABEL: test_vcvtq_n_u16_f16:898; CHECK-LABEL: test_vcvtq_n_u16_f16:899; CHECK: @ %bb.0: @ %entry900; CHECK-NEXT: vcvt.u16.f16 q0, q0, #2901; CHECK-NEXT: bx lr902entry:903 %vcvt_n1 = tail call <8 x i16> @llvm.arm.neon.vcvtfp2fxu.v8i16.v8f16(<8 x half> %a, i32 2)904 ret <8 x i16> %vcvt_n1905}906 907declare <8 x i16> @llvm.arm.neon.vcvtfp2fxu.v8i16.v8f16(<8 x half>, i32) #2908 909define dso_local <4 x half> @test_vmax_f16(<4 x half> %a, <4 x half> %b) {910; CHECKLABEL: test_vmax_f16:911; CHECK-LABEL: test_vmax_f16:912; CHECK: @ %bb.0: @ %entry913; CHECK-NEXT: vmax.f16 d0, d0, d1914; CHECK-NEXT: bx lr915entry:916 %vmax_v2.i = tail call <4 x half> @llvm.arm.neon.vmaxs.v4f16(<4 x half> %a, <4 x half> %b)917 ret <4 x half> %vmax_v2.i918}919 920define dso_local <8 x half> @test_vmaxq_f16(<8 x half> %a, <8 x half> %b) {921; CHECKLABEL: test_vmaxq_f16:922; CHECK-LABEL: test_vmaxq_f16:923; CHECK: @ %bb.0: @ %entry924; CHECK-NEXT: vmax.f16 q0, q0, q1925; CHECK-NEXT: bx lr926entry:927 %vmaxq_v2.i = tail call <8 x half> @llvm.arm.neon.vmaxs.v8f16(<8 x half> %a, <8 x half> %b)928 ret <8 x half> %vmaxq_v2.i929}930 931define dso_local <4 x half> @test_vmaxnm_f16(<4 x half> %a, <4 x half> %b) {932; CHECK-LABEL: test_vmaxnm_f16:933; CHECK: @ %bb.0: @ %entry934; CHECK-NEXT: vmaxnm.f16 d0, d0, d1935; CHECK-NEXT: bx lr936entry:937 %vmaxnm_v2.i = tail call <4 x half> @llvm.arm.neon.vmaxnm.v4f16(<4 x half> %a, <4 x half> %b)938 ret <4 x half> %vmaxnm_v2.i939}940 941define dso_local <8 x half> @test_vmaxnmq_f16(<8 x half> %a, <8 x half> %b) {942; CHECK-LABEL: test_vmaxnmq_f16:943; CHECK: @ %bb.0: @ %entry944; CHECK-NEXT: vmaxnm.f16 q0, q0, q1945; CHECK-NEXT: bx lr946entry:947 %vmaxnmq_v2.i = tail call <8 x half> @llvm.arm.neon.vmaxnm.v8f16(<8 x half> %a, <8 x half> %b)948 ret <8 x half> %vmaxnmq_v2.i949}950 951define dso_local <4 x half> @test_vmin_f16(<4 x half> %a, <4 x half> %b) {952; CHECK-LABEL: test_vmin_f16:953; CHECK: @ %bb.0: @ %entry954; CHECK-NEXT: vmin.f16 d0, d0, d1955; CHECK-NEXT: bx lr956entry:957 %vmin_v2.i = tail call <4 x half> @llvm.arm.neon.vmins.v4f16(<4 x half> %a, <4 x half> %b)958 ret <4 x half> %vmin_v2.i959}960 961define dso_local <8 x half> @test_vminq_f16(<8 x half> %a, <8 x half> %b) {962; CHECK-LABEL: test_vminq_f16:963; CHECK: @ %bb.0: @ %entry964; CHECK-NEXT: vmin.f16 q0, q0, q1965; CHECK-NEXT: bx lr966entry:967 %vminq_v2.i = tail call <8 x half> @llvm.arm.neon.vmins.v8f16(<8 x half> %a, <8 x half> %b)968 ret <8 x half> %vminq_v2.i969}970 971define dso_local <4 x half> @test_vminnm_f16(<4 x half> %a, <4 x half> %b) {972; CHECK-LABEL: test_vminnm_f16:973; CHECK: @ %bb.0: @ %entry974; CHECK-NEXT: vminnm.f16 d0, d0, d1975; CHECK-NEXT: bx lr976entry:977 %vminnm_v2.i = tail call <4 x half> @llvm.arm.neon.vminnm.v4f16(<4 x half> %a, <4 x half> %b)978 ret <4 x half> %vminnm_v2.i979}980 981define dso_local <8 x half> @test_vminnmq_f16(<8 x half> %a, <8 x half> %b) {982; CHECK-LABEL: test_vminnmq_f16:983; CHECK: @ %bb.0: @ %entry984; CHECK-NEXT: vminnm.f16 q0, q0, q1985; CHECK-NEXT: bx lr986entry:987 %vminnmq_v2.i = tail call <8 x half> @llvm.arm.neon.vminnm.v8f16(<8 x half> %a, <8 x half> %b)988 ret <8 x half> %vminnmq_v2.i989}990 991define dso_local <4 x half> @test_vmul_f16(<4 x half> %a, <4 x half> %b) {992; CHECKLABEL: test_vmul_f16:993; CHECK-LABEL: test_vmul_f16:994; CHECK: @ %bb.0: @ %entry995; CHECK-NEXT: vmul.f16 d0, d0, d1996; CHECK-NEXT: bx lr997entry:998 %mul.i = fmul <4 x half> %a, %b999 ret <4 x half> %mul.i1000}1001 1002define dso_local <8 x half> @test_vmulq_f16(<8 x half> %a, <8 x half> %b) {1003; CHECKLABEL: test_vmulq_f16:1004; CHECK-LABEL: test_vmulq_f16:1005; CHECK: @ %bb.0: @ %entry1006; CHECK-NEXT: vmul.f16 q0, q0, q11007; CHECK-NEXT: bx lr1008entry:1009 %mul.i = fmul <8 x half> %a, %b1010 ret <8 x half> %mul.i1011}1012 1013define dso_local <4 x half> @test_vpadd_f16(<4 x half> %a, <4 x half> %b) {1014; CHECKLABEL: test_vpadd_f16:1015; CHECK-LABEL: test_vpadd_f16:1016; CHECK: @ %bb.0: @ %entry1017; CHECK-NEXT: vpadd.f16 d0, d0, d11018; CHECK-NEXT: bx lr1019entry:1020 %vpadd_v2.i = tail call <4 x half> @llvm.arm.neon.vpadd.v4f16(<4 x half> %a, <4 x half> %b)1021 ret <4 x half> %vpadd_v2.i1022}1023 1024define dso_local <4 x half> @test_vpmax_f16(<4 x half> %a, <4 x half> %b) {1025; CHECKLABEL: test_vpmax_f16:1026; CHECK-LABEL: test_vpmax_f16:1027; CHECK: @ %bb.0: @ %entry1028; CHECK-NEXT: vpmax.f16 d0, d0, d11029; CHECK-NEXT: bx lr1030entry:1031 %vpmax_v2.i = tail call <4 x half> @llvm.arm.neon.vpmaxs.v4f16(<4 x half> %a, <4 x half> %b)1032 ret <4 x half> %vpmax_v2.i1033}1034 1035define dso_local <4 x half> @test_vpmin_f16(<4 x half> %a, <4 x half> %b) {1036; CHECKLABEL: test_vpmin_f16:1037; CHECK-LABEL: test_vpmin_f16:1038; CHECK: @ %bb.0: @ %entry1039; CHECK-NEXT: vpmin.f16 d0, d0, d11040; CHECK-NEXT: bx lr1041entry:1042 %vpmin_v2.i = tail call <4 x half> @llvm.arm.neon.vpmins.v4f16(<4 x half> %a, <4 x half> %b)1043 ret <4 x half> %vpmin_v2.i1044}1045 1046define dso_local <4 x half> @test_vrecps_f16(<4 x half> %a, <4 x half> %b) {1047; CHECKLABEL: test_vrecps_f16:1048; CHECK-LABEL: test_vrecps_f16:1049; CHECK: @ %bb.0: @ %entry1050; CHECK-NEXT: vrecps.f16 d0, d0, d11051; CHECK-NEXT: bx lr1052entry:1053 %vrecps_v2.i = tail call <4 x half> @llvm.arm.neon.vrecps.v4f16(<4 x half> %a, <4 x half> %b)1054 ret <4 x half> %vrecps_v2.i1055}1056 1057define dso_local <8 x half> @test_vrecpsq_f16(<8 x half> %a, <8 x half> %b) {1058; CHECKLABEL: test_vrecpsq_f16:1059; CHECK-LABEL: test_vrecpsq_f16:1060; CHECK: @ %bb.0: @ %entry1061; CHECK-NEXT: vrecps.f16 q0, q0, q11062; CHECK-NEXT: bx lr1063entry:1064 %vrecpsq_v2.i = tail call <8 x half> @llvm.arm.neon.vrecps.v8f16(<8 x half> %a, <8 x half> %b)1065 ret <8 x half> %vrecpsq_v2.i1066}1067 1068define dso_local <4 x half> @test_vrsqrts_f16(<4 x half> %a, <4 x half> %b) {1069; CHECKLABEL: test_vrsqrts_f16:1070; CHECK-LABEL: test_vrsqrts_f16:1071; CHECK: @ %bb.0: @ %entry1072; CHECK-NEXT: vrsqrts.f16 d0, d0, d11073; CHECK-NEXT: bx lr1074entry:1075 %vrsqrts_v2.i = tail call <4 x half> @llvm.arm.neon.vrsqrts.v4f16(<4 x half> %a, <4 x half> %b)1076 ret <4 x half> %vrsqrts_v2.i1077}1078 1079define dso_local <8 x half> @test_vrsqrtsq_f16(<8 x half> %a, <8 x half> %b) {1080; CHECKLABEL: test_vrsqrtsq_f16:1081; CHECK-LABEL: test_vrsqrtsq_f16:1082; CHECK: @ %bb.0: @ %entry1083; CHECK-NEXT: vrsqrts.f16 q0, q0, q11084; CHECK-NEXT: bx lr1085entry:1086 %vrsqrtsq_v2.i = tail call <8 x half> @llvm.arm.neon.vrsqrts.v8f16(<8 x half> %a, <8 x half> %b)1087 ret <8 x half> %vrsqrtsq_v2.i1088}1089 1090define dso_local <4 x half> @test_vsub_f16(<4 x half> %a, <4 x half> %b) {1091; CHECKLABEL: test_vsub_f16:1092; CHECK-LABEL: test_vsub_f16:1093; CHECK: @ %bb.0: @ %entry1094; CHECK-NEXT: vsub.f16 d0, d0, d11095; CHECK-NEXT: bx lr1096entry:1097 %sub.i = fsub <4 x half> %a, %b1098 ret <4 x half> %sub.i1099}1100 1101define dso_local <8 x half> @test_vsubq_f16(<8 x half> %a, <8 x half> %b) {1102; CHECKLABEL: test_vsubq_f16:1103; CHECK-LABEL: test_vsubq_f16:1104; CHECK: @ %bb.0: @ %entry1105; CHECK-NEXT: vsub.f16 q0, q0, q11106; CHECK-NEXT: bx lr1107entry:1108 %sub.i = fsub <8 x half> %a, %b1109 ret <8 x half> %sub.i1110}1111 1112define dso_local <4 x half> @test_vfma_f16(<4 x half> %a, <4 x half> %b, <4 x half> %c) {1113; CHECK-LABEL: test_vfma_f16:1114; CHECK: @ %bb.0: @ %entry1115; CHECK-NEXT: vfma.f16 d0, d1, d21116; CHECK-NEXT: bx lr1117entry:1118 %0 = tail call <4 x half> @llvm.fma.v4f16(<4 x half> %b, <4 x half> %c, <4 x half> %a)1119 ret <4 x half> %01120}1121 1122define dso_local <8 x half> @test_vfmaq_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c) {1123; CHECK-LABEL: test_vfmaq_f16:1124; CHECK: @ %bb.0: @ %entry1125; CHECK-NEXT: vfma.f16 q0, q1, q21126; CHECK-NEXT: bx lr1127entry:1128 %0 = tail call <8 x half> @llvm.fma.v8f16(<8 x half> %b, <8 x half> %c, <8 x half> %a)1129 ret <8 x half> %01130}1131 1132define dso_local <4 x half> @test_vfms_f16(<4 x half> %a, <4 x half> %b, <4 x half> %c) {1133; CHECK-LABEL: test_vfms_f16:1134; CHECK: @ %bb.0: @ %entry1135; CHECK-NEXT: vneg.f16 d16, d11136; CHECK-NEXT: vfma.f16 d0, d16, d21137; CHECK-NEXT: bx lr1138entry:1139 %sub.i = fsub <4 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b1140 %0 = tail call <4 x half> @llvm.fma.v4f16(<4 x half> %sub.i, <4 x half> %c, <4 x half> %a)1141 ret <4 x half> %01142}1143 1144define dso_local <8 x half> @test_vfmsq_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c) {1145; CHECK-LABEL: test_vfmsq_f16:1146; CHECK: @ %bb.0: @ %entry1147; CHECK-NEXT: vneg.f16 q8, q11148; CHECK-NEXT: vfma.f16 q0, q8, q21149; CHECK-NEXT: bx lr1150entry:1151 %sub.i = fsub <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b1152 %0 = tail call <8 x half> @llvm.fma.v8f16(<8 x half> %sub.i, <8 x half> %c, <8 x half> %a)1153 ret <8 x half> %01154}1155 1156define dso_local <4 x half> @test_vmul_lane_f16(<4 x half> %a, <4 x half> %b) {1157; CHECK-LABEL: test_vmul_lane_f16:1158; CHECK: @ %bb.0: @ %entry1159; CHECK-NEXT: vmul.f16 d0, d0, d1[3]1160; CHECK-NEXT: bx lr1161entry:1162 %shuffle = shufflevector <4 x half> %b, <4 x half> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>1163 %mul = fmul <4 x half> %shuffle, %a1164 ret <4 x half> %mul1165}1166 1167define dso_local <8 x half> @test_vmulq_lane_f16(<8 x half> %a, <4 x half> %b) {1168; CHECK-LABEL: test_vmulq_lane_f16:1169; CHECK: @ %bb.0: @ %entry1170; CHECK-NEXT: vmul.f16 q0, q0, d2[3]1171; CHECK-NEXT: bx lr1172entry:1173 %shuffle = shufflevector <4 x half> %b, <4 x half> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>1174 %mul = fmul <8 x half> %shuffle, %a1175 ret <8 x half> %mul1176}1177 1178define dso_local <4 x half> @test_vmul_n_f16(<4 x half> %a, float %b.coerce) {1179; CHECK-LABEL: test_vmul_n_f16:1180; CHECK: @ %bb.0: @ %entry1181; CHECK-NEXT: @ kill: def $s2 killed $s2 def $d11182; CHECK-NEXT: vmul.f16 d0, d0, d1[0]1183; CHECK-NEXT: bx lr1184entry:1185 %0 = bitcast float %b.coerce to i321186 %tmp.0.extract.trunc = trunc i32 %0 to i161187 %1 = bitcast i16 %tmp.0.extract.trunc to half1188 %vecinit = insertelement <4 x half> undef, half %1, i32 01189 %vecinit4 = shufflevector <4 x half> %vecinit, <4 x half> undef, <4 x i32> zeroinitializer1190 %mul = fmul <4 x half> %vecinit4, %a1191 ret <4 x half> %mul1192}1193 1194define dso_local <8 x half> @test_vmulq_n_f16(<8 x half> %a, float %b.coerce) {1195; CHECK-LABEL: test_vmulq_n_f16:1196; CHECK: @ %bb.0: @ %entry1197; CHECK-NEXT: @ kill: def $s4 killed $s4 def $d21198; CHECK-NEXT: vmul.f16 q0, q0, d2[0]1199; CHECK-NEXT: bx lr1200entry:1201 %0 = bitcast float %b.coerce to i321202 %tmp.0.extract.trunc = trunc i32 %0 to i161203 %1 = bitcast i16 %tmp.0.extract.trunc to half1204 %vecinit = insertelement <8 x half> undef, half %1, i32 01205 %vecinit8 = shufflevector <8 x half> %vecinit, <8 x half> undef, <8 x i32> zeroinitializer1206 %mul = fmul <8 x half> %vecinit8, %a1207 ret <8 x half> %mul1208}1209 1210define dso_local <4 x half> @test_vbsl_f16(<4 x i16> %a, <4 x half> %b, <4 x half> %c) {1211; CHECKLABEL: test_vbsl_f16:1212; CHECK-LABEL: test_vbsl_f16:1213; CHECK: @ %bb.0: @ %entry1214; CHECK-NEXT: vbsl d0, d1, d21215; CHECK-NEXT: bx lr1216entry:1217 %0 = bitcast <4 x i16> %a to <8 x i8>1218 %1 = bitcast <4 x half> %b to <8 x i8>1219 %2 = bitcast <4 x half> %c to <8 x i8>1220 %vbsl_v.i = tail call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> %0, <8 x i8> %1, <8 x i8> %2)1221 %3 = bitcast <8 x i8> %vbsl_v.i to <4 x half>1222 ret <4 x half> %31223}1224 1225define dso_local <8 x half> @test_vbslq_f16(<8 x i16> %a, <8 x half> %b, <8 x half> %c) {1226; CHECKLABEL: test_vbslq_f16:1227; CHECK-LABEL: test_vbslq_f16:1228; CHECK: @ %bb.0: @ %entry1229; CHECK-NEXT: vbsl q0, q1, q21230; CHECK-NEXT: bx lr1231entry:1232 %0 = bitcast <8 x i16> %a to <16 x i8>1233 %1 = bitcast <8 x half> %b to <16 x i8>1234 %2 = bitcast <8 x half> %c to <16 x i8>1235 %vbslq_v.i = tail call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2)1236 %3 = bitcast <16 x i8> %vbslq_v.i to <8 x half>1237 ret <8 x half> %31238}1239 1240define dso_local %struct.float16x4x2_t @test_vzip_f16(<4 x half> %a, <4 x half> %b) {1241; CHECK-LABEL: test_vzip_f16:1242; CHECK: @ %bb.0: @ %entry1243; CHECK-NEXT: vzip.16 d0, d11244; CHECK-NEXT: bx lr1245entry:1246 %vzip.i = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 5>1247 %vzip1.i = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 2, i32 6, i32 3, i32 7>1248 %.fca.0.0.insert = insertvalue %struct.float16x4x2_t undef, <4 x half> %vzip.i, 0, 01249 %.fca.0.1.insert = insertvalue %struct.float16x4x2_t %.fca.0.0.insert, <4 x half> %vzip1.i, 0, 11250 ret %struct.float16x4x2_t %.fca.0.1.insert1251}1252 1253define dso_local %struct.float16x8x2_t @test_vzipq_f16(<8 x half> %a, <8 x half> %b) {1254; CHECK-LABEL: test_vzipq_f16:1255; CHECK: @ %bb.0: @ %entry1256; CHECK-NEXT: vzip.16 q0, q11257; CHECK-NEXT: bx lr1258entry:1259 %vzip.i = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>1260 %vzip1.i = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>1261 %.fca.0.0.insert = insertvalue %struct.float16x8x2_t undef, <8 x half> %vzip.i, 0, 01262 %.fca.0.1.insert = insertvalue %struct.float16x8x2_t %.fca.0.0.insert, <8 x half> %vzip1.i, 0, 11263 ret %struct.float16x8x2_t %.fca.0.1.insert1264}1265 1266define dso_local %struct.float16x4x2_t @test_vuzp_f16(<4 x half> %a, <4 x half> %b) {1267; CHECK-LABEL: test_vuzp_f16:1268; CHECK: @ %bb.0: @ %entry1269; CHECK-NEXT: vuzp.16 d0, d11270; CHECK-NEXT: bx lr1271entry:1272 %vuzp.i = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6>1273 %vuzp1.i = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 1, i32 3, i32 5, i32 7>1274 %.fca.0.0.insert = insertvalue %struct.float16x4x2_t undef, <4 x half> %vuzp.i, 0, 01275 %.fca.0.1.insert = insertvalue %struct.float16x4x2_t %.fca.0.0.insert, <4 x half> %vuzp1.i, 0, 11276 ret %struct.float16x4x2_t %.fca.0.1.insert1277}1278 1279define dso_local %struct.float16x8x2_t @test_vuzpq_f16(<8 x half> %a, <8 x half> %b) {1280; CHECK-LABEL: test_vuzpq_f16:1281; CHECK: @ %bb.0: @ %entry1282; CHECK-NEXT: vuzp.16 q0, q11283; CHECK-NEXT: bx lr1284entry:1285 %vuzp.i = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>1286 %vuzp1.i = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1287 %.fca.0.0.insert = insertvalue %struct.float16x8x2_t undef, <8 x half> %vuzp.i, 0, 01288 %.fca.0.1.insert = insertvalue %struct.float16x8x2_t %.fca.0.0.insert, <8 x half> %vuzp1.i, 0, 11289 ret %struct.float16x8x2_t %.fca.0.1.insert1290}1291 1292define dso_local %struct.float16x4x2_t @test_vtrn_f16(<4 x half> %a, <4 x half> %b) {1293; CHECK-LABEL: test_vtrn_f16:1294; CHECK: @ %bb.0: @ %entry1295; CHECK-NEXT: vtrn.16 d0, d11296; CHECK-NEXT: bx lr1297entry:1298 %vtrn.i = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6>1299 %vtrn1.i = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 1, i32 5, i32 3, i32 7>1300 %.fca.0.0.insert = insertvalue %struct.float16x4x2_t undef, <4 x half> %vtrn.i, 0, 01301 %.fca.0.1.insert = insertvalue %struct.float16x4x2_t %.fca.0.0.insert, <4 x half> %vtrn1.i, 0, 11302 ret %struct.float16x4x2_t %.fca.0.1.insert1303}1304 1305define dso_local %struct.float16x8x2_t @test_vtrnq_f16(<8 x half> %a, <8 x half> %b) {1306; CHECK-LABEL: test_vtrnq_f16:1307; CHECK: @ %bb.0: @ %entry1308; CHECK-NEXT: vtrn.16 q0, q11309; CHECK-NEXT: bx lr1310entry:1311 %vtrn.i = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>1312 %vtrn1.i = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>1313 %.fca.0.0.insert = insertvalue %struct.float16x8x2_t undef, <8 x half> %vtrn.i, 0, 01314 %.fca.0.1.insert = insertvalue %struct.float16x8x2_t %.fca.0.0.insert, <8 x half> %vtrn1.i, 0, 11315 ret %struct.float16x8x2_t %.fca.0.1.insert1316}1317 1318define dso_local <4 x half> @test_vmov_n_f16(float %a.coerce) {1319; CHECK-LABEL: test_vmov_n_f16:1320; CHECK: @ %bb.0: @ %entry1321; CHECK-NEXT: @ kill: def $s0 killed $s0 def $d01322; CHECK-NEXT: vdup.16 d0, d0[0]1323; CHECK-NEXT: bx lr1324entry:1325 %0 = bitcast float %a.coerce to i321326 %tmp.0.extract.trunc = trunc i32 %0 to i161327 %1 = bitcast i16 %tmp.0.extract.trunc to half1328 %vecinit = insertelement <4 x half> undef, half %1, i32 01329 %vecinit4 = shufflevector <4 x half> %vecinit, <4 x half> undef, <4 x i32> zeroinitializer1330 ret <4 x half> %vecinit41331}1332 1333define dso_local <8 x half> @test_vmovq_n_f16(float %a.coerce) {1334; CHECK-LABEL: test_vmovq_n_f16:1335; CHECK: @ %bb.0: @ %entry1336; CHECK-NEXT: @ kill: def $s0 killed $s0 def $d01337; CHECK-NEXT: vdup.16 q0, d0[0]1338; CHECK-NEXT: bx lr1339entry:1340 %0 = bitcast float %a.coerce to i321341 %tmp.0.extract.trunc = trunc i32 %0 to i161342 %1 = bitcast i16 %tmp.0.extract.trunc to half1343 %vecinit = insertelement <8 x half> undef, half %1, i32 01344 %vecinit8 = shufflevector <8 x half> %vecinit, <8 x half> undef, <8 x i32> zeroinitializer1345 ret <8 x half> %vecinit81346}1347 1348define dso_local <4 x half> @test_vdup_n_f16(float %a.coerce) {1349; CHECK-LABEL: test_vdup_n_f16:1350; CHECK: @ %bb.0: @ %entry1351; CHECK-NEXT: @ kill: def $s0 killed $s0 def $d01352; CHECK-NEXT: vdup.16 d0, d0[0]1353; CHECK-NEXT: bx lr1354entry:1355 %0 = bitcast float %a.coerce to i321356 %tmp.0.extract.trunc = trunc i32 %0 to i161357 %1 = bitcast i16 %tmp.0.extract.trunc to half1358 %vecinit = insertelement <4 x half> undef, half %1, i32 01359 %vecinit4 = shufflevector <4 x half> %vecinit, <4 x half> undef, <4 x i32> zeroinitializer1360 ret <4 x half> %vecinit41361}1362 1363define dso_local <8 x half> @test_vdupq_n_f16(float %a.coerce) {1364; CHECK-LABEL: test_vdupq_n_f16:1365; CHECK: @ %bb.0: @ %entry1366; CHECK-NEXT: @ kill: def $s0 killed $s0 def $d01367; CHECK-NEXT: vdup.16 q0, d0[0]1368; CHECK-NEXT: bx lr1369entry:1370 %0 = bitcast float %a.coerce to i321371 %tmp.0.extract.trunc = trunc i32 %0 to i161372 %1 = bitcast i16 %tmp.0.extract.trunc to half1373 %vecinit = insertelement <8 x half> undef, half %1, i32 01374 %vecinit8 = shufflevector <8 x half> %vecinit, <8 x half> undef, <8 x i32> zeroinitializer1375 ret <8 x half> %vecinit81376}1377 1378define dso_local <4 x half> @test_vdup_lane_f16(<4 x half> %a) {1379; CHECK-LABEL: test_vdup_lane_f16:1380; CHECK: @ %bb.0: @ %entry1381; CHECK-NEXT: vdup.16 d0, d0[3]1382; CHECK-NEXT: bx lr1383entry:1384 %shuffle = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>1385 ret <4 x half> %shuffle1386}1387 1388define dso_local <8 x half> @test_vdupq_lane_f16(<4 x half> %a) {1389; CHECK-LABEL: test_vdupq_lane_f16:1390; CHECK: @ %bb.0: @ %entry1391; CHECK-NEXT: vdup.16 q0, d0[3]1392; CHECK-NEXT: bx lr1393entry:1394 %shuffle = shufflevector <4 x half> %a, <4 x half> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>1395 ret <8 x half> %shuffle1396}1397 1398define dso_local <4 x half> @test_vext_f16(<4 x half> %a, <4 x half> %b) {1399; CHECK-LABEL: test_vext_f16:1400; CHECK: @ %bb.0: @ %entry1401; CHECK-NEXT: vext.16 d0, d0, d1, #21402; CHECK-NEXT: bx lr1403entry:1404 %vext = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 2, i32 3, i32 4, i32 5>1405 ret <4 x half> %vext1406}1407 1408define dso_local <8 x half> @test_vextq_f16(<8 x half> %a, <8 x half> %b) {1409; CHECK-LABEL: test_vextq_f16:1410; CHECK: @ %bb.0: @ %entry1411; CHECK-NEXT: vext.16 q0, q0, q1, #51412; CHECK-NEXT: bx lr1413entry:1414 %vext = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12>1415 ret <8 x half> %vext1416}1417 1418define dso_local <4 x half> @test_vrev64_f16(<4 x half> %a) {1419; CHECK-LABEL: test_vrev64_f16:1420; CHECK: @ %bb.0: @ %entry1421; CHECK-NEXT: vrev64.16 d0, d01422; CHECK-NEXT: bx lr1423entry:1424 %shuffle.i = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>1425 ret <4 x half> %shuffle.i1426}1427 1428define dso_local <8 x half> @test_vrev64q_f16(<8 x half> %a) {1429; CHECK-LABEL: test_vrev64q_f16:1430; CHECK: @ %bb.0: @ %entry1431; CHECK-NEXT: vrev64.16 q0, q01432; CHECK-NEXT: bx lr1433entry:1434 %shuffle.i = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>1435 ret <8 x half> %shuffle.i1436}1437 1438define <4 x half> @test_vld_dup1_4xhalf(ptr %b) {1439; CHECK-LABEL: test_vld_dup1_4xhalf:1440; CHECK: @ %bb.0: @ %entry1441; CHECK-NEXT: vld1.16 {d0[]}, [r0:16]1442; CHECK-NEXT: bx lr1443 1444entry:1445 %b1 = load half, ptr %b, align 21446 %vecinit = insertelement <4 x half> undef, half %b1, i32 01447 %vecinit2 = insertelement <4 x half> %vecinit, half %b1, i32 11448 %vecinit3 = insertelement <4 x half> %vecinit2, half %b1, i32 21449 %vecinit4 = insertelement <4 x half> %vecinit3, half %b1, i32 31450 ret <4 x half> %vecinit41451}1452 1453define <8 x half> @test_vld_dup1_8xhalf(ptr %b) local_unnamed_addr {1454; CHECK-LABEL: test_vld_dup1_8xhalf:1455; CHECK: @ %bb.0: @ %entry1456; CHECK-NEXT: vld1.16 {d0[], d1[]}, [r0:16]1457; CHECK-NEXT: bx lr1458 1459entry:1460 %b1 = load half, ptr %b, align 21461 %vecinit = insertelement <8 x half> undef, half %b1, i32 01462 %vecinit8 = shufflevector <8 x half> %vecinit, <8 x half> undef, <8 x i32> zeroinitializer1463 ret <8 x half> %vecinit81464}1465 1466define <8 x half> @test_shufflevector8xhalf(<4 x half> %a) {1467; CHECK-LABEL: test_shufflevector8xhalf:1468; CHECK: @ %bb.0: @ %entry1469; CHECK-NEXT: @ kill: def $d0 killed $d0 def $q01470; CHECK-NEXT: vmov.f64 d1, d01471; CHECK-NEXT: bx lr1472 1473entry:1474 %r = shufflevector <4 x half> %a, <4 x half> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>1475 ret <8 x half> %r1476}1477 1478declare <4 x half> @llvm.fabs.v4f16(<4 x half>)1479declare <8 x half> @llvm.fabs.v8f16(<8 x half>)1480declare <4 x i16> @llvm.arm.neon.vcvtas.v4i16.v4f16(<4 x half>)1481declare <4 x i16> @llvm.arm.neon.vcvtau.v4i16.v4f16(<4 x half>)1482declare <8 x i16> @llvm.arm.neon.vcvtas.v8i16.v8f16(<8 x half>)1483declare <4 x i16> @llvm.arm.neon.vcvtms.v4i16.v4f16(<4 x half>)1484declare <8 x i16> @llvm.arm.neon.vcvtms.v8i16.v8f16(<8 x half>)1485declare <4 x i16> @llvm.arm.neon.vcvtmu.v4i16.v4f16(<4 x half>)1486declare <8 x i16> @llvm.arm.neon.vcvtmu.v8i16.v8f16(<8 x half>)1487declare <4 x i16> @llvm.arm.neon.vcvtns.v4i16.v4f16(<4 x half>)1488declare <8 x i16> @llvm.arm.neon.vcvtns.v8i16.v8f16(<8 x half>)1489declare <4 x i16> @llvm.arm.neon.vcvtnu.v4i16.v4f16(<4 x half>)1490declare <8 x i16> @llvm.arm.neon.vcvtnu.v8i16.v8f16(<8 x half>)1491declare <4 x i16> @llvm.arm.neon.vcvtps.v4i16.v4f16(<4 x half>)1492declare <8 x i16> @llvm.arm.neon.vcvtps.v8i16.v8f16(<8 x half>)1493declare <4 x i16> @llvm.arm.neon.vcvtpu.v4i16.v4f16(<4 x half>)1494declare <8 x i16> @llvm.arm.neon.vcvtpu.v8i16.v8f16(<8 x half>)1495declare <4 x half> @llvm.arm.neon.vrecpe.v4f16(<4 x half>)1496declare <8 x half> @llvm.arm.neon.vrecpe.v8f16(<8 x half>)1497declare <4 x half> @llvm.arm.neon.vrintz.v4f16(<4 x half>)1498declare <8 x half> @llvm.arm.neon.vrintz.v8f16(<8 x half>)1499declare <4 x half> @llvm.arm.neon.vrinta.v4f16(<4 x half>)1500declare <8 x half> @llvm.arm.neon.vrinta.v8f16(<8 x half>)1501declare <4 x half> @llvm.arm.neon.vrintm.v4f16(<4 x half>)1502declare <8 x half> @llvm.arm.neon.vrintm.v8f16(<8 x half>)1503declare <4 x half> @llvm.arm.neon.vrintn.v4f16(<4 x half>)1504declare <8 x half> @llvm.arm.neon.vrintn.v8f16(<8 x half>)1505declare <4 x half> @llvm.arm.neon.vrintp.v4f16(<4 x half>)1506declare <8 x half> @llvm.arm.neon.vrintp.v8f16(<8 x half>)1507declare <4 x half> @llvm.arm.neon.vrintx.v4f16(<4 x half>)1508declare <8 x half> @llvm.arm.neon.vrintx.v8f16(<8 x half>)1509declare <4 x half> @llvm.arm.neon.vrsqrte.v4f16(<4 x half>)1510declare <8 x half> @llvm.arm.neon.vrsqrte.v8f16(<8 x half>)1511declare <4 x half> @llvm.arm.neon.vabds.v4f16(<4 x half>, <4 x half>)1512declare <8 x half> @llvm.arm.neon.vabds.v8f16(<8 x half>, <8 x half>)1513declare <4 x i16> @llvm.arm.neon.vacge.v4i16.v4f16(<4 x half>, <4 x half>)1514declare <8 x i16> @llvm.arm.neon.vacge.v8i16.v8f16(<8 x half>, <8 x half>)1515declare <4 x i16> @llvm.arm.neon.vacgt.v4i16.v4f16(<4 x half>, <4 x half>)1516declare <8 x i16> @llvm.arm.neon.vacgt.v8i16.v8f16(<8 x half>, <8 x half>)1517declare <4 x half> @llvm.arm.neon.vmaxs.v4f16(<4 x half>, <4 x half>)1518declare <8 x half> @llvm.arm.neon.vmaxs.v8f16(<8 x half>, <8 x half>)1519declare <4 x half> @llvm.arm.neon.vmaxnm.v4f16(<4 x half>, <4 x half>)1520declare <8 x half> @llvm.arm.neon.vmaxnm.v8f16(<8 x half>, <8 x half>)1521declare <4 x half> @llvm.arm.neon.vmins.v4f16(<4 x half>, <4 x half>)1522declare <8 x half> @llvm.arm.neon.vmins.v8f16(<8 x half>, <8 x half>)1523declare <4 x half> @llvm.arm.neon.vminnm.v4f16(<4 x half>, <4 x half>)1524declare <8 x half> @llvm.arm.neon.vminnm.v8f16(<8 x half>, <8 x half>)1525declare <4 x half> @llvm.arm.neon.vpadd.v4f16(<4 x half>, <4 x half>)1526declare <4 x half> @llvm.arm.neon.vpmaxs.v4f16(<4 x half>, <4 x half>)1527declare <4 x half> @llvm.arm.neon.vpmins.v4f16(<4 x half>, <4 x half>)1528declare <4 x half> @llvm.arm.neon.vrecps.v4f16(<4 x half>, <4 x half>)1529declare <8 x half> @llvm.arm.neon.vrecps.v8f16(<8 x half>, <8 x half>)1530declare <4 x half> @llvm.arm.neon.vrsqrts.v4f16(<4 x half>, <4 x half>)1531declare <8 x half> @llvm.arm.neon.vrsqrts.v8f16(<8 x half>, <8 x half>)1532declare <4 x half> @llvm.fma.v4f16(<4 x half>, <4 x half>, <4 x half>)1533declare <8 x half> @llvm.fma.v8f16(<8 x half>, <8 x half>, <8 x half>)1534declare <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8>, <8 x i8>, <8 x i8>)1535declare <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)1536declare { <8 x half>, <8 x half> } @llvm.arm.neon.vld2lane.v8f16.p0(ptr, <8 x half>, <8 x half>, i32, i32)1537declare { <4 x half>, <4 x half> } @llvm.arm.neon.vld2lane.v4f16.p0(ptr, <4 x half>, <4 x half>, i32, i32)1538declare { <8 x half>, <8 x half>, <8 x half> } @llvm.arm.neon.vld3lane.v8f16.p0(ptr, <8 x half>, <8 x half>, <8 x half>, i32, i32)1539declare { <4 x half>, <4 x half>, <4 x half> } @llvm.arm.neon.vld3lane.v4f16.p0(ptr, <4 x half>, <4 x half>, <4 x half>, i32, i32)1540declare { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.arm.neon.vld4lane.v8f16.p0(ptr, <8 x half>, <8 x half>, <8 x half>, <8 x half>, i32, i32)1541declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.arm.neon.vld4lane.v4f16.p0(ptr, <4 x half>, <4 x half>, <4 x half>, <4 x half>, i32, i32)1542declare void @llvm.arm.neon.vst2lane.p0.v8f16(ptr, <8 x half>, <8 x half>, i32, i32)1543declare void @llvm.arm.neon.vst2lane.p0.v4f16(ptr, <4 x half>, <4 x half>, i32, i32)1544declare void @llvm.arm.neon.vst3lane.p0.v8f16(ptr, <8 x half>, <8 x half>, <8 x half>, i32, i32)1545declare void @llvm.arm.neon.vst3lane.p0.v4f16(ptr, <4 x half>, <4 x half>, <4 x half>, i32, i32)1546declare void @llvm.arm.neon.vst4lane.p0.v8f16(ptr, <8 x half>, <8 x half>, <8 x half>, <8 x half>, i32, i32)1547declare void @llvm.arm.neon.vst4lane.p0.v4f16(ptr, <4 x half>, <4 x half>, <4 x half>, <4 x half>, i32, i32)1548 1549define { <8 x half>, <8 x half> } @test_vld2q_lane_f16(ptr, <8 x half>, <8 x half>) {1550; CHECK-LABEL: test_vld2q_lane_f16:1551; CHECK: @ %bb.0: @ %entry1552; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1 def $q0_q11553; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1 def $q0_q11554; CHECK-NEXT: vld2.16 {d1[3], d3[3]}, [r0]1555; CHECK-NEXT: bx lr1556entry:1557 %3 = tail call { <8 x half>, <8 x half> } @llvm.arm.neon.vld2lane.v8f16.p0(ptr %0, <8 x half> %1, <8 x half> %2, i32 7, i32 2)1558 ret { <8 x half>, <8 x half> } %31559}1560 1561define { <4 x half>, <4 x half> } @test_vld2_lane_f16(ptr, <4 x half>, <4 x half>) {1562; CHECK-LABEL: test_vld2_lane_f16:1563; CHECK: @ %bb.0: @ %entry1564; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0 def $q01565; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0 def $q01566; CHECK-NEXT: vld2.16 {d0[3], d1[3]}, [r0]1567; CHECK-NEXT: bx lr1568entry:1569 %3 = tail call { <4 x half>, <4 x half> } @llvm.arm.neon.vld2lane.v4f16.p0(ptr %0, <4 x half> %1, <4 x half> %2, i32 3, i32 2)1570 ret { <4 x half>, <4 x half> } %31571}1572 1573define { <8 x half>, <8 x half>, <8 x half> } @test_vld3q_lane_f16(ptr, <8 x half>, <8 x half>, <8 x half>) {1574; CHECK-LABEL: test_vld3q_lane_f16:1575; CHECK: @ %bb.0: @ %entry1576; CHECK-NEXT: @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q31577; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q31578; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q31579; CHECK-NEXT: vld3.16 {d1[3], d3[3], d5[3]}, [r0]1580; CHECK-NEXT: bx lr1581entry:1582 %4 = tail call { <8 x half>, <8 x half>, <8 x half> } @llvm.arm.neon.vld3lane.v8f16.p0(ptr %0, <8 x half> %1, <8 x half> %2, <8 x half> %3, i32 7, i32 2)1583 ret { <8 x half>, <8 x half>, <8 x half> } %41584}1585 1586define { <4 x half>, <4 x half>, <4 x half> } @test_vld3_lane_f16(ptr, <4 x half>, <4 x half>, <4 x half>) {1587; CHECK-LABEL: test_vld3_lane_f16:1588; CHECK: @ %bb.0: @ %entry1589; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q11590; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0_q1 def $q0_q11591; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0_q1 def $q0_q11592; CHECK-NEXT: vld3.16 {d0[3], d1[3], d2[3]}, [r0]1593; CHECK-NEXT: bx lr1594entry:1595 %4 = tail call { <4 x half>, <4 x half>, <4 x half> } @llvm.arm.neon.vld3lane.v4f16.p0(ptr %0, <4 x half> %1, <4 x half> %2, <4 x half> %3, i32 3, i32 2)1596 ret { <4 x half>, <4 x half>, <4 x half> } %41597}1598define { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @test_vld4lane_v8f16_p0i8(ptr, <8 x half>, <8 x half>, <8 x half>, <8 x half>) {1599; CHECK-LABEL: test_vld4lane_v8f16_p0i8:1600; CHECK: @ %bb.0: @ %entry1601; CHECK-NEXT: @ kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q31602; CHECK-NEXT: @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q31603; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q31604; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q31605; CHECK-NEXT: vld4.16 {d1[3], d3[3], d5[3], d7[3]}, [r0]1606; CHECK-NEXT: bx lr1607entry:1608 %5 = tail call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.arm.neon.vld4lane.v8f16.p0(ptr %0, <8 x half> %1, <8 x half> %2, <8 x half> %3, <8 x half> %4, i32 7, i32 2)1609 ret { <8 x half>, <8 x half>, <8 x half>, <8 x half> } %51610}1611define { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @test_vld4lane_v4f16_p0i8(ptr, <4 x half>, <4 x half>, <4 x half>, <4 x half>) {1612; CHECK-LABEL: test_vld4lane_v4f16_p0i8:1613; CHECK: @ %bb.0: @ %entry1614; CHECK-NEXT: @ kill: def $d3 killed $d3 killed $q0_q1 def $q0_q11615; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q11616; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0_q1 def $q0_q11617; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0_q1 def $q0_q11618; CHECK-NEXT: vld4.16 {d0[3], d1[3], d2[3], d3[3]}, [r0]1619; CHECK-NEXT: bx lr1620entry:1621 %5 = tail call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.arm.neon.vld4lane.v4f16.p0(ptr %0, <4 x half> %1, <4 x half> %2, <4 x half> %3, <4 x half> %4, i32 3, i32 2)1622 ret { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %51623}1624define void @test_vst2lane_p0i8_v8f16(ptr, <8 x half>, <8 x half>) {1625; CHECK-LABEL: test_vst2lane_p0i8_v8f16:1626; CHECK: @ %bb.0: @ %entry1627; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1 def $q0_q11628; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1 def $q0_q11629; CHECK-NEXT: vst2.16 {d0[0], d2[0]}, [r0]1630; CHECK-NEXT: bx lr1631entry:1632 tail call void @llvm.arm.neon.vst2lane.p0.v8f16(ptr %0, <8 x half> %1, <8 x half> %2, i32 0, i32 1)1633 ret void1634}1635define void @test_vst2lane_p0i8_v4f16(ptr, <4 x half>, <4 x half>) {1636; CHECK-LABEL: test_vst2lane_p0i8_v4f16:1637; CHECK: @ %bb.0: @ %entry1638; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0 def $q01639; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0 def $q01640; CHECK-NEXT: vst2.16 {d0[0], d1[0]}, [r0:32]1641; CHECK-NEXT: bx lr1642entry:1643 tail call void @llvm.arm.neon.vst2lane.p0.v4f16(ptr %0, <4 x half> %1, <4 x half> %2, i32 0, i32 0)1644 ret void1645}1646define void @test_vst3lane_p0i8_v8f16(ptr, <8 x half>, <8 x half>, <8 x half>) {1647; CHECK-LABEL: test_vst3lane_p0i8_v8f16:1648; CHECK: @ %bb.0: @ %entry1649; CHECK-NEXT: @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q31650; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q31651; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q31652; CHECK-NEXT: vst3.16 {d0[0], d2[0], d4[0]}, [r0]1653; CHECK-NEXT: bx lr1654entry:1655 tail call void @llvm.arm.neon.vst3lane.p0.v8f16(ptr %0, <8 x half> %1, <8 x half> %2, <8 x half> %3, i32 0, i32 0)1656 ret void1657}1658define void @test_vst3lane_p0i8_v4f16(ptr, <4 x half>, <4 x half>, <4 x half>) {1659; CHECK-LABEL: test_vst3lane_p0i8_v4f16:1660; CHECK: @ %bb.0: @ %entry1661; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q11662; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0_q1 def $q0_q11663; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0_q1 def $q0_q11664; CHECK-NEXT: vst3.16 {d0[0], d1[0], d2[0]}, [r0]1665; CHECK-NEXT: bx lr1666entry:1667 tail call void @llvm.arm.neon.vst3lane.p0.v4f16(ptr %0, <4 x half> %1, <4 x half> %2, <4 x half> %3, i32 0, i32 0)1668 ret void1669}1670define void @test_vst4lane_p0i8_v8f16(ptr, <8 x half>, <8 x half>, <8 x half>, <8 x half>) {1671; CHECK-LABEL: test_vst4lane_p0i8_v8f16:1672; CHECK: @ %bb.0: @ %entry1673; CHECK-NEXT: @ kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q31674; CHECK-NEXT: @ kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q31675; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q31676; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q31677; CHECK-NEXT: vst4.16 {d0[0], d2[0], d4[0], d6[0]}, [r0:64]1678; CHECK-NEXT: bx lr1679entry:1680 tail call void @llvm.arm.neon.vst4lane.p0.v8f16(ptr %0, <8 x half> %1, <8 x half> %2, <8 x half> %3, <8 x half> %4, i32 0, i32 0)1681 ret void1682}1683define void @test_vst4lane_p0i8_v4f16(ptr, <4 x half>, <4 x half>, <4 x half>, <4 x half>) {1684; CHECK-LABEL: test_vst4lane_p0i8_v4f16:1685; CHECK: @ %bb.0: @ %entry1686; CHECK-NEXT: @ kill: def $d3 killed $d3 killed $q0_q1 def $q0_q11687; CHECK-NEXT: @ kill: def $d2 killed $d2 killed $q0_q1 def $q0_q11688; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0_q1 def $q0_q11689; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0_q1 def $q0_q11690; CHECK-NEXT: vst4.16 {d0[0], d1[0], d2[0], d3[0]}, [r0:64]1691; CHECK-NEXT: bx lr1692entry:1693 tail call void @llvm.arm.neon.vst4lane.p0.v4f16(ptr %0, <4 x half> %1, <4 x half> %2, <4 x half> %3, <4 x half> %4, i32 0, i32 0)1694 ret void1695}1696