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1; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE2; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabihf | FileCheck %s --check-prefix=CHECK-THUMB --check-prefix=CHECK-THUMB-LE3; RUN: llc < %s -mtriple=armebv7 -target-abi apcs | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE4; RUN: llc < %s -mtriple=thumbebv7-none-linux-gnueabihf | FileCheck %s --check-prefix=CHECK-THUMB --check-prefix=CHECK-THUMB-BE5; RUN: llc < %s -mtriple=armv7m--none-eabi | FileCheck %s --check-prefix=CHECK-M6; RUN: llc < %s -mtriple=armv8m--none-eabi | FileCheck %s --check-prefix=CHECK-M7 8define i64 @test1(ptr %ptr, i64 %val) {9; CHECK-LABEL: test1:10; CHECK: dmb {{ish$}}11; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]12; CHECK-LE: adds [[REG3:(r[0-9]?[02468])]], [[REG1]]13; CHECK-LE: adc [[REG4:(r[0-9]?[13579])]], [[REG2]]14; CHECK-BE: adds [[REG4:(r[0-9]?[13579])]], [[REG2]]15; CHECK-BE: adc [[REG3:(r[0-9]?[02468])]], [[REG1]]16; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]17; CHECK: cmp18; CHECK: bne19; CHECK: dmb {{ish$}}20 21; CHECK-THUMB-LABEL: test1:22; CHECK-THUMB: dmb {{ish$}}23; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]24; CHECK-THUMB-LE: adds.w [[REG3:[a-z0-9]+]], [[REG1]]25; CHECK-THUMB-LE: adc.w [[REG4:[a-z0-9]+]], [[REG2]]26; CHECK-THUMB-BE: adds.w [[REG4:[a-z0-9]+]], [[REG2]]27; CHECK-THUMB-BE: adc.w [[REG3:[a-z0-9]+]], [[REG1]]28; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]29; CHECK-THUMB: cmp30; CHECK-THUMB: bne31; CHECK-THUMB: dmb {{ish$}}32 33; CHECK-M: __atomic_fetch_add_834 35 %r = atomicrmw add ptr %ptr, i64 %val seq_cst36 ret i64 %r37}38 39define i64 @test2(ptr %ptr, i64 %val) {40; CHECK-LABEL: test2:41; CHECK: dmb {{ish$}}42; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]43; CHECK-LE: subs [[REG3:(r[0-9]?[02468])]], [[REG1]]44; CHECK-LE: sbc [[REG4:(r[0-9]?[13579])]], [[REG2]]45; CHECK-BE: subs [[REG4:(r[0-9]?[13579])]], [[REG2]]46; CHECK-BE: sbc [[REG3:(r[0-9]?[02468])]], [[REG1]]47; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]48; CHECK: cmp49; CHECK: bne50; CHECK: dmb {{ish$}}51 52; CHECK-THUMB-LABEL: test2:53; CHECK-THUMB: dmb {{ish$}}54; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]55; CHECK-THUMB-LE: subs.w [[REG3:[a-z0-9]+]], [[REG1]]56; CHECK-THUMB-LE: sbc.w [[REG4:[a-z0-9]+]], [[REG2]]57; CHECK-THUMB-BE: subs.w [[REG4:[a-z0-9]+]], [[REG2]]58; CHECK-THUMB-BE: sbc.w [[REG3:[a-z0-9]+]], [[REG1]]59; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]60; CHECK-THUMB: cmp61; CHECK-THUMB: bne62; CHECK-THUMB: dmb {{ish$}}63 64; CHECK-M: __atomic_fetch_sub_865 66 %r = atomicrmw sub ptr %ptr, i64 %val seq_cst67 ret i64 %r68}69 70define i64 @test3(ptr %ptr, i64 %val) {71; CHECK-LABEL: test3:72; CHECK: dmb {{ish$}}73; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]74; CHECK-LE-DAG: and [[REG3:(r[0-9]?[02468])]], [[REG1]],75; CHECK-LE-DAG: and [[REG4:(r[0-9]?[13579])]], [[REG2]],76; CHECK-BE-DAG: and [[REG4:(r[0-9]?[13579])]], [[REG2]],77; CHECK-BE-DAG: and [[REG3:(r[0-9]?[02468])]], [[REG1]],78; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]79; CHECK: cmp80; CHECK: bne81; CHECK: dmb {{ish$}}82 83; CHECK-THUMB-LABEL: test3:84; CHECK-THUMB: dmb {{ish$}}85; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]86; CHECK-THUMB-LE-DAG: and.w [[REG3:[a-z0-9]+]], [[REG1]],87; CHECK-THUMB-LE-DAG: and.w [[REG4:[a-z0-9]+]], [[REG2]],88; CHECK-THUMB-BE-DAG: and.w [[REG4:[a-z0-9]+]], [[REG2]],89; CHECK-THUMB-BE-DAG: and.w [[REG3:[a-z0-9]+]], [[REG1]],90; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]91; CHECK-THUMB: cmp92; CHECK-THUMB: bne93; CHECK-THUMB: dmb {{ish$}}94 95; CHECK-M: _atomic_fetch_and_896 97 %r = atomicrmw and ptr %ptr, i64 %val seq_cst98 ret i64 %r99}100 101define i64 @test4(ptr %ptr, i64 %val) {102; CHECK-LABEL: test4:103; CHECK: dmb {{ish$}}104; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]105; CHECK-LE-DAG: orr [[REG3:(r[0-9]?[02468])]], [[REG1]],106; CHECK-LE-DAG: orr [[REG4:(r[0-9]?[13579])]], [[REG2]],107; CHECK-BE-DAG: orr [[REG4:(r[0-9]?[13579])]], [[REG2]],108; CHECK-BE-DAG: orr [[REG3:(r[0-9]?[02468])]], [[REG1]],109; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]110; CHECK: cmp111; CHECK: bne112; CHECK: dmb {{ish$}}113 114; CHECK-THUMB-LABEL: test4:115; CHECK-THUMB: dmb {{ish$}}116; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]117; CHECK-THUMB-LE-DAG: orr.w [[REG3:[a-z0-9]+]], [[REG1]],118; CHECK-THUMB-LE-DAG: orr.w [[REG4:[a-z0-9]+]], [[REG2]],119; CHECK-THUMB-BE-DAG: orr.w [[REG4:[a-z0-9]+]], [[REG2]],120; CHECK-THUMB-BE-DAG: orr.w [[REG3:[a-z0-9]+]], [[REG1]],121; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]122; CHECK-THUMB: cmp123; CHECK-THUMB: bne124; CHECK-THUMB: dmb {{ish$}}125 126; CHECK-M: __atomic_fetch_or_8127 128 %r = atomicrmw or ptr %ptr, i64 %val seq_cst129 ret i64 %r130}131 132define i64 @test5(ptr %ptr, i64 %val) {133; CHECK-LABEL: test5:134; CHECK: dmb {{ish$}}135; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]136; CHECK-LE-DAG: eor [[REG3:(r[0-9]?[02468])]], [[REG1]],137; CHECK-LE-DAG: eor [[REG4:(r[0-9]?[13579])]], [[REG2]],138; CHECK-BE-DAG: eor [[REG4:(r[0-9]?[13579])]], [[REG2]],139; CHECK-BE-DAG: eor [[REG3:(r[0-9]?[02468])]], [[REG1]],140; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]141; CHECK: cmp142; CHECK: bne143; CHECK: dmb {{ish$}}144 145; CHECK-THUMB-LABEL: test5:146; CHECK-THUMB: dmb {{ish$}}147; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]148; CHECK-THUMB-LE-DAG: eor.w [[REG3:[a-z0-9]+]], [[REG1]],149; CHECK-THUMB-LE-DAG: eor.w [[REG4:[a-z0-9]+]], [[REG2]],150; CHECK-THUMB-BE-DAG: eor.w [[REG4:[a-z0-9]+]], [[REG2]],151; CHECK-THUMB-BE-DAG: eor.w [[REG3:[a-z0-9]+]], [[REG1]],152; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]153; CHECK-THUMB: cmp154; CHECK-THUMB: bne155; CHECK-THUMB: dmb {{ish$}}156 157; CHECK-M: __atomic_fetch_xor_8158 159 %r = atomicrmw xor ptr %ptr, i64 %val seq_cst160 ret i64 %r161}162 163define i64 @test6(ptr %ptr, i64 %val) {164; CHECK-LABEL: test6:165; CHECK: dmb {{ish$}}166; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]167; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}168; CHECK: cmp169; CHECK: bne170; CHECK: dmb {{ish$}}171 172; CHECK-THUMB-LABEL: test6:173; CHECK-THUMB: dmb {{ish$}}174; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]175; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}176; CHECK-THUMB: cmp177; CHECK-THUMB: bne178; CHECK-THUMB: dmb {{ish$}}179 180; CHECK-M: __atomic_exchange_8181 182 %r = atomicrmw xchg ptr %ptr, i64 %val seq_cst183 ret i64 %r184}185 186define i64 @test7(ptr %ptr, i64 %val1, i64 %val2) {187; CHECK-LABEL: test7:188; CHECK-DAG: mov [[VAL1LO:r[0-9]+]], r1189; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]190; CHECK-LE-DAG: eor [[MISMATCH_LO:.*]], [[REG1]], [[VAL1LO]]191; CHECK-LE-DAG: eor [[MISMATCH_HI:.*]], [[REG2]], r2192; CHECK-BE-DAG: eor [[MISMATCH_LO:.*]], [[REG2]], r2193; CHECK-BE-DAG: eor [[MISMATCH_HI:.*]], [[REG1]], r1194; CHECK: orrs {{r[0-9]+}}, [[MISMATCH_LO]], [[MISMATCH_HI]]195; CHECK: bne196; CHECK-DAG: dmb {{ish$}}197; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}198; CHECK: cmp199; CHECK: beq200; CHECK: dmb {{ish$}}201 202; CHECK-THUMB-LABEL: test7:203; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]204; CHECK-THUMB-LE-DAG: eor.w [[MISMATCH_LO:[a-z0-9]+]], [[REG1]], r2205; CHECK-THUMB-LE-DAG: eor.w [[MISMATCH_HI:[a-z0-9]+]], [[REG2]], r3206; CHECK-THUMB-BE-DAG: eor.w [[MISMATCH_HI:[a-z0-9]+]], [[REG1]], r2207; CHECK-THUMB-BE-DAG: eor.w [[MISMATCH_LO:[a-z0-9]+]], [[REG2]], r3208; CHECK-THUMB-LE: orrs.w {{.*}}, [[MISMATCH_LO]], [[MISMATCH_HI]]209; CHECK-THUMB: bne210; CHECK-THUMB: dmb {{ish$}}211; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}212; CHECK-THUMB: cmp213; CHECK-THUMB: beq214; CHECK-THUMB: dmb {{ish$}}215 216; CHECK-M: __atomic_compare_exchange_8217 218 %pair = cmpxchg ptr %ptr, i64 %val1, i64 %val2 seq_cst seq_cst219 %r = extractvalue { i64, i1 } %pair, 0220 ret i64 %r221}222 223; Compiles down to a single ldrexd, except on M class devices where ldrexd224; isn't supported.225define i64 @test8(ptr %ptr) {226; CHECK-LABEL: test8:227; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]228; CHECK-NOT: strexd229; CHECK: clrex230; CHECK-NOT: strexd231; CHECK: dmb {{ish$}}232 233; CHECK-THUMB-LABEL: test8:234; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]235; CHECK-THUMB-NOT: strexd236; CHECK-THUMB: clrex237; CHECK-THUMB-NOT: strexd238; CHECK-THUMB: dmb {{ish$}}239 240; CHECK-M: __atomic_load_8241 242 %r = load atomic i64, ptr %ptr seq_cst, align 8243 ret i64 %r244}245 246; Compiles down to atomicrmw xchg; there really isn't any more efficient247; way to write it. Except on M class devices, where ldrexd/strexd aren't248; supported.249define void @test9(ptr %ptr, i64 %val) {250; CHECK-LABEL: test9:251; CHECK: dmb {{ish$}}252; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]253; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}254; CHECK: cmp255; CHECK: bne256; CHECK: dmb {{ish$}}257 258; CHECK-THUMB-LABEL: test9:259; CHECK-THUMB: dmb {{ish$}}260; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]261; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}262; CHECK-THUMB: cmp263; CHECK-THUMB: bne264; CHECK-THUMB: dmb {{ish$}}265 266; CHECK-M: __atomic_store_8267 268 store atomic i64 %val, ptr %ptr seq_cst, align 8269 ret void270}271 272define i64 @test10(ptr %ptr, i64 %val) {273; CHECK-LABEL: test10:274; CHECK: dmb {{ish$}}275; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]276; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2277; CHECK-LE: subs {{[^,]+}}, r1, [[REG1]]278; CHECK-BE: subs {{[^,]+}}, r2, [[REG2]]279; CHECK-LE: sbcs {{[^,]+}}, r2, [[REG2]]280; CHECK-BE: sbcs {{[^,]+}}, r1, [[REG1]]281; CHECK: movge [[OUT_HI]], [[REG2]]282; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1283; CHECK: movge [[OUT_LO]], [[REG1]]284; CHECK: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]285; CHECK: cmp286; CHECK: bne287; CHECK: dmb {{ish$}}288 289; CHECK-THUMB-LABEL: test10:290; CHECK-THUMB: dmb {{ish$}}291; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]292; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2293; CHECK-THUMB-LE: subs.w {{[^,]+}}, r2, [[REG1]]294; CHECK-THUMB-BE: subs.w {{[^,]+}}, r3, [[REG2]]295; CHECK-THUMB-LE: sbcs.w {{[^,]+}}, r3, [[REG2]]296; CHECK-THUMB-BE: sbcs.w {{[^,]+}}, r2, [[REG1]]297; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3298; CHECK-THUMB: itt ge299; CHECK-THUMB: movge [[OUT_HI]], [[REG2]]300; CHECK-THUMB: movge [[OUT_LO]], [[REG1]]301; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]302; CHECK-THUMB: cmp303; CHECK-THUMB: bne304; CHECK-THUMB: dmb {{ish$}}305 306; CHECK-M: __atomic_compare_exchange_8307 308 %r = atomicrmw min ptr %ptr, i64 %val seq_cst309 ret i64 %r310}311 312define i64 @test11(ptr %ptr, i64 %val) {313; CHECK-LABEL: test11:314; CHECK: dmb {{ish$}}315; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]316; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2317; CHECK-LE: subs {{[^,]+}}, r1, [[REG1]]318; CHECK-BE: subs {{[^,]+}}, r2, [[REG2]]319; CHECK-LE: sbcs {{[^,]+}}, r2, [[REG2]]320; CHECK-BE: sbcs {{[^,]+}}, r1, [[REG1]]321; CHECK: movhs [[OUT_HI]], [[REG2]]322; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1323; CHECK: movhs [[OUT_LO]], [[REG1]]324; CHECK: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]325; CHECK: cmp326; CHECK: bne327; CHECK: dmb {{ish$}}328 329; CHECK-THUMB-LABEL: test11:330; CHECK-THUMB: dmb {{ish$}}331; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]332; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2333; CHECK-THUMB-LE: subs.w {{[^,]+}}, r2, [[REG1]]334; CHECK-THUMB-BE: subs.w {{[^,]+}}, r3, [[REG2]]335; CHECK-THUMB-LE: sbcs.w {{[^,]+}}, r3, [[REG2]]336; CHECK-THUMB-BE: sbcs.w {{[^,]+}}, r2, [[REG1]]337; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3338; CHECK-THUMB: itt hs339; CHECK-THUMB: movhs [[OUT_HI]], [[REG2]]340; CHECK-THUMB: movhs [[OUT_LO]], [[REG1]]341; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]342; CHECK-THUMB: cmp343; CHECK-THUMB: bne344; CHECK-THUMB: dmb {{ish$}}345 346; CHECK-M: __atomic_compare_exchange_8347 348 %r = atomicrmw umin ptr %ptr, i64 %val seq_cst349 ret i64 %r350}351 352define i64 @test12(ptr %ptr, i64 %val) {353; CHECK-LABEL: test12:354; CHECK: dmb {{ish$}}355; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]356; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2357; CHECK-LE: subs {{[^,]+}}, r1, [[REG1]]358; CHECK-BE: subs {{[^,]+}}, r2, [[REG2]]359; CHECK-LE: sbcs {{[^,]+}}, r2, [[REG2]]360; CHECK-BE: sbcs {{[^,]+}}, r1, [[REG1]]361; CHECK: movlt [[OUT_HI]], [[REG2]]362; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1363; CHECK: movlt [[OUT_LO]], [[REG1]]364; CHECK: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]365; CHECK: cmp366; CHECK: bne367; CHECK: dmb {{ish$}}368 369; CHECK-THUMB-LABEL: test12:370; CHECK-THUMB: dmb {{ish$}}371; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]372; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2373; CHECK-THUMB-LE: subs.w {{[^,]+}}, r2, [[REG1]]374; CHECK-THUMB-BE: subs.w {{[^,]+}}, r3, [[REG2]]375; CHECK-THUMB-LE: sbcs.w {{[^,]+}}, r3, [[REG2]]376; CHECK-THUMB-BE: sbcs.w {{[^,]+}}, r2, [[REG1]]377; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3378; CHECK-THUMB: itt lt379; CHECK-THUMB: movlt [[OUT_HI]], [[REG2]]380; CHECK-THUMB: movlt [[OUT_LO]], [[REG1]]381; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]382; CHECK-THUMB: cmp383; CHECK-THUMB: bne384; CHECK-THUMB: dmb {{ish$}}385 386; CHECK-M: __atomic_compare_exchange_8387 388 %r = atomicrmw max ptr %ptr, i64 %val seq_cst389 ret i64 %r390}391 392define i64 @test13(ptr %ptr, i64 %val) {393; CHECK-LABEL: test13:394; CHECK: dmb {{ish$}}395; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]396; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2397; CHECK-LE: subs {{[^,]+}}, r1, [[REG1]]398; CHECK-BE: subs {{[^,]+}}, r2, [[REG2]]399; CHECK-LE: sbcs {{[^,]+}}, r2, [[REG2]]400; CHECK-BE: sbcs {{[^,]+}}, r1, [[REG1]]401; CHECK: movlo [[OUT_HI]], [[REG2]]402; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1403; CHECK: movlo [[OUT_LO]], [[REG1]]404; CHECK: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]405; CHECK: cmp406; CHECK: bne407; CHECK: dmb {{ish$}}408 409; CHECK-THUMB-LABEL: test13:410; CHECK-THUMB: dmb {{ish$}}411; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]412; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2413; CHECK-THUMB-LE: subs.w {{[^,]+}}, r2, [[REG1]]414; CHECK-THUMB-BE: subs.w {{[^,]+}}, r3, [[REG2]]415; CHECK-THUMB-LE: sbcs.w {{[^,]+}}, r3, [[REG2]]416; CHECK-THUMB-BE: sbcs.w {{[^,]+}}, r2, [[REG1]]417; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3418; CHECK-THUMB: itt lo419; CHECK-THUMB: movlo [[OUT_HI]], [[REG2]]420; CHECK-THUMB: movlo [[OUT_LO]], [[REG1]]421; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]422; CHECK-THUMB: cmp423; CHECK-THUMB: bne424; CHECK-THUMB: dmb {{ish$}}425 426; CHECK-M: __atomic_compare_exchange_8427 428 %r = atomicrmw umax ptr %ptr, i64 %val seq_cst429 ret i64 %r430}431 432