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1; RUN: llc -mtriple=thumbv7-none-eabi -mcpu=cortex-m33 -verify-machineinstrs -o - %s | FileCheck %s2 3define i8 @test_atomic_load_add_i8(i8 %offset) nounwind {4; CHECK-LABEL: test_atomic_load_add_i8:5 %old = atomicrmw add ptr @var8, i8 %offset seq_cst6; CHECK-NOT: dmb7; CHECK-NOT: mcr8; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var89; CHECK: movt r[[ADDR]], :upper16:var810 11; CHECK: .LBB{{[0-9]+}}_1:12; CHECK: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]]13 ; r0 below is a reasonable guess but could change: it certainly comes into the14 ; function there.15; CHECK-NEXT: add{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r016; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]17; CHECK-NEXT: cmp [[STATUS]], #018; CHECK-NEXT: bne .LBB{{[0-9]+}}_119; CHECK-NOT: dmb20; CHECK-NOT: mcr21 22; CHECK: mov r0, r[[OLD]]23 ret i8 %old24}25 26define i16 @test_atomic_load_add_i16(i16 %offset) nounwind {27; CHECK-LABEL: test_atomic_load_add_i16:28 %old = atomicrmw add ptr @var16, i16 %offset acquire29; CHECK-NOT: dmb30; CHECK-NOT: mcr31; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var1632; CHECK: movt r[[ADDR]], :upper16:var1633 34; CHECK: .LBB{{[0-9]+}}_1:35; CHECK: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]]36 ; r0 below is a reasonable guess but could change: it certainly comes into the37 ; function there.38; CHECK-NEXT: add{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r039; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]40; CHECK-NEXT: cmp [[STATUS]], #041; CHECK-NEXT: bne .LBB{{[0-9]+}}_142; CHECK-NOT: dmb43; CHECK-NOT: mcr44 45; CHECK: mov r0, r[[OLD]]46 ret i16 %old47}48 49define i32 @test_atomic_load_add_i32(i32 %offset) nounwind {50; CHECK-LABEL: test_atomic_load_add_i32:51 %old = atomicrmw add ptr @var32, i32 %offset release52; CHECK-NOT: dmb53; CHECK-NOT: mcr54; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var3255; CHECK: movt r[[ADDR]], :upper16:var3256 57; CHECK: .LBB{{[0-9]+}}_1:58; CHECK: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]]59 ; r0 below is a reasonable guess but could change: it certainly comes into the60 ; function there.61; CHECK-NEXT: add{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r062; CHECK-NEXT: stlex [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]63; CHECK-NEXT: cmp [[STATUS]], #064; CHECK-NEXT: bne .LBB{{[0-9]+}}_165; CHECK-NOT: dmb66; CHECK-NOT: mcr67 68; CHECK: mov r0, r[[OLD]]69 ret i32 %old70}71 72define void @test_atomic_load_add_i64(i64 %offset) nounwind {73; CHECK-LABEL: test_atomic_load_add_i64:74; CHECK: bl __atomic_fetch_add_875 %old = atomicrmw add ptr @var64, i64 %offset monotonic76 store i64 %old, ptr @var6477 ret void78}79 80define i8 @test_load_acquire_i8(ptr %ptr) {81; CHECK-LABEL: test_load_acquire_i8:82; CHECK: ldab r0, [r0]83 %val = load atomic i8, ptr %ptr seq_cst, align 184 ret i8 %val85}86 87define i16 @test_load_acquire_i16(ptr %ptr) {88; CHECK-LABEL: test_load_acquire_i16:89; CHECK: ldah r0, [r0]90 %val = load atomic i16, ptr %ptr acquire, align 291 ret i16 %val92}93 94define i32 @test_load_acquire_i32(ptr %ptr) {95; CHECK-LABEL: test_load_acquire_i32:96; CHECK: lda r0, [r0]97 %val = load atomic i32, ptr %ptr acquire, align 498 ret i32 %val99}100 101define i64 @test_load_acquire_i64(ptr %ptr) {102; CHECK-LABEL: test_load_acquire_i64:103; CHECK: bl __atomic_load104 %val = load atomic i64, ptr %ptr acquire, align 4105 ret i64 %val106}107 108define void @test_store_release_i8(i8 %val, ptr %ptr) {109; CHECK-LABEL: test_store_release_i8:110; CHECK: stlb r0, [r1]111 store atomic i8 %val, ptr %ptr seq_cst, align 1112 ret void113}114 115define void @test_store_release_i16(i16 %val, ptr %ptr) {116; CHECK-LABEL: test_store_release_i16:117; CHECK: stlh r0, [r1]118 store atomic i16 %val, ptr %ptr release, align 2119 ret void120}121 122define void @test_store_release_i32(i32 %val, ptr %ptr) {123; CHECK-LABEL: test_store_release_i32:124; CHECK: stl r0, [r1]125 store atomic i32 %val, ptr %ptr seq_cst, align 4126 ret void127}128 129define void @test_store_release_i64(i64 %val, ptr %ptr) {130; CHECK-LABEL: test_store_release_i64:131; CHECK: bl __atomic_store132 store atomic i64 %val, ptr %ptr seq_cst, align 4133 ret void134}135 136 137@var8 = global i8 0138@var16 = global i16 0139@var32 = global i32 0140@var64 = global i64 0141