117 lines · plain
1; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 -simplifycfg-sink-common=false | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-CORTEX2; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=swift -simplifycfg-sink-common=false | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-SWIFT3; Avoid some 's' 16-bit instruction which partially update CPSR (and add false4; dependency) when it isn't dependent on last CPSR defining instruction.5; rdar://89282086 7define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {8 entry:9; CHECK-LABEL: t1:10; CHECK-CORTEX: muls [[REG:(r[0-9]+)]], r3, r211; CHECK-CORTEX-NEXT: mul [[REG2:(r[0-9]+)]], r1, r012; CHECK-SWIFT: muls [[REG2:(r[0-9]+)]], r1, r013; CHECK-SWIFT-NEXT: mul [[REG:(r[0-9]+)]], r2, r314; CHECK-NEXT: muls r0, [[REG]], [[REG2]]15 %0 = mul nsw i32 %a, %b16 %1 = mul nsw i32 %c, %d17 %2 = mul nsw i32 %0, %118 ret i32 %219}20 21; Avoid partial CPSR dependency via loop backedge.22; rdar://1035757023define void @t2(ptr nocapture %ptr1, ptr %ptr2, i32 %c) nounwind {24entry:25; CHECK-LABEL: t2:26 br label %while.body27 28while.body:29; CHECK: while.body30; CHECK: mul r{{[0-9]+}}31; CHECK-NOT: muls32 %ptr1.addr.09 = phi ptr [ %add.ptr, %while.body ], [ %ptr1, %entry ]33 %ptr2.addr.08 = phi ptr [ %incdec.ptr, %while.body ], [ %ptr2, %entry ]34 %0 = load i32, ptr %ptr1.addr.09, align 435 %arrayidx1 = getelementptr inbounds i32, ptr %ptr1.addr.09, i32 136 %1 = load i32, ptr %arrayidx1, align 437 %arrayidx3 = getelementptr inbounds i32, ptr %ptr1.addr.09, i32 238 %2 = load i32, ptr %arrayidx3, align 439 %arrayidx4 = getelementptr inbounds i32, ptr %ptr1.addr.09, i32 340 %3 = load i32, ptr %arrayidx4, align 441 %add.ptr = getelementptr inbounds i32, ptr %ptr1.addr.09, i32 442 %mul = mul i32 %1, %043 %mul5 = mul i32 %mul, %244 %mul6 = mul i32 %mul5, %345 store i32 %mul6, ptr %ptr2.addr.08, align 446 %incdec.ptr = getelementptr inbounds i32, ptr %ptr2.addr.08, i32 -147 %tobool = icmp eq ptr %incdec.ptr, null48 br i1 %tobool, label %while.end, label %while.body49 50while.end:51 ret void52}53 54; Allow partial CPSR dependency when code size is the priority.55; rdar://1287892856define void @t3(ptr nocapture %ptr1, ptr %ptr2, i32 %c) nounwind minsize {57entry:58; CHECK-LABEL: t3:59 br label %while.body60 61while.body:62; CHECK: while.body63; CHECK: muls r{{[0-9]+}}64; CHECK: muls65 %ptr1.addr.09 = phi ptr [ %add.ptr, %while.body ], [ %ptr1, %entry ]66 %ptr2.addr.08 = phi ptr [ %incdec.ptr, %while.body ], [ %ptr2, %entry ]67 %0 = load i32, ptr %ptr1.addr.09, align 468 %arrayidx1 = getelementptr inbounds i32, ptr %ptr1.addr.09, i32 169 %1 = load i32, ptr %arrayidx1, align 470 %arrayidx3 = getelementptr inbounds i32, ptr %ptr1.addr.09, i32 271 %2 = load i32, ptr %arrayidx3, align 472 %arrayidx4 = getelementptr inbounds i32, ptr %ptr1.addr.09, i32 373 %3 = load i32, ptr %arrayidx4, align 474 %add.ptr = getelementptr inbounds i32, ptr %ptr1.addr.09, i32 475 %mul = mul i32 %1, %076 %mul5 = mul i32 %mul, %277 %mul6 = mul i32 %mul5, %378 store i32 %mul6, ptr %ptr2.addr.08, align 479 %incdec.ptr = getelementptr inbounds i32, ptr %ptr2.addr.08, i32 -180 %tobool = icmp eq ptr %incdec.ptr, null81 br i1 %tobool, label %while.end, label %while.body82 83while.end:84 ret void85}86 87; Avoid producing tMOVi8 after a high-latency flag-setting operation.88; <rdar://problem/13468102>89define void @t4(ptr nocapture %p, ptr nocapture %q) {90entry:91; CHECK: t492; CHECK: vmrs APSR_nzcv, fpscr93; CHECK: if.then94; CHECK-NOT: movs95 %0 = load double, ptr %q, align 496 %cmp = fcmp olt double %0, 1.000000e+0197 %incdec.ptr1 = getelementptr inbounds i32, ptr %p, i32 198 br i1 %cmp, label %if.then, label %if.else99 100if.then:101 store i32 7, ptr %p, align 4102 %incdec.ptr2 = getelementptr inbounds i32, ptr %p, i32 2103 store i32 8, ptr %incdec.ptr1, align 4104 store i32 9, ptr %incdec.ptr2, align 4105 br label %if.end106 107if.else:108 store i32 3, ptr %p, align 4109 %incdec.ptr5 = getelementptr inbounds i32, ptr %p, i32 3110 store i32 5, ptr %incdec.ptr1, align 4111 store i32 6, ptr %incdec.ptr5, align 4112 br label %if.end113 114if.end:115 ret void116}117