178 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=armv8.6a-arm-none-eabi -mattr=+bf16,+neon,fullfp16 < %s | FileCheck %s3; FIXME: Remove fullfp16 once bfloat arguments and returns lowering stops4; depending on it.5 6target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"7target triple = "armv8.6a-arm-none-eabi"8 9define arm_aapcs_vfpcc <4 x bfloat> @test_vcreate_bf16(i64 %a) {10; CHECK-LABEL: test_vcreate_bf16:11; CHECK: @ %bb.0: @ %entry12; CHECK-NEXT: vmov d0, r0, r113; CHECK-NEXT: bx lr14entry:15 %0 = bitcast i64 %a to <4 x bfloat>16 ret <4 x bfloat> %017}18 19define arm_aapcs_vfpcc <4 x bfloat> @test_vdup_n_bf16(bfloat %v) {20; CHECK-LABEL: test_vdup_n_bf16:21; CHECK: @ %bb.0: @ %entry22; CHECK-NEXT: @ kill: def $s0 killed $s0 def $d023; CHECK-NEXT: vdup.16 d0, d0[0]24; CHECK-NEXT: bx lr25entry:26 %vecinit.i = insertelement <4 x bfloat> undef, bfloat %v, i32 027 %vecinit3.i = shufflevector <4 x bfloat> %vecinit.i, <4 x bfloat> undef, <4 x i32> zeroinitializer28 ret <4 x bfloat> %vecinit3.i29}30 31define arm_aapcs_vfpcc <8 x bfloat> @test_vdupq_n_bf16(bfloat %v) {32; CHECK-LABEL: test_vdupq_n_bf16:33; CHECK: @ %bb.0: @ %entry34; CHECK-NEXT: @ kill: def $s0 killed $s0 def $d035; CHECK-NEXT: vdup.16 q0, d0[0]36; CHECK-NEXT: bx lr37entry:38 %vecinit.i = insertelement <8 x bfloat> undef, bfloat %v, i32 039 %vecinit7.i = shufflevector <8 x bfloat> %vecinit.i, <8 x bfloat> undef, <8 x i32> zeroinitializer40 ret <8 x bfloat> %vecinit7.i41}42 43define arm_aapcs_vfpcc <4 x bfloat> @test_vdup_lane_bf16(<4 x bfloat> %v) {44; CHECK-LABEL: test_vdup_lane_bf16:45; CHECK: @ %bb.0: @ %entry46; CHECK-NEXT: vdup.16 d0, d0[1]47; CHECK-NEXT: bx lr48entry:49 %lane = shufflevector <4 x bfloat> %v, <4 x bfloat> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>50 ret <4 x bfloat> %lane51}52 53define arm_aapcs_vfpcc <8 x bfloat> @test_vdupq_lane_bf16(<4 x bfloat> %v) {54; CHECK-LABEL: test_vdupq_lane_bf16:55; CHECK: @ %bb.0: @ %entry56; CHECK-NEXT: vdup.16 q0, d0[1]57; CHECK-NEXT: bx lr58entry:59 %lane = shufflevector <4 x bfloat> %v, <4 x bfloat> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>60 ret <8 x bfloat> %lane61}62 63define arm_aapcs_vfpcc <4 x bfloat> @test_vdup_laneq_bf16(<8 x bfloat> %v) {64; CHECK-LABEL: test_vdup_laneq_bf16:65; CHECK: @ %bb.0: @ %entry66; CHECK-NEXT: vdup.16 d0, d1[3]67; CHECK-NEXT: bx lr68entry:69 %lane = shufflevector <8 x bfloat> %v, <8 x bfloat> undef, <4 x i32> <i32 7, i32 7, i32 7, i32 7>70 ret <4 x bfloat> %lane71}72 73define arm_aapcs_vfpcc <8 x bfloat> @test_vdupq_laneq_bf16(<8 x bfloat> %v) {74; CHECK-LABEL: test_vdupq_laneq_bf16:75; CHECK: @ %bb.0: @ %entry76; CHECK-NEXT: vdup.16 q0, d1[3]77; CHECK-NEXT: bx lr78entry:79 %lane = shufflevector <8 x bfloat> %v, <8 x bfloat> undef, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>80 ret <8 x bfloat> %lane81}82 83define arm_aapcs_vfpcc <8 x bfloat> @test_vcombine_bf16(<4 x bfloat> %low, <4 x bfloat> %high) {84; CHECK-LABEL: test_vcombine_bf16:85; CHECK: @ %bb.0: @ %entry86; CHECK-NEXT: vmov.f64 d16, d187; CHECK-NEXT: vorr d17, d0, d088; CHECK-NEXT: vorr q0, q8, q889; CHECK-NEXT: bx lr90entry:91 %shuffle.i = shufflevector <4 x bfloat> %high, <4 x bfloat> %low, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>92 ret <8 x bfloat> %shuffle.i93}94 95define arm_aapcs_vfpcc <4 x bfloat> @test_vget_high_bf16(<8 x bfloat> %a) {96; CHECK-LABEL: test_vget_high_bf16:97; CHECK: @ %bb.0: @ %entry98; CHECK-NEXT: vmov.f64 d0, d199; CHECK-NEXT: bx lr100entry:101 %shuffle.i = shufflevector <8 x bfloat> %a, <8 x bfloat> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>102 ret <4 x bfloat> %shuffle.i103}104 105define arm_aapcs_vfpcc <4 x bfloat> @test_vget_low_bf16(<8 x bfloat> %a) {106; CHECK-LABEL: test_vget_low_bf16:107; CHECK: @ %bb.0: @ %entry108; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0109; CHECK-NEXT: bx lr110entry:111 %shuffle.i = shufflevector <8 x bfloat> %a, <8 x bfloat> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>112 ret <4 x bfloat> %shuffle.i113}114 115define arm_aapcs_vfpcc bfloat @test_vgetq_lane_bf16_even(<8 x bfloat> %v) {116; CHECK-LABEL: test_vgetq_lane_bf16_even:117; CHECK: @ %bb.0: @ %entry118; CHECK-NEXT: vmov.f32 s0, s3119; CHECK-NEXT: bx lr120entry:121 %0 = extractelement <8 x bfloat> %v, i32 6122 ret bfloat %0123}124 125define arm_aapcs_vfpcc bfloat @test_vgetq_lane_bf16_odd(<8 x bfloat> %v) {126; CHECK-LABEL: test_vgetq_lane_bf16_odd:127; CHECK: @ %bb.0: @ %entry128; CHECK-NEXT: vmovx.f16 s0, s3129; CHECK-NEXT: bx lr130entry:131 %0 = extractelement <8 x bfloat> %v, i32 7132 ret bfloat %0133}134 135define arm_aapcs_vfpcc bfloat @test_vget_lane_bf16_even(<4 x bfloat> %v) {136; CHECK-LABEL: test_vget_lane_bf16_even:137; CHECK: @ %bb.0: @ %entry138; CHECK-NEXT: vmov.f32 s0, s1139; CHECK-NEXT: bx lr140entry:141 %0 = extractelement <4 x bfloat> %v, i32 2142 ret bfloat %0143}144 145define arm_aapcs_vfpcc bfloat @test_vget_lane_bf16_odd(<4 x bfloat> %v) {146; CHECK-LABEL: test_vget_lane_bf16_odd:147; CHECK: @ %bb.0: @ %entry148; CHECK-NEXT: vmovx.f16 s0, s0149; CHECK-NEXT: bx lr150entry:151 %0 = extractelement <4 x bfloat> %v, i32 1152 ret bfloat %0153}154 155define arm_aapcs_vfpcc <4 x bfloat> @test_vset_lane_bf16(bfloat %a, <4 x bfloat> %v) {156; CHECK-LABEL: test_vset_lane_bf16:157; CHECK: @ %bb.0: @ %entry158; CHECK-NEXT: vmov r0, s0159; CHECK-NEXT: vmov.16 d1[1], r0160; CHECK-NEXT: vorr d0, d1, d1161; CHECK-NEXT: bx lr162entry:163 %0 = insertelement <4 x bfloat> %v, bfloat %a, i32 1164 ret <4 x bfloat> %0165}166 167define arm_aapcs_vfpcc <8 x bfloat> @test_vsetq_lane_bf16(bfloat %a, <8 x bfloat> %v) {168; CHECK-LABEL: test_vsetq_lane_bf16:169; CHECK: @ %bb.0: @ %entry170; CHECK-NEXT: vmov r0, s0171; CHECK-NEXT: vmov.16 d3[3], r0172; CHECK-NEXT: vorr q0, q1, q1173; CHECK-NEXT: bx lr174entry:175 %0 = insertelement <8 x bfloat> %v, bfloat %a, i32 7176 ret <8 x bfloat> %0177}178