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1; RUN: llc < %s -mtriple armeb-eabi -mattr v7,neon -o - | FileCheck %s2 3define void @vector_ext_2i8_to_2i64( ptr %loadaddr, ptr %storeaddr ) {4; CHECK-LABEL: vector_ext_2i8_to_2i64:5; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16]6; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]7; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]8; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]9; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]]10; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1]11; CHECK-NEXT: bx lr12 %1 = load <2 x i8>, ptr %loadaddr13 %2 = zext <2 x i8> %1 to <2 x i64>14 store <2 x i64> %2, ptr %storeaddr15 ret void16}17 18define void @vector_ext_2i16_to_2i64( ptr %loadaddr, ptr %storeaddr ) {19; CHECK-LABEL: vector_ext_2i16_to_2i64:20; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32]21; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]22; CHECK-NEXT: vmovl.u16 [[QREG:q[0-9]+]], [[REG]]23; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]]24; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1]25; CHECK-NEXT: bx lr26 %1 = load <2 x i16>, ptr %loadaddr27 %2 = zext <2 x i16> %1 to <2 x i64>28 store <2 x i64> %2, ptr %storeaddr29 ret void30}31 32 33define void @vector_ext_2i8_to_2i32( ptr %loadaddr, ptr %storeaddr ) {34; CHECK-LABEL: vector_ext_2i8_to_2i32:35; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16]36; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]37; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]38; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]39; CHECK-NEXT: vrev64.32 [[REG]], [[REG]]40; CHECK-NEXT: vstr [[REG]], [r1]41; CHECK-NEXT: bx lr42 %1 = load <2 x i8>, ptr %loadaddr43 %2 = zext <2 x i8> %1 to <2 x i32>44 store <2 x i32> %2, ptr %storeaddr45 ret void46}47 48define void @vector_ext_2i16_to_2i32( ptr %loadaddr, ptr %storeaddr ) {49; CHECK-LABEL: vector_ext_2i16_to_2i32:50; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32]51; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]52; CHECK-NEXT: vmovl.u16 [[QREG:q[0-9]+]], [[REG]]53; CHECK-NEXT: vrev64.32 [[REG]], [[REG]]54; CHECK-NEXT: vstr [[REG]], [r1]55; CHECK-NEXT: bx lr56 %1 = load <2 x i16>, ptr %loadaddr57 %2 = zext <2 x i16> %1 to <2 x i32>58 store <2 x i32> %2, ptr %storeaddr59 ret void60}61 62define void @vector_ext_2i8_to_2i16( ptr %loadaddr, ptr %storeaddr ) {63; CHECK-LABEL: vector_ext_2i8_to_2i16:64; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16]65; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]66; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]67; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]68; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]69; CHECK-NEXT: vuzp.16 [[REG]], {{d[0-9]+}}70; CHECK-NEXT: vrev32.16 [[REG]], {{d[0-9]+}}71; CHECK-NEXT: vst1.32 {[[REG]][0]}, [r1:32]72; CHECK-NEXT: bx lr73 %1 = load <2 x i8>, ptr %loadaddr74 %2 = zext <2 x i8> %1 to <2 x i16>75 store <2 x i16> %2, ptr %storeaddr76 ret void77}78 79define void @vector_ext_4i8_to_4i32( ptr %loadaddr, ptr %storeaddr ) {80; CHECK-LABEL: vector_ext_4i8_to_4i32:81; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32]82; CHECK-NEXT: vrev32.8 [[REG]], [[REG]]83; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]84; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]85; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]86; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1]87; CHECK-NEXT: bx lr88 %1 = load <4 x i8>, ptr %loadaddr89 %2 = zext <4 x i8> %1 to <4 x i32>90 store <4 x i32> %2, ptr %storeaddr91 ret void92}93 94define void @vector_ext_4i8_to_4i16( ptr %loadaddr, ptr %storeaddr ) {95; CHECK-LABEL: vector_ext_4i8_to_4i16:96; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32]97; CHECK-NEXT: vrev32.8 [[REG]], [[REG]]98; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]99; CHECK-NEXT: vrev64.16 [[REG]], [[REG]]100; CHECK-NEXT: vstr [[REG]], [r1]101; CHECK-NEXT: bx lr102 %1 = load <4 x i8>, ptr %loadaddr103 %2 = zext <4 x i8> %1 to <4 x i16>104 store <4 x i16> %2, ptr %storeaddr105 ret void106}107