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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple armeb-eabi -mattr=armv8.2-a,neon,fullfp16 -target-abi=aapcs-gnu -float-abi hard -o - %s | FileCheck %s3 4;64 bit conversions to v4f165define void @conv_i64_to_v4f16( i64 %val, ptr %store ) {6; CHECK-LABEL: conv_i64_to_v4f16:7; CHECK: @ %bb.0: @ %entry8; CHECK-NEXT: vmov d16, r1, r09; CHECK-NEXT: vldr d17, [r2]10; CHECK-NEXT: vrev64.16 d16, d1611; CHECK-NEXT: vrev64.16 d17, d1712; CHECK-NEXT: vadd.f16 d16, d16, d1713; CHECK-NEXT: vrev64.16 d16, d1614; CHECK-NEXT: vstr d16, [r2]15; CHECK-NEXT: bx lr16entry:17 %v = bitcast i64 %val to <4 x half>18 %w = load <4 x half>, ptr %store19 %a = fadd <4 x half> %v, %w20 store <4 x half> %a, ptr %store21 ret void22}23 24define void @conv_f64_to_v4f16( double %val, ptr %store ) {25; CHECK-LABEL: conv_f64_to_v4f16:26; CHECK: @ %bb.0: @ %entry27; CHECK-NEXT: vldr d16, [r0]28; CHECK-NEXT: vrev64.16 d17, d029; CHECK-NEXT: vrev64.16 d16, d1630; CHECK-NEXT: vadd.f16 d16, d17, d1631; CHECK-NEXT: vrev64.16 d16, d1632; CHECK-NEXT: vstr d16, [r0]33; CHECK-NEXT: bx lr34entry:35 %v = bitcast double %val to <4 x half>36 %w = load <4 x half>, ptr %store37 %a = fadd <4 x half> %v, %w38 store <4 x half> %a, ptr %store39 ret void40}41 42define void @conv_v2f32_to_v4f16( <2 x float> %a, ptr %store ) {43; CHECK-LABEL: conv_v2f32_to_v4f16:44; CHECK: @ %bb.0: @ %entry45; CHECK-NEXT: vldr d16, .LCPI2_046; CHECK-NEXT: vrev64.32 d17, d047; CHECK-NEXT: vrev64.32 d16, d1648; CHECK-NEXT: vadd.f32 d16, d17, d1649; CHECK-NEXT: vldr d17, [r0]50; CHECK-NEXT: vrev64.16 d17, d1751; CHECK-NEXT: vrev32.16 d16, d1652; CHECK-NEXT: vadd.f16 d16, d16, d1753; CHECK-NEXT: vrev64.16 d16, d1654; CHECK-NEXT: vstr d16, [r0]55; CHECK-NEXT: bx lr56; CHECK-NEXT: .p2align 357; CHECK-NEXT: @ %bb.1:58; CHECK-NEXT: .LCPI2_0:59; CHECK-NEXT: .long 0xbf800000 @ float -160; CHECK-NEXT: .long 0x3f800000 @ float 161entry:62 %c = fadd <2 x float> %a, <float -1.0, float 1.0>63 %v = bitcast <2 x float> %c to <4 x half>64 %w = load <4 x half>, ptr %store65 %z = fadd <4 x half> %v, %w66 store <4 x half> %z, ptr %store67 ret void68}69 70define void @conv_v2i32_to_v4f16( <2 x i32> %a, ptr %store ) {71; CHECK-LABEL: conv_v2i32_to_v4f16:72; CHECK: @ %bb.0: @ %entry73; CHECK-NEXT: vldr d16, .LCPI3_074; CHECK-NEXT: vrev64.32 d17, d075; CHECK-NEXT: vrev64.32 d16, d1676; CHECK-NEXT: vadd.i32 d16, d17, d1677; CHECK-NEXT: vldr d18, [r0]78; CHECK-NEXT: vrev64.16 d17, d1879; CHECK-NEXT: vrev32.16 d16, d1680; CHECK-NEXT: vadd.f16 d16, d16, d1781; CHECK-NEXT: vrev64.16 d16, d1682; CHECK-NEXT: vstr d16, [r0]83; CHECK-NEXT: bx lr84; CHECK-NEXT: .p2align 385; CHECK-NEXT: @ %bb.1:86; CHECK-NEXT: .LCPI3_0:87; CHECK-NEXT: .long 1 @ 0x188; CHECK-NEXT: .long 4294967295 @ 0xffffffff89entry:90 %c = add <2 x i32> %a, <i32 1, i32 -1>91 %v = bitcast <2 x i32> %c to <4 x half>92 %w = load <4 x half>, ptr %store93 %z = fadd <4 x half> %v, %w94 store <4 x half> %z, ptr %store95 ret void96}97 98define void @conv_v4i16_to_v4f16( <4 x i16> %a, ptr %store ) {99; CHECK-LABEL: conv_v4i16_to_v4f16:100; CHECK: @ %bb.0: @ %entry101; CHECK-NEXT: vmov.i64 d16, #0xffff00000000ffff102; CHECK-NEXT: vldr d17, [r0]103; CHECK-NEXT: vrev64.16 d18, d0104; CHECK-NEXT: vadd.i16 d16, d18, d16105; CHECK-NEXT: vrev64.16 d17, d17106; CHECK-NEXT: vadd.f16 d16, d16, d17107; CHECK-NEXT: vrev64.16 d16, d16108; CHECK-NEXT: vstr d16, [r0]109; CHECK-NEXT: bx lr110entry:111 %c = add <4 x i16> %a, <i16 -1, i16 0, i16 0, i16 -1>112 %v = bitcast <4 x i16> %c to <4 x half>113 %w = load <4 x half>, ptr %store114 %z = fadd <4 x half> %v, %w115 store <4 x half> %z, ptr %store116 ret void117}118 119define void @conv_v8i8_to_v4f16( <8 x i8> %a, ptr %store ) {120; CHECK-LABEL: conv_v8i8_to_v4f16:121; CHECK: @ %bb.0: @ %entry122; CHECK-NEXT: vmov.i8 d16, #0x1123; CHECK-NEXT: vrev64.8 d17, d0124; CHECK-NEXT: vldr d18, [r0]125; CHECK-NEXT: vadd.i8 d16, d17, d16126; CHECK-NEXT: vrev64.16 d17, d18127; CHECK-NEXT: vrev16.8 d16, d16128; CHECK-NEXT: vadd.f16 d16, d16, d17129; CHECK-NEXT: vrev64.16 d16, d16130; CHECK-NEXT: vstr d16, [r0]131; CHECK-NEXT: bx lr132entry:133 %c = add <8 x i8> %a, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>134 %v = bitcast <8 x i8> %c to <4 x half>135 %w = load <4 x half>, ptr %store136 %z = fadd <4 x half> %v, %w137 store <4 x half> %z, ptr %store138 ret void139}140 141define void @conv_v2i64_to_v8f16( <2 x i64> %val, ptr %store ) {142; CHECK-LABEL: conv_v2i64_to_v8f16:143; CHECK: @ %bb.0: @ %entry144; CHECK-NEXT: vld1.64 {d16, d17}, [r0]145; CHECK-NEXT: adr r1, .LCPI6_0146; CHECK-NEXT: vld1.64 {d18, d19}, [r1:128]147; CHECK-NEXT: vadd.i64 q9, q0, q9148; CHECK-NEXT: vrev64.16 q8, q8149; CHECK-NEXT: vrev64.16 q9, q9150; CHECK-NEXT: vadd.f16 q8, q9, q8151; CHECK-NEXT: vrev64.16 q8, q8152; CHECK-NEXT: vst1.64 {d16, d17}, [r0]153; CHECK-NEXT: bx lr154; CHECK-NEXT: .p2align 4155; CHECK-NEXT: @ %bb.1:156; CHECK-NEXT: .LCPI6_0:157; CHECK-NEXT: .long 0 @ 0x0158; CHECK-NEXT: .long 1 @ 0x1159; CHECK-NEXT: .long 4294967295 @ 0xffffffff160; CHECK-NEXT: .long 4294967295 @ 0xffffffff161entry:162 %v = add <2 x i64> %val, <i64 1, i64 -1>163 %v1 = bitcast <2 x i64> %v to <8 x half>164 %w = load <8 x half>, ptr %store165 %a = fadd <8 x half> %v1, %w166 store <8 x half> %a, ptr %store167 ret void168}169define void @conv_v2f64_to_v8f16( <2 x double> %val, ptr %store ) {170; CHECK-LABEL: conv_v2f64_to_v8f16:171; CHECK: @ %bb.0: @ %entry172; CHECK-NEXT: vmov.f64 d16, #-1.000000e+00173; CHECK-NEXT: vmov.f64 d17, #1.000000e+00174; CHECK-NEXT: vadd.f64 d19, d1, d16175; CHECK-NEXT: vadd.f64 d18, d0, d17176; CHECK-NEXT: vld1.64 {d16, d17}, [r0]177; CHECK-NEXT: vrev64.16 q8, q8178; CHECK-NEXT: vrev64.16 q9, q9179; CHECK-NEXT: vadd.f16 q8, q9, q8180; CHECK-NEXT: vrev64.16 q8, q8181; CHECK-NEXT: vst1.64 {d16, d17}, [r0]182; CHECK-NEXT: bx lr183entry:184 %v = fadd <2 x double> %val, <double 1.0, double -1.0>185 %v1 = bitcast <2 x double> %v to <8 x half>186 %w = load <8 x half>, ptr %store187 %a = fadd <8 x half> %v1, %w188 store <8 x half> %a, ptr %store189 ret void190}191 192define void @conv_v4f32_to_v8f16( <4 x float> %a, ptr %store ) {193; CHECK-LABEL: conv_v4f32_to_v8f16:194; CHECK: @ %bb.0: @ %entry195; CHECK-NEXT: adr r1, .LCPI8_0196; CHECK-NEXT: vrev64.32 q9, q0197; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]198; CHECK-NEXT: vrev64.32 q8, q8199; CHECK-NEXT: vadd.f32 q8, q9, q8200; CHECK-NEXT: vld1.64 {d18, d19}, [r0]201; CHECK-NEXT: vrev64.16 q9, q9202; CHECK-NEXT: vrev32.16 q8, q8203; CHECK-NEXT: vadd.f16 q8, q8, q9204; CHECK-NEXT: vrev64.16 q8, q8205; CHECK-NEXT: vst1.64 {d16, d17}, [r0]206; CHECK-NEXT: bx lr207; CHECK-NEXT: .p2align 4208; CHECK-NEXT: @ %bb.1:209; CHECK-NEXT: .LCPI8_0:210; CHECK-NEXT: .long 0xbf800000 @ float -1211; CHECK-NEXT: .long 0x3f800000 @ float 1212; CHECK-NEXT: .long 0xbf800000 @ float -1213; CHECK-NEXT: .long 0x3f800000 @ float 1214entry:215 %c = fadd <4 x float> %a, <float -1.0, float 1.0, float -1.0, float 1.0>216 %v = bitcast <4 x float> %c to <8 x half>217 %w = load <8 x half>, ptr %store218 %z = fadd <8 x half> %v, %w219 store <8 x half> %z, ptr %store220 ret void221}222 223define void @conv_v4i32_to_v8f16( <4 x i32> %a, ptr %store ) {224; CHECK-LABEL: conv_v4i32_to_v8f16:225; CHECK: @ %bb.0: @ %entry226; CHECK-NEXT: adr r1, .LCPI9_0227; CHECK-NEXT: vrev64.32 q9, q0228; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]229; CHECK-NEXT: vrev64.32 q8, q8230; CHECK-NEXT: vadd.i32 q8, q9, q8231; CHECK-NEXT: vld1.64 {d20, d21}, [r0]232; CHECK-NEXT: vrev64.16 q9, q10233; CHECK-NEXT: vrev32.16 q8, q8234; CHECK-NEXT: vadd.f16 q8, q8, q9235; CHECK-NEXT: vrev64.16 q8, q8236; CHECK-NEXT: vst1.64 {d16, d17}, [r0]237; CHECK-NEXT: bx lr238; CHECK-NEXT: .p2align 4239; CHECK-NEXT: @ %bb.1:240; CHECK-NEXT: .LCPI9_0:241; CHECK-NEXT: .long 4294967295 @ 0xffffffff242; CHECK-NEXT: .long 1 @ 0x1243; CHECK-NEXT: .long 4294967295 @ 0xffffffff244; CHECK-NEXT: .long 1 @ 0x1245entry:246 %c = add <4 x i32> %a, <i32 -1, i32 1, i32 -1, i32 1>247 %v = bitcast <4 x i32> %c to <8 x half>248 %w = load <8 x half>, ptr %store249 %z = fadd <8 x half> %v, %w250 store <8 x half> %z, ptr %store251 ret void252}253 254define void @conv_v8i16_to_v8f16( <8 x i16> %a, ptr %store ) {255; CHECK-LABEL: conv_v8i16_to_v8f16:256; CHECK: @ %bb.0: @ %entry257; CHECK-NEXT: adr r1, .LCPI10_0258; CHECK-NEXT: vld1.64 {d18, d19}, [r0]259; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]260; CHECK-NEXT: vrev64.16 q10, q0261; CHECK-NEXT: vrev64.16 q8, q8262; CHECK-NEXT: vrev64.16 q9, q9263; CHECK-NEXT: vadd.i16 q8, q10, q8264; CHECK-NEXT: vadd.f16 q8, q8, q9265; CHECK-NEXT: vrev64.16 q8, q8266; CHECK-NEXT: vst1.64 {d16, d17}, [r0]267; CHECK-NEXT: bx lr268; CHECK-NEXT: .p2align 4269; CHECK-NEXT: @ %bb.1:270; CHECK-NEXT: .LCPI10_0:271; CHECK-NEXT: .short 65535 @ 0xffff272; CHECK-NEXT: .short 1 @ 0x1273; CHECK-NEXT: .short 0 @ 0x0274; CHECK-NEXT: .short 7 @ 0x7275; CHECK-NEXT: .short 65535 @ 0xffff276; CHECK-NEXT: .short 1 @ 0x1277; CHECK-NEXT: .short 0 @ 0x0278; CHECK-NEXT: .short 7 @ 0x7279entry:280 %c = add <8 x i16> %a, <i16 -1, i16 1, i16 0, i16 7, i16 -1, i16 1, i16 0, i16 7>281 %v = bitcast <8 x i16> %c to <8 x half>282 %w = load <8 x half>, ptr %store283 %z = fadd <8 x half> %v, %w284 store <8 x half> %z, ptr %store285 ret void286}287 288define void @conv_v16i8_to_v8f16( <16 x i8> %a, ptr %store ) {289; CHECK-LABEL: conv_v16i8_to_v8f16:290; CHECK: @ %bb.0: @ %entry291; CHECK-NEXT: vrev64.8 q8, q0292; CHECK-NEXT: vmov.i8 q9, #0x1293; CHECK-NEXT: vadd.i8 q8, q8, q9294; CHECK-NEXT: vld1.64 {d20, d21}, [r0]295; CHECK-NEXT: vrev64.16 q9, q10296; CHECK-NEXT: vrev16.8 q8, q8297; CHECK-NEXT: vadd.f16 q8, q8, q9298; CHECK-NEXT: vrev64.16 q8, q8299; CHECK-NEXT: vst1.64 {d16, d17}, [r0]300; CHECK-NEXT: bx lr301entry:302 %c = add <16 x i8> %a, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>303 %v = bitcast <16 x i8> %c to <8 x half>304 %w = load <8 x half>, ptr %store305 %z = fadd <8 x half> %v, %w306 store <8 x half> %z, ptr %store307 ret void308}309 310define void @conv_v4f16_to_i64( <4 x half> %a, ptr %store ) {311; CHECK-LABEL: conv_v4f16_to_i64:312; CHECK: @ %bb.0: @ %entry313; CHECK-NEXT: vldr d16, .LCPI12_0314; CHECK-NEXT: vrev64.16 d17, d0315; CHECK-NEXT: vrev64.16 d16, d16316; CHECK-NEXT: vadd.f16 d16, d17, d16317; CHECK-NEXT: vrev64.16 d16, d16318; CHECK-NEXT: vmov r1, r2, d16319; CHECK-NEXT: subs r1, r1, #1320; CHECK-NEXT: sbc r2, r2, #0321; CHECK-NEXT: str r2, [r0]322; CHECK-NEXT: str r1, [r0, #4]323; CHECK-NEXT: bx lr324; CHECK-NEXT: .p2align 3325; CHECK-NEXT: @ %bb.1:326; CHECK-NEXT: .LCPI12_0:327; CHECK-NEXT: .short 0xbc00 @ half -1328; CHECK-NEXT: .short 0x3c00 @ half 1329; CHECK-NEXT: .short 0xbc00 @ half -1330; CHECK-NEXT: .short 0x3c00 @ half 1331entry:332 %z = fadd <4 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0>333 %y = bitcast <4 x half> %z to i64334 %w = add i64 %y, -1335 store i64 %w, ptr %store336 ret void337}338 339define void @conv_v4f16_to_f64( <4 x half> %a, ptr %store ) {340; CHECK-LABEL: conv_v4f16_to_f64:341; CHECK: @ %bb.0: @ %entry342; CHECK-NEXT: vldr d16, .LCPI13_0343; CHECK-NEXT: vrev64.16 d17, d0344; CHECK-NEXT: vrev64.16 d16, d16345; CHECK-NEXT: vadd.f16 d16, d17, d16346; CHECK-NEXT: vmov.f64 d17, #-1.000000e+00347; CHECK-NEXT: vrev64.16 d16, d16348; CHECK-NEXT: vadd.f64 d16, d16, d17349; CHECK-NEXT: vstr d16, [r0]350; CHECK-NEXT: bx lr351; CHECK-NEXT: .p2align 3352; CHECK-NEXT: @ %bb.1:353; CHECK-NEXT: .LCPI13_0:354; CHECK-NEXT: .short 0xbc00 @ half -1355; CHECK-NEXT: .short 0x3c00 @ half 1356; CHECK-NEXT: .short 0xbc00 @ half -1357; CHECK-NEXT: .short 0x3c00 @ half 1358entry:359 %z = fadd <4 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0>360 %y = bitcast <4 x half> %z to double361 %w = fadd double %y, -1.0362 store double %w, ptr %store363 ret void364}365 366define void @conv_v4f16_to_v2i32( <4 x half> %a, ptr %store ) {367; CHECK-LABEL: conv_v4f16_to_v2i32:368; CHECK: @ %bb.0: @ %entry369; CHECK-NEXT: vldr d16, .LCPI14_0370; CHECK-NEXT: vrev64.16 d17, d0371; CHECK-NEXT: vrev64.16 d16, d16372; CHECK-NEXT: vadd.f16 d16, d17, d16373; CHECK-NEXT: vldr d17, .LCPI14_1374; CHECK-NEXT: vrev64.32 d17, d17375; CHECK-NEXT: vrev32.16 d16, d16376; CHECK-NEXT: vadd.i32 d16, d16, d17377; CHECK-NEXT: vrev64.32 d16, d16378; CHECK-NEXT: vstr d16, [r0]379; CHECK-NEXT: bx lr380; CHECK-NEXT: .p2align 3381; CHECK-NEXT: @ %bb.1:382; CHECK-NEXT: .LCPI14_0:383; CHECK-NEXT: .short 0xbc00 @ half -1384; CHECK-NEXT: .short 0x3c00 @ half 1385; CHECK-NEXT: .short 0xbc00 @ half -1386; CHECK-NEXT: .short 0x3c00 @ half 1387; CHECK-NEXT: .LCPI14_1:388; CHECK-NEXT: .long 4294967295 @ 0xffffffff389; CHECK-NEXT: .long 1 @ 0x1390entry:391 %z = fadd <4 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0>392 %y = bitcast <4 x half> %z to <2 x i32>393 %w = add <2 x i32> %y, <i32 -1, i32 1>394 store <2 x i32> %w, ptr %store395 ret void396}397 398define void @conv_v4f16_to_v2f32( <4 x half> %a, ptr %store ) {399; CHECK-LABEL: conv_v4f16_to_v2f32:400; CHECK: @ %bb.0: @ %entry401; CHECK-NEXT: vldr d16, .LCPI15_0402; CHECK-NEXT: vrev64.16 d17, d0403; CHECK-NEXT: vrev64.16 d16, d16404; CHECK-NEXT: vadd.f16 d16, d17, d16405; CHECK-NEXT: vldr d17, .LCPI15_1406; CHECK-NEXT: vrev64.32 d17, d17407; CHECK-NEXT: vrev32.16 d16, d16408; CHECK-NEXT: vadd.f32 d16, d16, d17409; CHECK-NEXT: vrev64.32 d16, d16410; CHECK-NEXT: vstr d16, [r0]411; CHECK-NEXT: bx lr412; CHECK-NEXT: .p2align 3413; CHECK-NEXT: @ %bb.1:414; CHECK-NEXT: .LCPI15_0:415; CHECK-NEXT: .short 0xbc00 @ half -1416; CHECK-NEXT: .short 0x3c00 @ half 1417; CHECK-NEXT: .short 0xbc00 @ half -1418; CHECK-NEXT: .short 0x3c00 @ half 1419; CHECK-NEXT: .LCPI15_1:420; CHECK-NEXT: .long 0xbf800000 @ float -1421; CHECK-NEXT: .long 0x3f800000 @ float 1422entry:423 %z = fadd <4 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0>424 %y = bitcast <4 x half> %z to <2 x float>425 %w = fadd <2 x float> %y, <float -1.0, float 1.0>426 store <2 x float> %w, ptr %store427 ret void428}429 430define void @conv_v4f16_to_v4i16( <4 x half> %a, ptr %store ) {431; CHECK-LABEL: conv_v4f16_to_v4i16:432; CHECK: @ %bb.0: @ %entry433; CHECK-NEXT: vldr d16, .LCPI16_0434; CHECK-NEXT: vrev64.16 d17, d0435; CHECK-NEXT: vrev64.16 d16, d16436; CHECK-NEXT: vadd.f16 d16, d17, d16437; CHECK-NEXT: vldr d17, .LCPI16_1438; CHECK-NEXT: vrev64.16 d17, d17439; CHECK-NEXT: vadd.i16 d16, d16, d17440; CHECK-NEXT: vrev64.16 d16, d16441; CHECK-NEXT: vstr d16, [r0]442; CHECK-NEXT: bx lr443; CHECK-NEXT: .p2align 3444; CHECK-NEXT: @ %bb.1:445; CHECK-NEXT: .LCPI16_0:446; CHECK-NEXT: .short 0xbc00 @ half -1447; CHECK-NEXT: .short 0x3c00 @ half 1448; CHECK-NEXT: .short 0xbc00 @ half -1449; CHECK-NEXT: .short 0x3c00 @ half 1450; CHECK-NEXT: .LCPI16_1:451; CHECK-NEXT: .short 65535 @ 0xffff452; CHECK-NEXT: .short 1 @ 0x1453; CHECK-NEXT: .short 0 @ 0x0454; CHECK-NEXT: .short 7 @ 0x7455entry:456 %z = fadd <4 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0>457 %y = bitcast <4 x half> %z to <4 x i16>458 %w = add <4 x i16> %y, <i16 -1, i16 1, i16 0, i16 7>459 store <4 x i16> %w, ptr %store460 ret void461}462 463define void @conv_v4f16_to_v8f8( <4 x half> %a, ptr %store ) {464; CHECK-LABEL: conv_v4f16_to_v8f8:465; CHECK: @ %bb.0: @ %entry466; CHECK-NEXT: vldr d16, .LCPI17_0467; CHECK-NEXT: vrev64.16 d17, d0468; CHECK-NEXT: vrev64.16 d16, d16469; CHECK-NEXT: vadd.f16 d16, d17, d16470; CHECK-NEXT: vmov.i8 d17, #0x1471; CHECK-NEXT: vrev16.8 d16, d16472; CHECK-NEXT: vadd.i8 d16, d16, d17473; CHECK-NEXT: vrev64.8 d16, d16474; CHECK-NEXT: vstr d16, [r0]475; CHECK-NEXT: bx lr476; CHECK-NEXT: .p2align 3477; CHECK-NEXT: @ %bb.1:478; CHECK-NEXT: .LCPI17_0:479; CHECK-NEXT: .short 0xbc00 @ half -1480; CHECK-NEXT: .short 0x3c00 @ half 1481; CHECK-NEXT: .short 0xbc00 @ half -1482; CHECK-NEXT: .short 0x3c00 @ half 1483entry:484 %z = fadd <4 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0>485 %y = bitcast <4 x half> %z to <8 x i8>486 %w = add <8 x i8> %y, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>487 store <8 x i8> %w, ptr %store488 ret void489}490 491define void @conv_v8f16_to_i128( <8 x half> %a, ptr %store ) {492; CHECK-LABEL: conv_v8f16_to_i128:493; CHECK: @ %bb.0: @ %entry494; CHECK-NEXT: .save {r11, lr}495; CHECK-NEXT: push {r11, lr}496; CHECK-NEXT: adr r1, .LCPI18_0497; CHECK-NEXT: vrev64.16 q9, q0498; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]499; CHECK-NEXT: vrev64.16 q8, q8500; CHECK-NEXT: vadd.f16 q8, q9, q8501; CHECK-NEXT: vrev32.16 q8, q8502; CHECK-NEXT: vmov r12, r2, d17503; CHECK-NEXT: vmov r3, r1, d16504; CHECK-NEXT: subs lr, r2, #1505; CHECK-NEXT: sbcs r2, r12, #0506; CHECK-NEXT: sbcs r1, r1, #0507; CHECK-NEXT: sbc r3, r3, #0508; CHECK-NEXT: str r3, [r0]509; CHECK-NEXT: stmib r0, {r1, r2, lr}510; CHECK-NEXT: pop {r11, pc}511; CHECK-NEXT: .p2align 4512; CHECK-NEXT: @ %bb.1:513; CHECK-NEXT: .LCPI18_0:514; CHECK-NEXT: .short 0xbc00 @ half -1515; CHECK-NEXT: .short 0x3c00 @ half 1516; CHECK-NEXT: .short 0xbc00 @ half -1517; CHECK-NEXT: .short 0x3c00 @ half 1518; CHECK-NEXT: .short 0xbc00 @ half -1519; CHECK-NEXT: .short 0x3c00 @ half 1520; CHECK-NEXT: .short 0xbc00 @ half -1521; CHECK-NEXT: .short 0x3c00 @ half 1522entry:523 %z = fadd <8 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0>524 %y = bitcast <8 x half> %z to i128525 %w = add i128 %y, -1526 store i128 %w, ptr %store527 ret void528}529 530define void @conv_v8f16_to_v2f64( <8 x half> %a, ptr %store ) {531; CHECK-LABEL: conv_v8f16_to_v2f64:532; CHECK: @ %bb.0: @ %entry533; CHECK-NEXT: adr r1, .LCPI19_0534; CHECK-NEXT: vrev64.16 q9, q0535; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]536; CHECK-NEXT: vrev64.16 q8, q8537; CHECK-NEXT: vadd.f16 q8, q9, q8538; CHECK-NEXT: vmov.f64 d18, #1.000000e+00539; CHECK-NEXT: vrev64.16 q8, q8540; CHECK-NEXT: vmov.f64 d19, #-1.000000e+00541; CHECK-NEXT: vadd.f64 d21, d17, d18542; CHECK-NEXT: vadd.f64 d20, d16, d19543; CHECK-NEXT: vst1.64 {d20, d21}, [r0]544; CHECK-NEXT: bx lr545; CHECK-NEXT: .p2align 4546; CHECK-NEXT: @ %bb.1:547; CHECK-NEXT: .LCPI19_0:548; CHECK-NEXT: .short 0xbc00 @ half -1549; CHECK-NEXT: .short 0x3c00 @ half 1550; CHECK-NEXT: .short 0xbc00 @ half -1551; CHECK-NEXT: .short 0x3c00 @ half 1552; CHECK-NEXT: .short 0xbc00 @ half -1553; CHECK-NEXT: .short 0x3c00 @ half 1554; CHECK-NEXT: .short 0xbc00 @ half -1555; CHECK-NEXT: .short 0x3c00 @ half 1556entry:557 %z = fadd <8 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0>558 %y = bitcast <8 x half> %z to <2 x double>559 %w = fadd <2 x double> %y, <double -1.0, double 1.0>560 store <2 x double> %w, ptr %store561 ret void562}563 564define void @conv_v8f16_to_v4i32( <8 x half> %a, ptr %store ) {565; CHECK-LABEL: conv_v8f16_to_v4i32:566; CHECK: @ %bb.0: @ %entry567; CHECK-NEXT: adr r1, .LCPI20_0568; CHECK-NEXT: vrev64.16 q9, q0569; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]570; CHECK-NEXT: adr r1, .LCPI20_1571; CHECK-NEXT: vrev64.16 q8, q8572; CHECK-NEXT: vadd.f16 q8, q9, q8573; CHECK-NEXT: vld1.64 {d18, d19}, [r1:128]574; CHECK-NEXT: vrev64.32 q9, q9575; CHECK-NEXT: vrev32.16 q8, q8576; CHECK-NEXT: vadd.i32 q8, q8, q9577; CHECK-NEXT: vrev64.32 q8, q8578; CHECK-NEXT: vst1.64 {d16, d17}, [r0]579; CHECK-NEXT: bx lr580; CHECK-NEXT: .p2align 4581; CHECK-NEXT: @ %bb.1:582; CHECK-NEXT: .LCPI20_0:583; CHECK-NEXT: .short 0xbc00 @ half -1584; CHECK-NEXT: .short 0x3c00 @ half 1585; CHECK-NEXT: .short 0xbc00 @ half -1586; CHECK-NEXT: .short 0x3c00 @ half 1587; CHECK-NEXT: .short 0xbc00 @ half -1588; CHECK-NEXT: .short 0x3c00 @ half 1589; CHECK-NEXT: .short 0xbc00 @ half -1590; CHECK-NEXT: .short 0x3c00 @ half 1591; CHECK-NEXT: .LCPI20_1:592; CHECK-NEXT: .long 4294967295 @ 0xffffffff593; CHECK-NEXT: .long 1 @ 0x1594; CHECK-NEXT: .long 4294967295 @ 0xffffffff595; CHECK-NEXT: .long 1 @ 0x1596entry:597 %z = fadd <8 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0>598 %y = bitcast <8 x half> %z to <4 x i32>599 %w = add <4 x i32> %y, <i32 -1, i32 1, i32 -1, i32 1>600 store <4 x i32> %w, ptr %store601 ret void602}603 604define void @conv_v8f16_to_v4f32( <8 x half> %a, ptr %store ) {605; CHECK-LABEL: conv_v8f16_to_v4f32:606; CHECK: @ %bb.0: @ %entry607; CHECK-NEXT: adr r1, .LCPI21_0608; CHECK-NEXT: vrev64.16 q9, q0609; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]610; CHECK-NEXT: adr r1, .LCPI21_1611; CHECK-NEXT: vrev64.16 q8, q8612; CHECK-NEXT: vadd.f16 q8, q9, q8613; CHECK-NEXT: vld1.64 {d18, d19}, [r1:128]614; CHECK-NEXT: vrev64.32 q9, q9615; CHECK-NEXT: vrev32.16 q8, q8616; CHECK-NEXT: vadd.f32 q8, q8, q9617; CHECK-NEXT: vrev64.32 q8, q8618; CHECK-NEXT: vst1.64 {d16, d17}, [r0]619; CHECK-NEXT: bx lr620; CHECK-NEXT: .p2align 4621; CHECK-NEXT: @ %bb.1:622; CHECK-NEXT: .LCPI21_0:623; CHECK-NEXT: .short 0xbc00 @ half -1624; CHECK-NEXT: .short 0x3c00 @ half 1625; CHECK-NEXT: .short 0xbc00 @ half -1626; CHECK-NEXT: .short 0x3c00 @ half 1627; CHECK-NEXT: .short 0xbc00 @ half -1628; CHECK-NEXT: .short 0x3c00 @ half 1629; CHECK-NEXT: .short 0xbc00 @ half -1630; CHECK-NEXT: .short 0x3c00 @ half 1631; CHECK-NEXT: .LCPI21_1:632; CHECK-NEXT: .long 0xbf800000 @ float -1633; CHECK-NEXT: .long 0x3f800000 @ float 1634; CHECK-NEXT: .long 0xbf800000 @ float -1635; CHECK-NEXT: .long 0x3f800000 @ float 1636entry:637 %z = fadd <8 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0>638 %y = bitcast <8 x half> %z to <4 x float>639 %w = fadd <4 x float> %y, <float -1.0, float 1.0, float -1.0, float 1.0>640 store <4 x float> %w, ptr %store641 ret void642}643 644define void @conv_v8f16_to_v8i16( <8 x half> %a, ptr %store ) {645; CHECK-LABEL: conv_v8f16_to_v8i16:646; CHECK: @ %bb.0: @ %entry647; CHECK-NEXT: adr r1, .LCPI22_0648; CHECK-NEXT: vrev64.16 q9, q0649; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]650; CHECK-NEXT: adr r1, .LCPI22_1651; CHECK-NEXT: vrev64.16 q8, q8652; CHECK-NEXT: vadd.f16 q8, q9, q8653; CHECK-NEXT: vld1.64 {d18, d19}, [r1:128]654; CHECK-NEXT: vrev64.16 q9, q9655; CHECK-NEXT: vadd.i16 q8, q8, q9656; CHECK-NEXT: vrev64.16 q8, q8657; CHECK-NEXT: vst1.64 {d16, d17}, [r0]658; CHECK-NEXT: bx lr659; CHECK-NEXT: .p2align 4660; CHECK-NEXT: @ %bb.1:661; CHECK-NEXT: .LCPI22_0:662; CHECK-NEXT: .short 0xbc00 @ half -1663; CHECK-NEXT: .short 0x3c00 @ half 1664; CHECK-NEXT: .short 0xbc00 @ half -1665; CHECK-NEXT: .short 0x3c00 @ half 1666; CHECK-NEXT: .short 0xbc00 @ half -1667; CHECK-NEXT: .short 0x3c00 @ half 1668; CHECK-NEXT: .short 0xbc00 @ half -1669; CHECK-NEXT: .short 0x3c00 @ half 1670; CHECK-NEXT: .LCPI22_1:671; CHECK-NEXT: .short 65535 @ 0xffff672; CHECK-NEXT: .short 1 @ 0x1673; CHECK-NEXT: .short 0 @ 0x0674; CHECK-NEXT: .short 7 @ 0x7675; CHECK-NEXT: .short 65535 @ 0xffff676; CHECK-NEXT: .short 1 @ 0x1677; CHECK-NEXT: .short 0 @ 0x0678; CHECK-NEXT: .short 7 @ 0x7679entry:680 %z = fadd <8 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0>681 %y = bitcast <8 x half> %z to <8 x i16>682 %w = add <8 x i16> %y, <i16 -1, i16 1, i16 0, i16 7, i16 -1, i16 1, i16 0, i16 7>683 store <8 x i16> %w, ptr %store684 ret void685}686 687define void @conv_v8f16_to_v8f8( <8 x half> %a, ptr %store ) {688; CHECK-LABEL: conv_v8f16_to_v8f8:689; CHECK: @ %bb.0: @ %entry690; CHECK-NEXT: adr r1, .LCPI23_0691; CHECK-NEXT: vrev64.16 q9, q0692; CHECK-NEXT: vld1.64 {d16, d17}, [r1:128]693; CHECK-NEXT: vrev64.16 q8, q8694; CHECK-NEXT: vadd.f16 q8, q9, q8695; CHECK-NEXT: vmov.i8 q9, #0x1696; CHECK-NEXT: vrev16.8 q8, q8697; CHECK-NEXT: vadd.i8 q8, q8, q9698; CHECK-NEXT: vrev64.8 q8, q8699; CHECK-NEXT: vst1.64 {d16, d17}, [r0]700; CHECK-NEXT: bx lr701; CHECK-NEXT: .p2align 4702; CHECK-NEXT: @ %bb.1:703; CHECK-NEXT: .LCPI23_0:704; CHECK-NEXT: .short 0xbc00 @ half -1705; CHECK-NEXT: .short 0x3c00 @ half 1706; CHECK-NEXT: .short 0xbc00 @ half -1707; CHECK-NEXT: .short 0x3c00 @ half 1708; CHECK-NEXT: .short 0xbc00 @ half -1709; CHECK-NEXT: .short 0x3c00 @ half 1710; CHECK-NEXT: .short 0xbc00 @ half -1711; CHECK-NEXT: .short 0x3c00 @ half 1712entry:713 %z = fadd <8 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0>714 %y = bitcast <8 x half> %z to <16 x i8>715 %w = add <16 x i8> %y, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>716 store <16 x i8> %w, ptr %store717 ret void718}719