2348 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple armeb-eabi -mattr v7,neon -float-abi soft %s -o - | FileCheck %s -check-prefix SOFT3; RUN: llc -mtriple armeb-eabi -mattr v7,neon -float-abi hard %s -o - | FileCheck %s -check-prefix HARD4 5define i64 @test_i64_f64(double %p) {6; SOFT-LABEL: test_i64_f64:7; SOFT: @ %bb.0:8; SOFT-NEXT: vmov d16, r1, r09; SOFT-NEXT: vadd.f64 d16, d16, d1610; SOFT-NEXT: vmov r0, r2, d1611; SOFT-NEXT: adds r1, r0, r012; SOFT-NEXT: adc r0, r2, r213; SOFT-NEXT: bx lr14;15; HARD-LABEL: test_i64_f64:16; HARD: @ %bb.0:17; HARD-NEXT: vadd.f64 d16, d0, d018; HARD-NEXT: vmov r0, r2, d1619; HARD-NEXT: adds r1, r0, r020; HARD-NEXT: adc r0, r2, r221; HARD-NEXT: bx lr22 %1 = fadd double %p, %p23 %2 = bitcast double %1 to i6424 %3 = add i64 %2, %225 ret i64 %326}27 28define i64 @test_i64_v1i64(<1 x i64> %p) {29; SOFT-LABEL: test_i64_v1i64:30; SOFT: @ %bb.0:31; SOFT-NEXT: vmov d16, r1, r032; SOFT-NEXT: vadd.i64 d16, d16, d1633; SOFT-NEXT: vmov r0, r2, d1634; SOFT-NEXT: adds r1, r0, r035; SOFT-NEXT: adc r0, r2, r236; SOFT-NEXT: bx lr37;38; HARD-LABEL: test_i64_v1i64:39; HARD: @ %bb.0:40; HARD-NEXT: vadd.i64 d16, d0, d041; HARD-NEXT: vmov r0, r2, d1642; HARD-NEXT: adds r1, r0, r043; HARD-NEXT: adc r0, r2, r244; HARD-NEXT: bx lr45 %1 = add <1 x i64> %p, %p46 %2 = bitcast <1 x i64> %1 to i6447 %3 = add i64 %2, %248 ret i64 %349}50 51define i64 @test_i64_v2f32(<2 x float> %p) {52; SOFT-LABEL: test_i64_v2f32:53; SOFT: @ %bb.0:54; SOFT-NEXT: vmov d16, r1, r055; SOFT-NEXT: vrev64.32 d16, d1656; SOFT-NEXT: vadd.f32 d16, d16, d1657; SOFT-NEXT: vrev64.32 d16, d1658; SOFT-NEXT: vmov r0, r2, d1659; SOFT-NEXT: adds r1, r0, r060; SOFT-NEXT: adc r0, r2, r261; SOFT-NEXT: bx lr62;63; HARD-LABEL: test_i64_v2f32:64; HARD: @ %bb.0:65; HARD-NEXT: vrev64.32 d16, d066; HARD-NEXT: vadd.f32 d16, d16, d1667; HARD-NEXT: vrev64.32 d16, d1668; HARD-NEXT: vmov r0, r2, d1669; HARD-NEXT: adds r1, r0, r070; HARD-NEXT: adc r0, r2, r271; HARD-NEXT: bx lr72 %1 = fadd <2 x float> %p, %p73 %2 = bitcast <2 x float> %1 to i6474 %3 = add i64 %2, %275 ret i64 %376}77 78define i64 @test_i64_v2i32(<2 x i32> %p) {79; SOFT-LABEL: test_i64_v2i32:80; SOFT: @ %bb.0:81; SOFT-NEXT: vmov d16, r1, r082; SOFT-NEXT: vrev64.32 d16, d1683; SOFT-NEXT: vadd.i32 d16, d16, d1684; SOFT-NEXT: vrev64.32 d16, d1685; SOFT-NEXT: vmov r0, r2, d1686; SOFT-NEXT: adds r1, r0, r087; SOFT-NEXT: adc r0, r2, r288; SOFT-NEXT: bx lr89;90; HARD-LABEL: test_i64_v2i32:91; HARD: @ %bb.0:92; HARD-NEXT: vrev64.32 d16, d093; HARD-NEXT: vadd.i32 d16, d16, d1694; HARD-NEXT: vrev64.32 d16, d1695; HARD-NEXT: vmov r0, r2, d1696; HARD-NEXT: adds r1, r0, r097; HARD-NEXT: adc r0, r2, r298; HARD-NEXT: bx lr99 %1 = add <2 x i32> %p, %p100 %2 = bitcast <2 x i32> %1 to i64101 %3 = add i64 %2, %2102 ret i64 %3103}104 105define i64 @test_i64_v4i16(<4 x i16> %p) {106; SOFT-LABEL: test_i64_v4i16:107; SOFT: @ %bb.0:108; SOFT-NEXT: vmov d16, r1, r0109; SOFT-NEXT: vrev64.16 d16, d16110; SOFT-NEXT: vadd.i16 d16, d16, d16111; SOFT-NEXT: vrev64.16 d16, d16112; SOFT-NEXT: vmov r0, r2, d16113; SOFT-NEXT: adds r1, r0, r0114; SOFT-NEXT: adc r0, r2, r2115; SOFT-NEXT: bx lr116;117; HARD-LABEL: test_i64_v4i16:118; HARD: @ %bb.0:119; HARD-NEXT: vrev64.16 d16, d0120; HARD-NEXT: vadd.i16 d16, d16, d16121; HARD-NEXT: vrev64.16 d16, d16122; HARD-NEXT: vmov r0, r2, d16123; HARD-NEXT: adds r1, r0, r0124; HARD-NEXT: adc r0, r2, r2125; HARD-NEXT: bx lr126 %1 = add <4 x i16> %p, %p127 %2 = bitcast <4 x i16> %1 to i64128 %3 = add i64 %2, %2129 ret i64 %3130}131 132define i64 @test_i64_v8i8(<8 x i8> %p) {133; SOFT-LABEL: test_i64_v8i8:134; SOFT: @ %bb.0:135; SOFT-NEXT: vmov d16, r1, r0136; SOFT-NEXT: vrev64.8 d16, d16137; SOFT-NEXT: vadd.i8 d16, d16, d16138; SOFT-NEXT: vrev64.8 d16, d16139; SOFT-NEXT: vmov r0, r2, d16140; SOFT-NEXT: adds r1, r0, r0141; SOFT-NEXT: adc r0, r2, r2142; SOFT-NEXT: bx lr143;144; HARD-LABEL: test_i64_v8i8:145; HARD: @ %bb.0:146; HARD-NEXT: vrev64.8 d16, d0147; HARD-NEXT: vadd.i8 d16, d16, d16148; HARD-NEXT: vrev64.8 d16, d16149; HARD-NEXT: vmov r0, r2, d16150; HARD-NEXT: adds r1, r0, r0151; HARD-NEXT: adc r0, r2, r2152; HARD-NEXT: bx lr153 %1 = add <8 x i8> %p, %p154 %2 = bitcast <8 x i8> %1 to i64155 %3 = add i64 %2, %2156 ret i64 %3157}158 159define double @test_f64_i64(i64 %p) {160; SOFT-LABEL: test_f64_i64:161; SOFT: @ %bb.0:162; SOFT-NEXT: adds r1, r1, r1163; SOFT-NEXT: adc r0, r0, r0164; SOFT-NEXT: vmov d16, r1, r0165; SOFT-NEXT: vadd.f64 d16, d16, d16166; SOFT-NEXT: vmov r1, r0, d16167; SOFT-NEXT: bx lr168;169; HARD-LABEL: test_f64_i64:170; HARD: @ %bb.0:171; HARD-NEXT: adds r1, r1, r1172; HARD-NEXT: adc r0, r0, r0173; HARD-NEXT: vmov d16, r1, r0174; HARD-NEXT: vadd.f64 d0, d16, d16175; HARD-NEXT: bx lr176 %1 = add i64 %p, %p177 %2 = bitcast i64 %1 to double178 %3 = fadd double %2, %2179 ret double %3180}181 182define double @test_f64_v1i64(<1 x i64> %p) {183; SOFT-LABEL: test_f64_v1i64:184; SOFT: @ %bb.0:185; SOFT-NEXT: vmov d16, r1, r0186; SOFT-NEXT: vadd.i64 d16, d16, d16187; SOFT-NEXT: vadd.f64 d16, d16, d16188; SOFT-NEXT: vmov r1, r0, d16189; SOFT-NEXT: bx lr190;191; HARD-LABEL: test_f64_v1i64:192; HARD: @ %bb.0:193; HARD-NEXT: vadd.i64 d16, d0, d0194; HARD-NEXT: vadd.f64 d0, d16, d16195; HARD-NEXT: bx lr196 %1 = add <1 x i64> %p, %p197 %2 = bitcast <1 x i64> %1 to double198 %3 = fadd double %2, %2199 ret double %3200}201 202define double @test_f64_v2f32(<2 x float> %p) {203; SOFT-LABEL: test_f64_v2f32:204; SOFT: @ %bb.0:205; SOFT-NEXT: vmov d16, r1, r0206; SOFT-NEXT: vrev64.32 d16, d16207; SOFT-NEXT: vadd.f32 d16, d16, d16208; SOFT-NEXT: vrev64.32 d16, d16209; SOFT-NEXT: vadd.f64 d16, d16, d16210; SOFT-NEXT: vmov r1, r0, d16211; SOFT-NEXT: bx lr212;213; HARD-LABEL: test_f64_v2f32:214; HARD: @ %bb.0:215; HARD-NEXT: vrev64.32 d16, d0216; HARD-NEXT: vadd.f32 d16, d16, d16217; HARD-NEXT: vrev64.32 d16, d16218; HARD-NEXT: vadd.f64 d0, d16, d16219; HARD-NEXT: bx lr220 %1 = fadd <2 x float> %p, %p221 %2 = bitcast <2 x float> %1 to double222 %3 = fadd double %2, %2223 ret double %3224}225 226define double @test_f64_v2i32(<2 x i32> %p) {227; SOFT-LABEL: test_f64_v2i32:228; SOFT: @ %bb.0:229; SOFT-NEXT: vmov d16, r1, r0230; SOFT-NEXT: vrev64.32 d16, d16231; SOFT-NEXT: vadd.i32 d16, d16, d16232; SOFT-NEXT: vrev64.32 d16, d16233; SOFT-NEXT: vadd.f64 d16, d16, d16234; SOFT-NEXT: vmov r1, r0, d16235; SOFT-NEXT: bx lr236;237; HARD-LABEL: test_f64_v2i32:238; HARD: @ %bb.0:239; HARD-NEXT: vrev64.32 d16, d0240; HARD-NEXT: vadd.i32 d16, d16, d16241; HARD-NEXT: vrev64.32 d16, d16242; HARD-NEXT: vadd.f64 d0, d16, d16243; HARD-NEXT: bx lr244 %1 = add <2 x i32> %p, %p245 %2 = bitcast <2 x i32> %1 to double246 %3 = fadd double %2, %2247 ret double %3248}249 250define double @test_f64_v4i16(<4 x i16> %p) {251; SOFT-LABEL: test_f64_v4i16:252; SOFT: @ %bb.0:253; SOFT-NEXT: vmov d16, r1, r0254; SOFT-NEXT: vrev64.16 d16, d16255; SOFT-NEXT: vadd.i16 d16, d16, d16256; SOFT-NEXT: vrev64.16 d16, d16257; SOFT-NEXT: vadd.f64 d16, d16, d16258; SOFT-NEXT: vmov r1, r0, d16259; SOFT-NEXT: bx lr260;261; HARD-LABEL: test_f64_v4i16:262; HARD: @ %bb.0:263; HARD-NEXT: vrev64.16 d16, d0264; HARD-NEXT: vadd.i16 d16, d16, d16265; HARD-NEXT: vrev64.16 d16, d16266; HARD-NEXT: vadd.f64 d0, d16, d16267; HARD-NEXT: bx lr268 %1 = add <4 x i16> %p, %p269 %2 = bitcast <4 x i16> %1 to double270 %3 = fadd double %2, %2271 ret double %3272}273 274define double @test_f64_v8i8(<8 x i8> %p) {275; SOFT-LABEL: test_f64_v8i8:276; SOFT: @ %bb.0:277; SOFT-NEXT: vmov d16, r1, r0278; SOFT-NEXT: vrev64.8 d16, d16279; SOFT-NEXT: vadd.i8 d16, d16, d16280; SOFT-NEXT: vrev64.8 d16, d16281; SOFT-NEXT: vadd.f64 d16, d16, d16282; SOFT-NEXT: vmov r1, r0, d16283; SOFT-NEXT: bx lr284;285; HARD-LABEL: test_f64_v8i8:286; HARD: @ %bb.0:287; HARD-NEXT: vrev64.8 d16, d0288; HARD-NEXT: vadd.i8 d16, d16, d16289; HARD-NEXT: vrev64.8 d16, d16290; HARD-NEXT: vadd.f64 d0, d16, d16291; HARD-NEXT: bx lr292 %1 = add <8 x i8> %p, %p293 %2 = bitcast <8 x i8> %1 to double294 %3 = fadd double %2, %2295 ret double %3296}297 298define <1 x i64> @test_v1i64_i64(i64 %p) {299; SOFT-LABEL: test_v1i64_i64:300; SOFT: @ %bb.0:301; SOFT-NEXT: adds r1, r1, r1302; SOFT-NEXT: adc r0, r0, r0303; SOFT-NEXT: vmov d16, r1, r0304; SOFT-NEXT: vadd.i64 d16, d16, d16305; SOFT-NEXT: vmov r1, r0, d16306; SOFT-NEXT: bx lr307;308; HARD-LABEL: test_v1i64_i64:309; HARD: @ %bb.0:310; HARD-NEXT: adds r1, r1, r1311; HARD-NEXT: adc r0, r0, r0312; HARD-NEXT: vmov d16, r1, r0313; HARD-NEXT: vadd.i64 d0, d16, d16314; HARD-NEXT: bx lr315 %1 = add i64 %p, %p316 %2 = bitcast i64 %1 to <1 x i64>317 %3 = add <1 x i64> %2, %2318 ret <1 x i64> %3319}320 321define <1 x i64> @test_v1i64_f64(double %p) {322; SOFT-LABEL: test_v1i64_f64:323; SOFT: @ %bb.0:324; SOFT-NEXT: vmov d16, r1, r0325; SOFT-NEXT: vadd.f64 d16, d16, d16326; SOFT-NEXT: vadd.i64 d16, d16, d16327; SOFT-NEXT: vmov r1, r0, d16328; SOFT-NEXT: bx lr329;330; HARD-LABEL: test_v1i64_f64:331; HARD: @ %bb.0:332; HARD-NEXT: vadd.f64 d16, d0, d0333; HARD-NEXT: vadd.i64 d0, d16, d16334; HARD-NEXT: bx lr335 %1 = fadd double %p, %p336 %2 = bitcast double %1 to <1 x i64>337 %3 = add <1 x i64> %2, %2338 ret <1 x i64> %3339}340 341define <1 x i64> @test_v1i64_v2f32(<2 x float> %p) {342; SOFT-LABEL: test_v1i64_v2f32:343; SOFT: @ %bb.0:344; SOFT-NEXT: vmov d16, r1, r0345; SOFT-NEXT: vrev64.32 d16, d16346; SOFT-NEXT: vadd.f32 d16, d16, d16347; SOFT-NEXT: vrev64.32 d16, d16348; SOFT-NEXT: vadd.i64 d16, d16, d16349; SOFT-NEXT: vmov r1, r0, d16350; SOFT-NEXT: bx lr351;352; HARD-LABEL: test_v1i64_v2f32:353; HARD: @ %bb.0:354; HARD-NEXT: vrev64.32 d16, d0355; HARD-NEXT: vadd.f32 d16, d16, d16356; HARD-NEXT: vrev64.32 d16, d16357; HARD-NEXT: vadd.i64 d0, d16, d16358; HARD-NEXT: bx lr359 %1 = fadd <2 x float> %p, %p360 %2 = bitcast <2 x float> %1 to <1 x i64>361 %3 = add <1 x i64> %2, %2362 ret <1 x i64> %3363}364 365define <1 x i64> @test_v1i64_v2i32(<2 x i32> %p) {366; SOFT-LABEL: test_v1i64_v2i32:367; SOFT: @ %bb.0:368; SOFT-NEXT: vmov d16, r1, r0369; SOFT-NEXT: vrev64.32 d16, d16370; SOFT-NEXT: vadd.i32 d16, d16, d16371; SOFT-NEXT: vrev64.32 d16, d16372; SOFT-NEXT: vadd.i64 d16, d16, d16373; SOFT-NEXT: vmov r1, r0, d16374; SOFT-NEXT: bx lr375;376; HARD-LABEL: test_v1i64_v2i32:377; HARD: @ %bb.0:378; HARD-NEXT: vrev64.32 d16, d0379; HARD-NEXT: vadd.i32 d16, d16, d16380; HARD-NEXT: vrev64.32 d16, d16381; HARD-NEXT: vadd.i64 d0, d16, d16382; HARD-NEXT: bx lr383 %1 = add <2 x i32> %p, %p384 %2 = bitcast <2 x i32> %1 to <1 x i64>385 %3 = add <1 x i64> %2, %2386 ret <1 x i64> %3387}388 389define <1 x i64> @test_v1i64_v4i16(<4 x i16> %p) {390; SOFT-LABEL: test_v1i64_v4i16:391; SOFT: @ %bb.0:392; SOFT-NEXT: vmov d16, r1, r0393; SOFT-NEXT: vrev64.16 d16, d16394; SOFT-NEXT: vadd.i16 d16, d16, d16395; SOFT-NEXT: vrev64.16 d16, d16396; SOFT-NEXT: vadd.i64 d16, d16, d16397; SOFT-NEXT: vmov r1, r0, d16398; SOFT-NEXT: bx lr399;400; HARD-LABEL: test_v1i64_v4i16:401; HARD: @ %bb.0:402; HARD-NEXT: vrev64.16 d16, d0403; HARD-NEXT: vadd.i16 d16, d16, d16404; HARD-NEXT: vrev64.16 d16, d16405; HARD-NEXT: vadd.i64 d0, d16, d16406; HARD-NEXT: bx lr407 %1 = add <4 x i16> %p, %p408 %2 = bitcast <4 x i16> %1 to <1 x i64>409 %3 = add <1 x i64> %2, %2410 ret <1 x i64> %3411}412 413define <1 x i64> @test_v1i64_v8i8(<8 x i8> %p) {414; SOFT-LABEL: test_v1i64_v8i8:415; SOFT: @ %bb.0:416; SOFT-NEXT: vmov d16, r1, r0417; SOFT-NEXT: vrev64.8 d16, d16418; SOFT-NEXT: vadd.i8 d16, d16, d16419; SOFT-NEXT: vrev64.8 d16, d16420; SOFT-NEXT: vadd.i64 d16, d16, d16421; SOFT-NEXT: vmov r1, r0, d16422; SOFT-NEXT: bx lr423;424; HARD-LABEL: test_v1i64_v8i8:425; HARD: @ %bb.0:426; HARD-NEXT: vrev64.8 d16, d0427; HARD-NEXT: vadd.i8 d16, d16, d16428; HARD-NEXT: vrev64.8 d16, d16429; HARD-NEXT: vadd.i64 d0, d16, d16430; HARD-NEXT: bx lr431 %1 = add <8 x i8> %p, %p432 %2 = bitcast <8 x i8> %1 to <1 x i64>433 %3 = add <1 x i64> %2, %2434 ret <1 x i64> %3435}436 437define <2 x float> @test_v2f32_i64(i64 %p) {438; SOFT-LABEL: test_v2f32_i64:439; SOFT: @ %bb.0:440; SOFT-NEXT: adds r1, r1, r1441; SOFT-NEXT: adc r0, r0, r0442; SOFT-NEXT: vmov d16, r1, r0443; SOFT-NEXT: vrev64.32 d16, d16444; SOFT-NEXT: vadd.f32 d16, d16, d16445; SOFT-NEXT: vrev64.32 d16, d16446; SOFT-NEXT: vmov r1, r0, d16447; SOFT-NEXT: bx lr448;449; HARD-LABEL: test_v2f32_i64:450; HARD: @ %bb.0:451; HARD-NEXT: adds r1, r1, r1452; HARD-NEXT: adc r0, r0, r0453; HARD-NEXT: vmov d16, r1, r0454; HARD-NEXT: vrev64.32 d16, d16455; HARD-NEXT: vadd.f32 d16, d16, d16456; HARD-NEXT: vrev64.32 d0, d16457; HARD-NEXT: bx lr458 %1 = add i64 %p, %p459 %2 = bitcast i64 %1 to <2 x float>460 %3 = fadd <2 x float> %2, %2461 ret <2 x float> %3462}463 464define <2 x float> @test_v2f32_f64(double %p) {465; SOFT-LABEL: test_v2f32_f64:466; SOFT: @ %bb.0:467; SOFT-NEXT: vmov d16, r1, r0468; SOFT-NEXT: vadd.f64 d16, d16, d16469; SOFT-NEXT: vrev64.32 d16, d16470; SOFT-NEXT: vadd.f32 d16, d16, d16471; SOFT-NEXT: vrev64.32 d16, d16472; SOFT-NEXT: vmov r1, r0, d16473; SOFT-NEXT: bx lr474;475; HARD-LABEL: test_v2f32_f64:476; HARD: @ %bb.0:477; HARD-NEXT: vadd.f64 d16, d0, d0478; HARD-NEXT: vrev64.32 d16, d16479; HARD-NEXT: vadd.f32 d16, d16, d16480; HARD-NEXT: vrev64.32 d0, d16481; HARD-NEXT: bx lr482 %1 = fadd double %p, %p483 %2 = bitcast double %1 to <2 x float>484 %3 = fadd <2 x float> %2, %2485 ret <2 x float> %3486}487 488define <2 x float> @test_v2f32_v1i64(<1 x i64> %p) {489; SOFT-LABEL: test_v2f32_v1i64:490; SOFT: @ %bb.0:491; SOFT-NEXT: vmov d16, r1, r0492; SOFT-NEXT: vadd.i64 d16, d16, d16493; SOFT-NEXT: vrev64.32 d16, d16494; SOFT-NEXT: vadd.f32 d16, d16, d16495; SOFT-NEXT: vrev64.32 d16, d16496; SOFT-NEXT: vmov r1, r0, d16497; SOFT-NEXT: bx lr498;499; HARD-LABEL: test_v2f32_v1i64:500; HARD: @ %bb.0:501; HARD-NEXT: vadd.i64 d16, d0, d0502; HARD-NEXT: vrev64.32 d16, d16503; HARD-NEXT: vadd.f32 d16, d16, d16504; HARD-NEXT: vrev64.32 d0, d16505; HARD-NEXT: bx lr506 %1 = add <1 x i64> %p, %p507 %2 = bitcast <1 x i64> %1 to <2 x float>508 %3 = fadd <2 x float> %2, %2509 ret <2 x float> %3510}511 512define <2 x float> @test_v2f32_v2i32(<2 x i32> %p) {513; SOFT-LABEL: test_v2f32_v2i32:514; SOFT: @ %bb.0:515; SOFT-NEXT: vmov d16, r1, r0516; SOFT-NEXT: vrev64.32 d16, d16517; SOFT-NEXT: vadd.i32 d16, d16, d16518; SOFT-NEXT: vadd.f32 d16, d16, d16519; SOFT-NEXT: vrev64.32 d16, d16520; SOFT-NEXT: vmov r1, r0, d16521; SOFT-NEXT: bx lr522;523; HARD-LABEL: test_v2f32_v2i32:524; HARD: @ %bb.0:525; HARD-NEXT: vrev64.32 d16, d0526; HARD-NEXT: vadd.i32 d16, d16, d16527; HARD-NEXT: vadd.f32 d16, d16, d16528; HARD-NEXT: vrev64.32 d0, d16529; HARD-NEXT: bx lr530 %1 = add <2 x i32> %p, %p531 %2 = bitcast <2 x i32> %1 to <2 x float>532 %3 = fadd <2 x float> %2, %2533 ret <2 x float> %3534}535 536define <2 x float> @test_v2f32_v4i16(<4 x i16> %p) {537; SOFT-LABEL: test_v2f32_v4i16:538; SOFT: @ %bb.0:539; SOFT-NEXT: vmov d16, r1, r0540; SOFT-NEXT: vrev64.16 d16, d16541; SOFT-NEXT: vadd.i16 d16, d16, d16542; SOFT-NEXT: vrev32.16 d16, d16543; SOFT-NEXT: vadd.f32 d16, d16, d16544; SOFT-NEXT: vrev64.32 d16, d16545; SOFT-NEXT: vmov r1, r0, d16546; SOFT-NEXT: bx lr547;548; HARD-LABEL: test_v2f32_v4i16:549; HARD: @ %bb.0:550; HARD-NEXT: vrev64.16 d16, d0551; HARD-NEXT: vadd.i16 d16, d16, d16552; HARD-NEXT: vrev32.16 d16, d16553; HARD-NEXT: vadd.f32 d16, d16, d16554; HARD-NEXT: vrev64.32 d0, d16555; HARD-NEXT: bx lr556 %1 = add <4 x i16> %p, %p557 %2 = bitcast <4 x i16> %1 to <2 x float>558 %3 = fadd <2 x float> %2, %2559 ret <2 x float> %3560}561 562define <2 x float> @test_v2f32_v8i8(<8 x i8> %p) {563; SOFT-LABEL: test_v2f32_v8i8:564; SOFT: @ %bb.0:565; SOFT-NEXT: vmov d16, r1, r0566; SOFT-NEXT: vrev64.8 d16, d16567; SOFT-NEXT: vadd.i8 d16, d16, d16568; SOFT-NEXT: vrev32.8 d16, d16569; SOFT-NEXT: vadd.f32 d16, d16, d16570; SOFT-NEXT: vrev64.32 d16, d16571; SOFT-NEXT: vmov r1, r0, d16572; SOFT-NEXT: bx lr573;574; HARD-LABEL: test_v2f32_v8i8:575; HARD: @ %bb.0:576; HARD-NEXT: vrev64.8 d16, d0577; HARD-NEXT: vadd.i8 d16, d16, d16578; HARD-NEXT: vrev32.8 d16, d16579; HARD-NEXT: vadd.f32 d16, d16, d16580; HARD-NEXT: vrev64.32 d0, d16581; HARD-NEXT: bx lr582 %1 = add <8 x i8> %p, %p583 %2 = bitcast <8 x i8> %1 to <2 x float>584 %3 = fadd <2 x float> %2, %2585 ret <2 x float> %3586}587 588define <2 x i32> @test_v2i32_i64(i64 %p) {589; SOFT-LABEL: test_v2i32_i64:590; SOFT: @ %bb.0:591; SOFT-NEXT: adds r1, r1, r1592; SOFT-NEXT: adc r0, r0, r0593; SOFT-NEXT: vmov d16, r1, r0594; SOFT-NEXT: vrev64.32 d16, d16595; SOFT-NEXT: vadd.i32 d16, d16, d16596; SOFT-NEXT: vrev64.32 d16, d16597; SOFT-NEXT: vmov r1, r0, d16598; SOFT-NEXT: bx lr599;600; HARD-LABEL: test_v2i32_i64:601; HARD: @ %bb.0:602; HARD-NEXT: adds r1, r1, r1603; HARD-NEXT: adc r0, r0, r0604; HARD-NEXT: vmov d16, r1, r0605; HARD-NEXT: vrev64.32 d16, d16606; HARD-NEXT: vadd.i32 d16, d16, d16607; HARD-NEXT: vrev64.32 d0, d16608; HARD-NEXT: bx lr609 %1 = add i64 %p, %p610 %2 = bitcast i64 %1 to <2 x i32>611 %3 = add <2 x i32> %2, %2612 ret <2 x i32> %3613}614 615define <2 x i32> @test_v2i32_f64(double %p) {616; SOFT-LABEL: test_v2i32_f64:617; SOFT: @ %bb.0:618; SOFT-NEXT: vmov d16, r1, r0619; SOFT-NEXT: vadd.f64 d16, d16, d16620; SOFT-NEXT: vrev64.32 d16, d16621; SOFT-NEXT: vadd.i32 d16, d16, d16622; SOFT-NEXT: vrev64.32 d16, d16623; SOFT-NEXT: vmov r1, r0, d16624; SOFT-NEXT: bx lr625;626; HARD-LABEL: test_v2i32_f64:627; HARD: @ %bb.0:628; HARD-NEXT: vadd.f64 d16, d0, d0629; HARD-NEXT: vrev64.32 d16, d16630; HARD-NEXT: vadd.i32 d16, d16, d16631; HARD-NEXT: vrev64.32 d0, d16632; HARD-NEXT: bx lr633 %1 = fadd double %p, %p634 %2 = bitcast double %1 to <2 x i32>635 %3 = add <2 x i32> %2, %2636 ret <2 x i32> %3637}638 639define <2 x i32> @test_v2i32_v1i64(<1 x i64> %p) {640; SOFT-LABEL: test_v2i32_v1i64:641; SOFT: @ %bb.0:642; SOFT-NEXT: vmov d16, r1, r0643; SOFT-NEXT: vadd.i64 d16, d16, d16644; SOFT-NEXT: vrev64.32 d16, d16645; SOFT-NEXT: vadd.i32 d16, d16, d16646; SOFT-NEXT: vrev64.32 d16, d16647; SOFT-NEXT: vmov r1, r0, d16648; SOFT-NEXT: bx lr649;650; HARD-LABEL: test_v2i32_v1i64:651; HARD: @ %bb.0:652; HARD-NEXT: vadd.i64 d16, d0, d0653; HARD-NEXT: vrev64.32 d16, d16654; HARD-NEXT: vadd.i32 d16, d16, d16655; HARD-NEXT: vrev64.32 d0, d16656; HARD-NEXT: bx lr657 %1 = add <1 x i64> %p, %p658 %2 = bitcast <1 x i64> %1 to <2 x i32>659 %3 = add <2 x i32> %2, %2660 ret <2 x i32> %3661}662 663define <2 x i32> @test_v2i32_v2f32(<2 x float> %p) {664; SOFT-LABEL: test_v2i32_v2f32:665; SOFT: @ %bb.0:666; SOFT-NEXT: vmov d16, r1, r0667; SOFT-NEXT: vrev64.32 d16, d16668; SOFT-NEXT: vadd.f32 d16, d16, d16669; SOFT-NEXT: vadd.i32 d16, d16, d16670; SOFT-NEXT: vrev64.32 d16, d16671; SOFT-NEXT: vmov r1, r0, d16672; SOFT-NEXT: bx lr673;674; HARD-LABEL: test_v2i32_v2f32:675; HARD: @ %bb.0:676; HARD-NEXT: vrev64.32 d16, d0677; HARD-NEXT: vadd.f32 d16, d16, d16678; HARD-NEXT: vadd.i32 d16, d16, d16679; HARD-NEXT: vrev64.32 d0, d16680; HARD-NEXT: bx lr681 %1 = fadd <2 x float> %p, %p682 %2 = bitcast <2 x float> %1 to <2 x i32>683 %3 = add <2 x i32> %2, %2684 ret <2 x i32> %3685}686 687define <2 x i32> @test_v2i32_v4i16(<4 x i16> %p) {688; SOFT-LABEL: test_v2i32_v4i16:689; SOFT: @ %bb.0:690; SOFT-NEXT: vmov d16, r1, r0691; SOFT-NEXT: vrev64.16 d16, d16692; SOFT-NEXT: vadd.i16 d16, d16, d16693; SOFT-NEXT: vrev32.16 d16, d16694; SOFT-NEXT: vadd.i32 d16, d16, d16695; SOFT-NEXT: vrev64.32 d16, d16696; SOFT-NEXT: vmov r1, r0, d16697; SOFT-NEXT: bx lr698;699; HARD-LABEL: test_v2i32_v4i16:700; HARD: @ %bb.0:701; HARD-NEXT: vrev64.16 d16, d0702; HARD-NEXT: vadd.i16 d16, d16, d16703; HARD-NEXT: vrev32.16 d16, d16704; HARD-NEXT: vadd.i32 d16, d16, d16705; HARD-NEXT: vrev64.32 d0, d16706; HARD-NEXT: bx lr707 %1 = add <4 x i16> %p, %p708 %2 = bitcast <4 x i16> %1 to <2 x i32>709 %3 = add <2 x i32> %2, %2710 ret <2 x i32> %3711}712 713define <2 x i32> @test_v2i32_v8i8(<8 x i8> %p) {714; SOFT-LABEL: test_v2i32_v8i8:715; SOFT: @ %bb.0:716; SOFT-NEXT: vmov d16, r1, r0717; SOFT-NEXT: vrev64.8 d16, d16718; SOFT-NEXT: vadd.i8 d16, d16, d16719; SOFT-NEXT: vrev32.8 d16, d16720; SOFT-NEXT: vadd.i32 d16, d16, d16721; SOFT-NEXT: vrev64.32 d16, d16722; SOFT-NEXT: vmov r1, r0, d16723; SOFT-NEXT: bx lr724;725; HARD-LABEL: test_v2i32_v8i8:726; HARD: @ %bb.0:727; HARD-NEXT: vrev64.8 d16, d0728; HARD-NEXT: vadd.i8 d16, d16, d16729; HARD-NEXT: vrev32.8 d16, d16730; HARD-NEXT: vadd.i32 d16, d16, d16731; HARD-NEXT: vrev64.32 d0, d16732; HARD-NEXT: bx lr733 %1 = add <8 x i8> %p, %p734 %2 = bitcast <8 x i8> %1 to <2 x i32>735 %3 = add <2 x i32> %2, %2736 ret <2 x i32> %3737}738 739define <4 x i16> @test_v4i16_i64(i64 %p) {740; SOFT-LABEL: test_v4i16_i64:741; SOFT: @ %bb.0:742; SOFT-NEXT: adds r1, r1, r1743; SOFT-NEXT: adc r0, r0, r0744; SOFT-NEXT: vmov d16, r1, r0745; SOFT-NEXT: vrev64.16 d16, d16746; SOFT-NEXT: vadd.i16 d16, d16, d16747; SOFT-NEXT: vrev64.16 d16, d16748; SOFT-NEXT: vmov r1, r0, d16749; SOFT-NEXT: bx lr750;751; HARD-LABEL: test_v4i16_i64:752; HARD: @ %bb.0:753; HARD-NEXT: adds r1, r1, r1754; HARD-NEXT: adc r0, r0, r0755; HARD-NEXT: vmov d16, r1, r0756; HARD-NEXT: vrev64.16 d16, d16757; HARD-NEXT: vadd.i16 d16, d16, d16758; HARD-NEXT: vrev64.16 d0, d16759; HARD-NEXT: bx lr760 %1 = add i64 %p, %p761 %2 = bitcast i64 %1 to <4 x i16>762 %3 = add <4 x i16> %2, %2763 ret <4 x i16> %3764}765 766define <4 x i16> @test_v4i16_f64(double %p) {767; SOFT-LABEL: test_v4i16_f64:768; SOFT: @ %bb.0:769; SOFT-NEXT: vmov d16, r1, r0770; SOFT-NEXT: vadd.f64 d16, d16, d16771; SOFT-NEXT: vrev64.16 d16, d16772; SOFT-NEXT: vadd.i16 d16, d16, d16773; SOFT-NEXT: vrev64.16 d16, d16774; SOFT-NEXT: vmov r1, r0, d16775; SOFT-NEXT: bx lr776;777; HARD-LABEL: test_v4i16_f64:778; HARD: @ %bb.0:779; HARD-NEXT: vadd.f64 d16, d0, d0780; HARD-NEXT: vrev64.16 d16, d16781; HARD-NEXT: vadd.i16 d16, d16, d16782; HARD-NEXT: vrev64.16 d0, d16783; HARD-NEXT: bx lr784 %1 = fadd double %p, %p785 %2 = bitcast double %1 to <4 x i16>786 %3 = add <4 x i16> %2, %2787 ret <4 x i16> %3788}789 790define <4 x i16> @test_v4i16_v1i64(<1 x i64> %p) {791; SOFT-LABEL: test_v4i16_v1i64:792; SOFT: @ %bb.0:793; SOFT-NEXT: vmov d16, r1, r0794; SOFT-NEXT: vadd.i64 d16, d16, d16795; SOFT-NEXT: vrev64.16 d16, d16796; SOFT-NEXT: vadd.i16 d16, d16, d16797; SOFT-NEXT: vrev64.16 d16, d16798; SOFT-NEXT: vmov r1, r0, d16799; SOFT-NEXT: bx lr800;801; HARD-LABEL: test_v4i16_v1i64:802; HARD: @ %bb.0:803; HARD-NEXT: vadd.i64 d16, d0, d0804; HARD-NEXT: vrev64.16 d16, d16805; HARD-NEXT: vadd.i16 d16, d16, d16806; HARD-NEXT: vrev64.16 d0, d16807; HARD-NEXT: bx lr808 %1 = add <1 x i64> %p, %p809 %2 = bitcast <1 x i64> %1 to <4 x i16>810 %3 = add <4 x i16> %2, %2811 ret <4 x i16> %3812}813 814define <4 x i16> @test_v4i16_v2f32(<2 x float> %p) {815; SOFT-LABEL: test_v4i16_v2f32:816; SOFT: @ %bb.0:817; SOFT-NEXT: vmov d16, r1, r0818; SOFT-NEXT: vrev64.32 d16, d16819; SOFT-NEXT: vadd.f32 d16, d16, d16820; SOFT-NEXT: vrev32.16 d16, d16821; SOFT-NEXT: vadd.i16 d16, d16, d16822; SOFT-NEXT: vrev64.16 d16, d16823; SOFT-NEXT: vmov r1, r0, d16824; SOFT-NEXT: bx lr825;826; HARD-LABEL: test_v4i16_v2f32:827; HARD: @ %bb.0:828; HARD-NEXT: vrev64.32 d16, d0829; HARD-NEXT: vadd.f32 d16, d16, d16830; HARD-NEXT: vrev32.16 d16, d16831; HARD-NEXT: vadd.i16 d16, d16, d16832; HARD-NEXT: vrev64.16 d0, d16833; HARD-NEXT: bx lr834 %1 = fadd <2 x float> %p, %p835 %2 = bitcast <2 x float> %1 to <4 x i16>836 %3 = add <4 x i16> %2, %2837 ret <4 x i16> %3838}839 840define <4 x i16> @test_v4i16_v2i32(<2 x i32> %p) {841; SOFT-LABEL: test_v4i16_v2i32:842; SOFT: @ %bb.0:843; SOFT-NEXT: vmov d16, r1, r0844; SOFT-NEXT: vrev64.32 d16, d16845; SOFT-NEXT: vadd.i32 d16, d16, d16846; SOFT-NEXT: vrev32.16 d16, d16847; SOFT-NEXT: vadd.i16 d16, d16, d16848; SOFT-NEXT: vrev64.16 d16, d16849; SOFT-NEXT: vmov r1, r0, d16850; SOFT-NEXT: bx lr851;852; HARD-LABEL: test_v4i16_v2i32:853; HARD: @ %bb.0:854; HARD-NEXT: vrev64.32 d16, d0855; HARD-NEXT: vadd.i32 d16, d16, d16856; HARD-NEXT: vrev32.16 d16, d16857; HARD-NEXT: vadd.i16 d16, d16, d16858; HARD-NEXT: vrev64.16 d0, d16859; HARD-NEXT: bx lr860 %1 = add <2 x i32> %p, %p861 %2 = bitcast <2 x i32> %1 to <4 x i16>862 %3 = add <4 x i16> %2, %2863 ret <4 x i16> %3864}865 866define <4 x i16> @test_v4i16_v8i8(<8 x i8> %p) {867; SOFT-LABEL: test_v4i16_v8i8:868; SOFT: @ %bb.0:869; SOFT-NEXT: vmov d16, r1, r0870; SOFT-NEXT: vrev64.8 d16, d16871; SOFT-NEXT: vadd.i8 d16, d16, d16872; SOFT-NEXT: vrev16.8 d16, d16873; SOFT-NEXT: vadd.i16 d16, d16, d16874; SOFT-NEXT: vrev64.16 d16, d16875; SOFT-NEXT: vmov r1, r0, d16876; SOFT-NEXT: bx lr877;878; HARD-LABEL: test_v4i16_v8i8:879; HARD: @ %bb.0:880; HARD-NEXT: vrev64.8 d16, d0881; HARD-NEXT: vadd.i8 d16, d16, d16882; HARD-NEXT: vrev16.8 d16, d16883; HARD-NEXT: vadd.i16 d16, d16, d16884; HARD-NEXT: vrev64.16 d0, d16885; HARD-NEXT: bx lr886 %1 = add <8 x i8> %p, %p887 %2 = bitcast <8 x i8> %1 to <4 x i16>888 %3 = add <4 x i16> %2, %2889 ret <4 x i16> %3890}891 892define <8 x i8> @test_v8i8_i64(i64 %p) {893; SOFT-LABEL: test_v8i8_i64:894; SOFT: @ %bb.0:895; SOFT-NEXT: adds r1, r1, r1896; SOFT-NEXT: adc r0, r0, r0897; SOFT-NEXT: vmov d16, r1, r0898; SOFT-NEXT: vrev64.8 d16, d16899; SOFT-NEXT: vadd.i8 d16, d16, d16900; SOFT-NEXT: vrev64.8 d16, d16901; SOFT-NEXT: vmov r1, r0, d16902; SOFT-NEXT: bx lr903;904; HARD-LABEL: test_v8i8_i64:905; HARD: @ %bb.0:906; HARD-NEXT: adds r1, r1, r1907; HARD-NEXT: adc r0, r0, r0908; HARD-NEXT: vmov d16, r1, r0909; HARD-NEXT: vrev64.8 d16, d16910; HARD-NEXT: vadd.i8 d16, d16, d16911; HARD-NEXT: vrev64.8 d0, d16912; HARD-NEXT: bx lr913 %1 = add i64 %p, %p914 %2 = bitcast i64 %1 to <8 x i8>915 %3 = add <8 x i8> %2, %2916 ret <8 x i8> %3917}918 919define <8 x i8> @test_v8i8_f64(double %p) {920; SOFT-LABEL: test_v8i8_f64:921; SOFT: @ %bb.0:922; SOFT-NEXT: vmov d16, r1, r0923; SOFT-NEXT: vadd.f64 d16, d16, d16924; SOFT-NEXT: vrev64.8 d16, d16925; SOFT-NEXT: vadd.i8 d16, d16, d16926; SOFT-NEXT: vrev64.8 d16, d16927; SOFT-NEXT: vmov r1, r0, d16928; SOFT-NEXT: bx lr929;930; HARD-LABEL: test_v8i8_f64:931; HARD: @ %bb.0:932; HARD-NEXT: vadd.f64 d16, d0, d0933; HARD-NEXT: vrev64.8 d16, d16934; HARD-NEXT: vadd.i8 d16, d16, d16935; HARD-NEXT: vrev64.8 d0, d16936; HARD-NEXT: bx lr937 %1 = fadd double %p, %p938 %2 = bitcast double %1 to <8 x i8>939 %3 = add <8 x i8> %2, %2940 ret <8 x i8> %3941}942 943define <8 x i8> @test_v8i8_v1i64(<1 x i64> %p) {944; SOFT-LABEL: test_v8i8_v1i64:945; SOFT: @ %bb.0:946; SOFT-NEXT: vmov d16, r1, r0947; SOFT-NEXT: vadd.i64 d16, d16, d16948; SOFT-NEXT: vrev64.8 d16, d16949; SOFT-NEXT: vadd.i8 d16, d16, d16950; SOFT-NEXT: vrev64.8 d16, d16951; SOFT-NEXT: vmov r1, r0, d16952; SOFT-NEXT: bx lr953;954; HARD-LABEL: test_v8i8_v1i64:955; HARD: @ %bb.0:956; HARD-NEXT: vadd.i64 d16, d0, d0957; HARD-NEXT: vrev64.8 d16, d16958; HARD-NEXT: vadd.i8 d16, d16, d16959; HARD-NEXT: vrev64.8 d0, d16960; HARD-NEXT: bx lr961 %1 = add <1 x i64> %p, %p962 %2 = bitcast <1 x i64> %1 to <8 x i8>963 %3 = add <8 x i8> %2, %2964 ret <8 x i8> %3965}966 967define <8 x i8> @test_v8i8_v2f32(<2 x float> %p) {968; SOFT-LABEL: test_v8i8_v2f32:969; SOFT: @ %bb.0:970; SOFT-NEXT: vmov d16, r1, r0971; SOFT-NEXT: vrev64.32 d16, d16972; SOFT-NEXT: vadd.f32 d16, d16, d16973; SOFT-NEXT: vrev32.8 d16, d16974; SOFT-NEXT: vadd.i8 d16, d16, d16975; SOFT-NEXT: vrev64.8 d16, d16976; SOFT-NEXT: vmov r1, r0, d16977; SOFT-NEXT: bx lr978;979; HARD-LABEL: test_v8i8_v2f32:980; HARD: @ %bb.0:981; HARD-NEXT: vrev64.32 d16, d0982; HARD-NEXT: vadd.f32 d16, d16, d16983; HARD-NEXT: vrev32.8 d16, d16984; HARD-NEXT: vadd.i8 d16, d16, d16985; HARD-NEXT: vrev64.8 d0, d16986; HARD-NEXT: bx lr987 %1 = fadd <2 x float> %p, %p988 %2 = bitcast <2 x float> %1 to <8 x i8>989 %3 = add <8 x i8> %2, %2990 ret <8 x i8> %3991}992 993define <8 x i8> @test_v8i8_v2i32(<2 x i32> %p) {994; SOFT-LABEL: test_v8i8_v2i32:995; SOFT: @ %bb.0:996; SOFT-NEXT: vmov d16, r1, r0997; SOFT-NEXT: vrev64.32 d16, d16998; SOFT-NEXT: vadd.i32 d16, d16, d16999; SOFT-NEXT: vrev32.8 d16, d161000; SOFT-NEXT: vadd.i8 d16, d16, d161001; SOFT-NEXT: vrev64.8 d16, d161002; SOFT-NEXT: vmov r1, r0, d161003; SOFT-NEXT: bx lr1004;1005; HARD-LABEL: test_v8i8_v2i32:1006; HARD: @ %bb.0:1007; HARD-NEXT: vrev64.32 d16, d01008; HARD-NEXT: vadd.i32 d16, d16, d161009; HARD-NEXT: vrev32.8 d16, d161010; HARD-NEXT: vadd.i8 d16, d16, d161011; HARD-NEXT: vrev64.8 d0, d161012; HARD-NEXT: bx lr1013 %1 = add <2 x i32> %p, %p1014 %2 = bitcast <2 x i32> %1 to <8 x i8>1015 %3 = add <8 x i8> %2, %21016 ret <8 x i8> %31017}1018 1019define <8 x i8> @test_v8i8_v4i16(<4 x i16> %p) {1020; SOFT-LABEL: test_v8i8_v4i16:1021; SOFT: @ %bb.0:1022; SOFT-NEXT: vmov d16, r1, r01023; SOFT-NEXT: vrev64.16 d16, d161024; SOFT-NEXT: vadd.i16 d16, d16, d161025; SOFT-NEXT: vrev16.8 d16, d161026; SOFT-NEXT: vadd.i8 d16, d16, d161027; SOFT-NEXT: vrev64.8 d16, d161028; SOFT-NEXT: vmov r1, r0, d161029; SOFT-NEXT: bx lr1030;1031; HARD-LABEL: test_v8i8_v4i16:1032; HARD: @ %bb.0:1033; HARD-NEXT: vrev64.16 d16, d01034; HARD-NEXT: vadd.i16 d16, d16, d161035; HARD-NEXT: vrev16.8 d16, d161036; HARD-NEXT: vadd.i8 d16, d16, d161037; HARD-NEXT: vrev64.8 d0, d161038; HARD-NEXT: bx lr1039 %1 = add <4 x i16> %p, %p1040 %2 = bitcast <4 x i16> %1 to <8 x i8>1041 %3 = add <8 x i8> %2, %21042 ret <8 x i8> %31043}1044 1045define fp128 @test_f128_v2f64(<2 x double> %p) {1046; SOFT-LABEL: test_f128_v2f64:1047; SOFT: @ %bb.0:1048; SOFT-NEXT: .save {r11, lr}1049; SOFT-NEXT: push {r11, lr}1050; SOFT-NEXT: .pad #161051; SOFT-NEXT: sub sp, sp, #161052; SOFT-NEXT: vmov d16, r3, r21053; SOFT-NEXT: vmov d17, r1, r01054; SOFT-NEXT: vadd.f64 d19, d16, d161055; SOFT-NEXT: vadd.f64 d18, d17, d171056; SOFT-NEXT: vrev64.32 q8, q91057; SOFT-NEXT: vmov r2, r3, d171058; SOFT-NEXT: vmov r0, r1, d161059; SOFT-NEXT: stm sp, {r0, r1, r2, r3}1060; SOFT-NEXT: bl __addtf31061; SOFT-NEXT: add sp, sp, #161062; SOFT-NEXT: pop {r11, pc}1063;1064; HARD-LABEL: test_f128_v2f64:1065; HARD: @ %bb.0:1066; HARD-NEXT: .save {r11, lr}1067; HARD-NEXT: push {r11, lr}1068; HARD-NEXT: .pad #161069; HARD-NEXT: sub sp, sp, #161070; HARD-NEXT: vadd.f64 d17, d1, d11071; HARD-NEXT: vadd.f64 d16, d0, d01072; HARD-NEXT: vrev64.32 q8, q81073; HARD-NEXT: vmov r2, r3, d171074; HARD-NEXT: vmov r0, r1, d161075; HARD-NEXT: stm sp, {r0, r1, r2, r3}1076; HARD-NEXT: bl __addtf31077; HARD-NEXT: add sp, sp, #161078; HARD-NEXT: pop {r11, pc}1079 %1 = fadd <2 x double> %p, %p1080 %2 = bitcast <2 x double> %1 to fp1281081 %3 = fadd fp128 %2, %21082 ret fp128 %31083}1084 1085define fp128 @test_f128_v2i64(<2 x i64> %p) {1086; SOFT-LABEL: test_f128_v2i64:1087; SOFT: @ %bb.0:1088; SOFT-NEXT: .save {r11, lr}1089; SOFT-NEXT: push {r11, lr}1090; SOFT-NEXT: .pad #161091; SOFT-NEXT: sub sp, sp, #161092; SOFT-NEXT: vmov d17, r3, r21093; SOFT-NEXT: vmov d16, r1, r01094; SOFT-NEXT: vadd.i64 q8, q8, q81095; SOFT-NEXT: vrev64.32 q8, q81096; SOFT-NEXT: vmov r2, r3, d171097; SOFT-NEXT: vmov r0, r1, d161098; SOFT-NEXT: stm sp, {r0, r1, r2, r3}1099; SOFT-NEXT: bl __addtf31100; SOFT-NEXT: add sp, sp, #161101; SOFT-NEXT: pop {r11, pc}1102;1103; HARD-LABEL: test_f128_v2i64:1104; HARD: @ %bb.0:1105; HARD-NEXT: .save {r11, lr}1106; HARD-NEXT: push {r11, lr}1107; HARD-NEXT: .pad #161108; HARD-NEXT: sub sp, sp, #161109; HARD-NEXT: vadd.i64 q8, q0, q01110; HARD-NEXT: vrev64.32 q8, q81111; HARD-NEXT: vmov r2, r3, d171112; HARD-NEXT: vmov r0, r1, d161113; HARD-NEXT: stm sp, {r0, r1, r2, r3}1114; HARD-NEXT: bl __addtf31115; HARD-NEXT: add sp, sp, #161116; HARD-NEXT: pop {r11, pc}1117 %1 = add <2 x i64> %p, %p1118 %2 = bitcast <2 x i64> %1 to fp1281119 %3 = fadd fp128 %2, %21120 ret fp128 %31121}1122 1123define fp128 @test_f128_v4f32(<4 x float> %p) {1124; SOFT-LABEL: test_f128_v4f32:1125; SOFT: @ %bb.0:1126; SOFT-NEXT: .save {r11, lr}1127; SOFT-NEXT: push {r11, lr}1128; SOFT-NEXT: .pad #161129; SOFT-NEXT: sub sp, sp, #161130; SOFT-NEXT: vmov d17, r3, r21131; SOFT-NEXT: vmov d16, r1, r01132; SOFT-NEXT: vrev64.32 q8, q81133; SOFT-NEXT: vadd.f32 q8, q8, q81134; SOFT-NEXT: vmov r2, r3, d171135; SOFT-NEXT: vmov r0, r1, d161136; SOFT-NEXT: stm sp, {r0, r1, r2, r3}1137; SOFT-NEXT: bl __addtf31138; SOFT-NEXT: add sp, sp, #161139; SOFT-NEXT: pop {r11, pc}1140;1141; HARD-LABEL: test_f128_v4f32:1142; HARD: @ %bb.0:1143; HARD-NEXT: .save {r11, lr}1144; HARD-NEXT: push {r11, lr}1145; HARD-NEXT: .pad #161146; HARD-NEXT: sub sp, sp, #161147; HARD-NEXT: vrev64.32 q8, q01148; HARD-NEXT: vadd.f32 q8, q8, q81149; HARD-NEXT: vmov r2, r3, d171150; HARD-NEXT: vmov r0, r1, d161151; HARD-NEXT: stm sp, {r0, r1, r2, r3}1152; HARD-NEXT: bl __addtf31153; HARD-NEXT: add sp, sp, #161154; HARD-NEXT: pop {r11, pc}1155 %1 = fadd <4 x float> %p, %p1156 %2 = bitcast <4 x float> %1 to fp1281157 %3 = fadd fp128 %2, %21158 ret fp128 %31159}1160 1161define fp128 @test_f128_v4i32(<4 x i32> %p) {1162; SOFT-LABEL: test_f128_v4i32:1163; SOFT: @ %bb.0:1164; SOFT-NEXT: .save {r11, lr}1165; SOFT-NEXT: push {r11, lr}1166; SOFT-NEXT: .pad #161167; SOFT-NEXT: sub sp, sp, #161168; SOFT-NEXT: vmov d17, r3, r21169; SOFT-NEXT: vmov d16, r1, r01170; SOFT-NEXT: vrev64.32 q8, q81171; SOFT-NEXT: vadd.i32 q8, q8, q81172; SOFT-NEXT: vmov r2, r3, d171173; SOFT-NEXT: vmov r0, r1, d161174; SOFT-NEXT: stm sp, {r0, r1, r2, r3}1175; SOFT-NEXT: bl __addtf31176; SOFT-NEXT: add sp, sp, #161177; SOFT-NEXT: pop {r11, pc}1178;1179; HARD-LABEL: test_f128_v4i32:1180; HARD: @ %bb.0:1181; HARD-NEXT: .save {r11, lr}1182; HARD-NEXT: push {r11, lr}1183; HARD-NEXT: .pad #161184; HARD-NEXT: sub sp, sp, #161185; HARD-NEXT: vrev64.32 q8, q01186; HARD-NEXT: vadd.i32 q8, q8, q81187; HARD-NEXT: vmov r2, r3, d171188; HARD-NEXT: vmov r0, r1, d161189; HARD-NEXT: stm sp, {r0, r1, r2, r3}1190; HARD-NEXT: bl __addtf31191; HARD-NEXT: add sp, sp, #161192; HARD-NEXT: pop {r11, pc}1193 %1 = add <4 x i32> %p, %p1194 %2 = bitcast <4 x i32> %1 to fp1281195 %3 = fadd fp128 %2, %21196 ret fp128 %31197}1198 1199define fp128 @test_f128_v8i16(<8 x i16> %p) {1200; SOFT-LABEL: test_f128_v8i16:1201; SOFT: @ %bb.0:1202; SOFT-NEXT: .save {r11, lr}1203; SOFT-NEXT: push {r11, lr}1204; SOFT-NEXT: .pad #161205; SOFT-NEXT: sub sp, sp, #161206; SOFT-NEXT: vmov d17, r3, r21207; SOFT-NEXT: vmov d16, r1, r01208; SOFT-NEXT: vrev64.16 q8, q81209; SOFT-NEXT: vadd.i16 q8, q8, q81210; SOFT-NEXT: vrev32.16 q8, q81211; SOFT-NEXT: vmov r2, r3, d171212; SOFT-NEXT: vmov r0, r1, d161213; SOFT-NEXT: stm sp, {r0, r1, r2, r3}1214; SOFT-NEXT: bl __addtf31215; SOFT-NEXT: add sp, sp, #161216; SOFT-NEXT: pop {r11, pc}1217;1218; HARD-LABEL: test_f128_v8i16:1219; HARD: @ %bb.0:1220; HARD-NEXT: .save {r11, lr}1221; HARD-NEXT: push {r11, lr}1222; HARD-NEXT: .pad #161223; HARD-NEXT: sub sp, sp, #161224; HARD-NEXT: vrev64.16 q8, q01225; HARD-NEXT: vadd.i16 q8, q8, q81226; HARD-NEXT: vrev32.16 q8, q81227; HARD-NEXT: vmov r2, r3, d171228; HARD-NEXT: vmov r0, r1, d161229; HARD-NEXT: stm sp, {r0, r1, r2, r3}1230; HARD-NEXT: bl __addtf31231; HARD-NEXT: add sp, sp, #161232; HARD-NEXT: pop {r11, pc}1233 %1 = add <8 x i16> %p, %p1234 %2 = bitcast <8 x i16> %1 to fp1281235 %3 = fadd fp128 %2, %21236 ret fp128 %31237}1238 1239define fp128 @test_f128_v16i8(<16 x i8> %p) {1240; SOFT-LABEL: test_f128_v16i8:1241; SOFT: @ %bb.0:1242; SOFT-NEXT: .save {r11, lr}1243; SOFT-NEXT: push {r11, lr}1244; SOFT-NEXT: .pad #161245; SOFT-NEXT: sub sp, sp, #161246; SOFT-NEXT: vmov d17, r3, r21247; SOFT-NEXT: vmov d16, r1, r01248; SOFT-NEXT: vrev64.8 q8, q81249; SOFT-NEXT: vadd.i8 q8, q8, q81250; SOFT-NEXT: vrev32.8 q8, q81251; SOFT-NEXT: vmov r2, r3, d171252; SOFT-NEXT: vmov r0, r1, d161253; SOFT-NEXT: stm sp, {r0, r1, r2, r3}1254; SOFT-NEXT: bl __addtf31255; SOFT-NEXT: add sp, sp, #161256; SOFT-NEXT: pop {r11, pc}1257;1258; HARD-LABEL: test_f128_v16i8:1259; HARD: @ %bb.0:1260; HARD-NEXT: .save {r11, lr}1261; HARD-NEXT: push {r11, lr}1262; HARD-NEXT: .pad #161263; HARD-NEXT: sub sp, sp, #161264; HARD-NEXT: vrev64.8 q8, q01265; HARD-NEXT: vadd.i8 q8, q8, q81266; HARD-NEXT: vrev32.8 q8, q81267; HARD-NEXT: vmov r2, r3, d171268; HARD-NEXT: vmov r0, r1, d161269; HARD-NEXT: stm sp, {r0, r1, r2, r3}1270; HARD-NEXT: bl __addtf31271; HARD-NEXT: add sp, sp, #161272; HARD-NEXT: pop {r11, pc}1273 %1 = add <16 x i8> %p, %p1274 %2 = bitcast <16 x i8> %1 to fp1281275 %3 = fadd fp128 %2, %21276 ret fp128 %31277}1278 1279define <2 x double> @test_v2f64_f128(fp128 %p) {1280; SOFT-LABEL: test_v2f64_f128:1281; SOFT: @ %bb.0:1282; SOFT-NEXT: .save {r11, lr}1283; SOFT-NEXT: push {r11, lr}1284; SOFT-NEXT: .pad #161285; SOFT-NEXT: sub sp, sp, #161286; SOFT-NEXT: stm sp, {r0, r1, r2, r3}1287; SOFT-NEXT: bl __addtf31288; SOFT-NEXT: vmov.32 d17[0], r21289; SOFT-NEXT: vmov.32 d16[0], r01290; SOFT-NEXT: vmov.32 d17[1], r31291; SOFT-NEXT: vmov.32 d16[1], r11292; SOFT-NEXT: vrev64.32 q8, q81293; SOFT-NEXT: vadd.f64 d18, d16, d161294; SOFT-NEXT: vadd.f64 d16, d17, d171295; SOFT-NEXT: vmov r1, r0, d181296; SOFT-NEXT: vmov r3, r2, d161297; SOFT-NEXT: add sp, sp, #161298; SOFT-NEXT: pop {r11, pc}1299;1300; HARD-LABEL: test_v2f64_f128:1301; HARD: @ %bb.0:1302; HARD-NEXT: .save {r11, lr}1303; HARD-NEXT: push {r11, lr}1304; HARD-NEXT: .pad #161305; HARD-NEXT: sub sp, sp, #161306; HARD-NEXT: stm sp, {r0, r1, r2, r3}1307; HARD-NEXT: bl __addtf31308; HARD-NEXT: vmov.32 d17[0], r21309; HARD-NEXT: vmov.32 d16[0], r01310; HARD-NEXT: vmov.32 d17[1], r31311; HARD-NEXT: vmov.32 d16[1], r11312; HARD-NEXT: vrev64.32 q8, q81313; HARD-NEXT: vadd.f64 d1, d17, d171314; HARD-NEXT: vadd.f64 d0, d16, d161315; HARD-NEXT: add sp, sp, #161316; HARD-NEXT: pop {r11, pc}1317 %1 = fadd fp128 %p, %p1318 %2 = bitcast fp128 %1 to <2 x double>1319 %3 = fadd <2 x double> %2, %21320 ret <2 x double> %31321}1322 1323define <2 x double> @test_v2f64_v2i64(<2 x i64> %p) {1324; SOFT-LABEL: test_v2f64_v2i64:1325; SOFT: @ %bb.0:1326; SOFT-NEXT: vmov d17, r3, r21327; SOFT-NEXT: vmov d16, r1, r01328; SOFT-NEXT: vadd.i64 q8, q8, q81329; SOFT-NEXT: vadd.f64 d18, d16, d161330; SOFT-NEXT: vadd.f64 d16, d17, d171331; SOFT-NEXT: vmov r1, r0, d181332; SOFT-NEXT: vmov r3, r2, d161333; SOFT-NEXT: bx lr1334;1335; HARD-LABEL: test_v2f64_v2i64:1336; HARD: @ %bb.0:1337; HARD-NEXT: vadd.i64 q8, q0, q01338; HARD-NEXT: vadd.f64 d1, d17, d171339; HARD-NEXT: vadd.f64 d0, d16, d161340; HARD-NEXT: bx lr1341 %1 = add <2 x i64> %p, %p1342 %2 = bitcast <2 x i64> %1 to <2 x double>1343 %3 = fadd <2 x double> %2, %21344 ret <2 x double> %31345}1346 1347define <2 x double> @test_v2f64_v4f32(<4 x float> %p) {1348; SOFT-LABEL: test_v2f64_v4f32:1349; SOFT: @ %bb.0:1350; SOFT-NEXT: vmov d17, r3, r21351; SOFT-NEXT: vmov d16, r1, r01352; SOFT-NEXT: vrev64.32 q8, q81353; SOFT-NEXT: vadd.f32 q8, q8, q81354; SOFT-NEXT: vrev64.32 q8, q81355; SOFT-NEXT: vadd.f64 d18, d16, d161356; SOFT-NEXT: vadd.f64 d16, d17, d171357; SOFT-NEXT: vmov r1, r0, d181358; SOFT-NEXT: vmov r3, r2, d161359; SOFT-NEXT: bx lr1360;1361; HARD-LABEL: test_v2f64_v4f32:1362; HARD: @ %bb.0:1363; HARD-NEXT: vrev64.32 q8, q01364; HARD-NEXT: vadd.f32 q8, q8, q81365; HARD-NEXT: vrev64.32 q8, q81366; HARD-NEXT: vadd.f64 d1, d17, d171367; HARD-NEXT: vadd.f64 d0, d16, d161368; HARD-NEXT: bx lr1369 %1 = fadd <4 x float> %p, %p1370 %2 = bitcast <4 x float> %1 to <2 x double>1371 %3 = fadd <2 x double> %2, %21372 ret <2 x double> %31373}1374 1375define <2 x double> @test_v2f64_v4i32(<4 x i32> %p) {1376; SOFT-LABEL: test_v2f64_v4i32:1377; SOFT: @ %bb.0:1378; SOFT-NEXT: vmov d17, r3, r21379; SOFT-NEXT: vmov d16, r1, r01380; SOFT-NEXT: vrev64.32 q8, q81381; SOFT-NEXT: vadd.i32 q8, q8, q81382; SOFT-NEXT: vrev64.32 q8, q81383; SOFT-NEXT: vadd.f64 d18, d16, d161384; SOFT-NEXT: vadd.f64 d16, d17, d171385; SOFT-NEXT: vmov r1, r0, d181386; SOFT-NEXT: vmov r3, r2, d161387; SOFT-NEXT: bx lr1388;1389; HARD-LABEL: test_v2f64_v4i32:1390; HARD: @ %bb.0:1391; HARD-NEXT: vrev64.32 q8, q01392; HARD-NEXT: vadd.i32 q8, q8, q81393; HARD-NEXT: vrev64.32 q8, q81394; HARD-NEXT: vadd.f64 d1, d17, d171395; HARD-NEXT: vadd.f64 d0, d16, d161396; HARD-NEXT: bx lr1397 %1 = add <4 x i32> %p, %p1398 %2 = bitcast <4 x i32> %1 to <2 x double>1399 %3 = fadd <2 x double> %2, %21400 ret <2 x double> %31401}1402 1403define <2 x double> @test_v2f64_v8i16(<8 x i16> %p) {1404; SOFT-LABEL: test_v2f64_v8i16:1405; SOFT: @ %bb.0:1406; SOFT-NEXT: vmov d17, r3, r21407; SOFT-NEXT: vmov d16, r1, r01408; SOFT-NEXT: vrev64.16 q8, q81409; SOFT-NEXT: vadd.i16 q8, q8, q81410; SOFT-NEXT: vrev64.16 q8, q81411; SOFT-NEXT: vadd.f64 d18, d16, d161412; SOFT-NEXT: vadd.f64 d16, d17, d171413; SOFT-NEXT: vmov r1, r0, d181414; SOFT-NEXT: vmov r3, r2, d161415; SOFT-NEXT: bx lr1416;1417; HARD-LABEL: test_v2f64_v8i16:1418; HARD: @ %bb.0:1419; HARD-NEXT: vrev64.16 q8, q01420; HARD-NEXT: vadd.i16 q8, q8, q81421; HARD-NEXT: vrev64.16 q8, q81422; HARD-NEXT: vadd.f64 d1, d17, d171423; HARD-NEXT: vadd.f64 d0, d16, d161424; HARD-NEXT: bx lr1425 %1 = add <8 x i16> %p, %p1426 %2 = bitcast <8 x i16> %1 to <2 x double>1427 %3 = fadd <2 x double> %2, %21428 ret <2 x double> %31429}1430 1431define <2 x double> @test_v2f64_v16i8(<16 x i8> %p) {1432; SOFT-LABEL: test_v2f64_v16i8:1433; SOFT: @ %bb.0:1434; SOFT-NEXT: vmov d17, r3, r21435; SOFT-NEXT: vmov d16, r1, r01436; SOFT-NEXT: vrev64.8 q8, q81437; SOFT-NEXT: vadd.i8 q8, q8, q81438; SOFT-NEXT: vrev64.8 q8, q81439; SOFT-NEXT: vadd.f64 d18, d16, d161440; SOFT-NEXT: vadd.f64 d16, d17, d171441; SOFT-NEXT: vmov r1, r0, d181442; SOFT-NEXT: vmov r3, r2, d161443; SOFT-NEXT: bx lr1444;1445; HARD-LABEL: test_v2f64_v16i8:1446; HARD: @ %bb.0:1447; HARD-NEXT: vrev64.8 q8, q01448; HARD-NEXT: vadd.i8 q8, q8, q81449; HARD-NEXT: vrev64.8 q8, q81450; HARD-NEXT: vadd.f64 d1, d17, d171451; HARD-NEXT: vadd.f64 d0, d16, d161452; HARD-NEXT: bx lr1453 %1 = add <16 x i8> %p, %p1454 %2 = bitcast <16 x i8> %1 to <2 x double>1455 %3 = fadd <2 x double> %2, %21456 ret <2 x double> %31457}1458 1459define <2 x i64> @test_v2i64_f128(fp128 %p) {1460; SOFT-LABEL: test_v2i64_f128:1461; SOFT: @ %bb.0:1462; SOFT-NEXT: .save {r11, lr}1463; SOFT-NEXT: push {r11, lr}1464; SOFT-NEXT: .pad #161465; SOFT-NEXT: sub sp, sp, #161466; SOFT-NEXT: stm sp, {r0, r1, r2, r3}1467; SOFT-NEXT: bl __addtf31468; SOFT-NEXT: vmov.32 d17[0], r21469; SOFT-NEXT: vmov.32 d16[0], r01470; SOFT-NEXT: vmov.32 d17[1], r31471; SOFT-NEXT: vmov.32 d16[1], r11472; SOFT-NEXT: vrev64.32 q8, q81473; SOFT-NEXT: vadd.i64 q8, q8, q81474; SOFT-NEXT: vmov r1, r0, d161475; SOFT-NEXT: vmov r3, r2, d171476; SOFT-NEXT: add sp, sp, #161477; SOFT-NEXT: pop {r11, pc}1478;1479; HARD-LABEL: test_v2i64_f128:1480; HARD: @ %bb.0:1481; HARD-NEXT: .save {r11, lr}1482; HARD-NEXT: push {r11, lr}1483; HARD-NEXT: .pad #161484; HARD-NEXT: sub sp, sp, #161485; HARD-NEXT: stm sp, {r0, r1, r2, r3}1486; HARD-NEXT: bl __addtf31487; HARD-NEXT: vmov.32 d17[0], r21488; HARD-NEXT: vmov.32 d16[0], r01489; HARD-NEXT: vmov.32 d17[1], r31490; HARD-NEXT: vmov.32 d16[1], r11491; HARD-NEXT: vrev64.32 q8, q81492; HARD-NEXT: vadd.i64 q0, q8, q81493; HARD-NEXT: add sp, sp, #161494; HARD-NEXT: pop {r11, pc}1495 %1 = fadd fp128 %p, %p1496 %2 = bitcast fp128 %1 to <2 x i64>1497 %3 = add <2 x i64> %2, %21498 ret <2 x i64> %31499}1500 1501define <2 x i64> @test_v2i64_v2f64(<2 x double> %p) {1502; SOFT-LABEL: test_v2i64_v2f64:1503; SOFT: @ %bb.0:1504; SOFT-NEXT: vmov d16, r3, r21505; SOFT-NEXT: vmov d17, r1, r01506; SOFT-NEXT: vadd.f64 d19, d16, d161507; SOFT-NEXT: vadd.f64 d18, d17, d171508; SOFT-NEXT: vadd.i64 q8, q9, q91509; SOFT-NEXT: vmov r1, r0, d161510; SOFT-NEXT: vmov r3, r2, d171511; SOFT-NEXT: bx lr1512;1513; HARD-LABEL: test_v2i64_v2f64:1514; HARD: @ %bb.0:1515; HARD-NEXT: vadd.f64 d17, d1, d11516; HARD-NEXT: vadd.f64 d16, d0, d01517; HARD-NEXT: vadd.i64 q0, q8, q81518; HARD-NEXT: bx lr1519 %1 = fadd <2 x double> %p, %p1520 %2 = bitcast <2 x double> %1 to <2 x i64>1521 %3 = add <2 x i64> %2, %21522 ret <2 x i64> %31523}1524 1525define <2 x i64> @test_v2i64_v4f32(<4 x float> %p) {1526; SOFT-LABEL: test_v2i64_v4f32:1527; SOFT: @ %bb.0:1528; SOFT-NEXT: vmov d17, r3, r21529; SOFT-NEXT: vmov d16, r1, r01530; SOFT-NEXT: vrev64.32 q8, q81531; SOFT-NEXT: vadd.f32 q8, q8, q81532; SOFT-NEXT: vrev64.32 q8, q81533; SOFT-NEXT: vadd.i64 q8, q8, q81534; SOFT-NEXT: vmov r1, r0, d161535; SOFT-NEXT: vmov r3, r2, d171536; SOFT-NEXT: bx lr1537;1538; HARD-LABEL: test_v2i64_v4f32:1539; HARD: @ %bb.0:1540; HARD-NEXT: vrev64.32 q8, q01541; HARD-NEXT: vadd.f32 q8, q8, q81542; HARD-NEXT: vrev64.32 q8, q81543; HARD-NEXT: vadd.i64 q0, q8, q81544; HARD-NEXT: bx lr1545 %1 = fadd <4 x float> %p, %p1546 %2 = bitcast <4 x float> %1 to <2 x i64>1547 %3 = add <2 x i64> %2, %21548 ret <2 x i64> %31549}1550 1551define <2 x i64> @test_v2i64_v4i32(<4 x i32> %p) {1552; SOFT-LABEL: test_v2i64_v4i32:1553; SOFT: @ %bb.0:1554; SOFT-NEXT: vmov d17, r3, r21555; SOFT-NEXT: vmov d16, r1, r01556; SOFT-NEXT: vrev64.32 q8, q81557; SOFT-NEXT: vadd.i32 q8, q8, q81558; SOFT-NEXT: vrev64.32 q8, q81559; SOFT-NEXT: vadd.i64 q8, q8, q81560; SOFT-NEXT: vmov r1, r0, d161561; SOFT-NEXT: vmov r3, r2, d171562; SOFT-NEXT: bx lr1563;1564; HARD-LABEL: test_v2i64_v4i32:1565; HARD: @ %bb.0:1566; HARD-NEXT: vrev64.32 q8, q01567; HARD-NEXT: vadd.i32 q8, q8, q81568; HARD-NEXT: vrev64.32 q8, q81569; HARD-NEXT: vadd.i64 q0, q8, q81570; HARD-NEXT: bx lr1571 %1 = add <4 x i32> %p, %p1572 %2 = bitcast <4 x i32> %1 to <2 x i64>1573 %3 = add <2 x i64> %2, %21574 ret <2 x i64> %31575}1576 1577define <2 x i64> @test_v2i64_v8i16(<8 x i16> %p) {1578; SOFT-LABEL: test_v2i64_v8i16:1579; SOFT: @ %bb.0:1580; SOFT-NEXT: vmov d17, r3, r21581; SOFT-NEXT: vmov d16, r1, r01582; SOFT-NEXT: vrev64.16 q8, q81583; SOFT-NEXT: vadd.i16 q8, q8, q81584; SOFT-NEXT: vrev64.16 q8, q81585; SOFT-NEXT: vadd.i64 q8, q8, q81586; SOFT-NEXT: vmov r1, r0, d161587; SOFT-NEXT: vmov r3, r2, d171588; SOFT-NEXT: bx lr1589;1590; HARD-LABEL: test_v2i64_v8i16:1591; HARD: @ %bb.0:1592; HARD-NEXT: vrev64.16 q8, q01593; HARD-NEXT: vadd.i16 q8, q8, q81594; HARD-NEXT: vrev64.16 q8, q81595; HARD-NEXT: vadd.i64 q0, q8, q81596; HARD-NEXT: bx lr1597 %1 = add <8 x i16> %p, %p1598 %2 = bitcast <8 x i16> %1 to <2 x i64>1599 %3 = add <2 x i64> %2, %21600 ret <2 x i64> %31601}1602 1603define <2 x i64> @test_v2i64_v16i8(<16 x i8> %p) {1604; SOFT-LABEL: test_v2i64_v16i8:1605; SOFT: @ %bb.0:1606; SOFT-NEXT: vmov d17, r3, r21607; SOFT-NEXT: vmov d16, r1, r01608; SOFT-NEXT: vrev64.8 q8, q81609; SOFT-NEXT: vadd.i8 q8, q8, q81610; SOFT-NEXT: vrev64.8 q8, q81611; SOFT-NEXT: vadd.i64 q8, q8, q81612; SOFT-NEXT: vmov r1, r0, d161613; SOFT-NEXT: vmov r3, r2, d171614; SOFT-NEXT: bx lr1615;1616; HARD-LABEL: test_v2i64_v16i8:1617; HARD: @ %bb.0:1618; HARD-NEXT: vrev64.8 q8, q01619; HARD-NEXT: vadd.i8 q8, q8, q81620; HARD-NEXT: vrev64.8 q8, q81621; HARD-NEXT: vadd.i64 q0, q8, q81622; HARD-NEXT: bx lr1623 %1 = add <16 x i8> %p, %p1624 %2 = bitcast <16 x i8> %1 to <2 x i64>1625 %3 = add <2 x i64> %2, %21626 ret <2 x i64> %31627}1628 1629define <4 x float> @test_v4f32_f128(fp128 %p) {1630; SOFT-LABEL: test_v4f32_f128:1631; SOFT: @ %bb.0:1632; SOFT-NEXT: .save {r11, lr}1633; SOFT-NEXT: push {r11, lr}1634; SOFT-NEXT: .pad #161635; SOFT-NEXT: sub sp, sp, #161636; SOFT-NEXT: stm sp, {r0, r1, r2, r3}1637; SOFT-NEXT: bl __addtf31638; SOFT-NEXT: vmov.32 d17[0], r21639; SOFT-NEXT: vmov.32 d16[0], r01640; SOFT-NEXT: vmov.32 d17[1], r31641; SOFT-NEXT: vmov.32 d16[1], r11642; SOFT-NEXT: vadd.f32 q8, q8, q81643; SOFT-NEXT: vrev64.32 q8, q81644; SOFT-NEXT: vmov r1, r0, d161645; SOFT-NEXT: vmov r3, r2, d171646; SOFT-NEXT: add sp, sp, #161647; SOFT-NEXT: pop {r11, pc}1648;1649; HARD-LABEL: test_v4f32_f128:1650; HARD: @ %bb.0:1651; HARD-NEXT: .save {r11, lr}1652; HARD-NEXT: push {r11, lr}1653; HARD-NEXT: .pad #161654; HARD-NEXT: sub sp, sp, #161655; HARD-NEXT: stm sp, {r0, r1, r2, r3}1656; HARD-NEXT: bl __addtf31657; HARD-NEXT: vmov.32 d17[0], r21658; HARD-NEXT: vmov.32 d16[0], r01659; HARD-NEXT: vmov.32 d17[1], r31660; HARD-NEXT: vmov.32 d16[1], r11661; HARD-NEXT: vadd.f32 q8, q8, q81662; HARD-NEXT: vrev64.32 q0, q81663; HARD-NEXT: add sp, sp, #161664; HARD-NEXT: pop {r11, pc}1665 %1 = fadd fp128 %p, %p1666 %2 = bitcast fp128 %1 to <4 x float>1667 %3 = fadd <4 x float> %2, %21668 ret <4 x float> %31669}1670 1671define <4 x float> @test_v4f32_v2f64(<2 x double> %p) {1672; SOFT-LABEL: test_v4f32_v2f64:1673; SOFT: @ %bb.0:1674; SOFT-NEXT: vmov d16, r3, r21675; SOFT-NEXT: vmov d17, r1, r01676; SOFT-NEXT: vadd.f64 d19, d16, d161677; SOFT-NEXT: vadd.f64 d18, d17, d171678; SOFT-NEXT: vrev64.32 q8, q91679; SOFT-NEXT: vadd.f32 q8, q8, q81680; SOFT-NEXT: vrev64.32 q8, q81681; SOFT-NEXT: vmov r1, r0, d161682; SOFT-NEXT: vmov r3, r2, d171683; SOFT-NEXT: bx lr1684;1685; HARD-LABEL: test_v4f32_v2f64:1686; HARD: @ %bb.0:1687; HARD-NEXT: vadd.f64 d17, d1, d11688; HARD-NEXT: vadd.f64 d16, d0, d01689; HARD-NEXT: vrev64.32 q8, q81690; HARD-NEXT: vadd.f32 q8, q8, q81691; HARD-NEXT: vrev64.32 q0, q81692; HARD-NEXT: bx lr1693 %1 = fadd <2 x double> %p, %p1694 %2 = bitcast <2 x double> %1 to <4 x float>1695 %3 = fadd <4 x float> %2, %21696 ret <4 x float> %31697}1698 1699define <4 x float> @test_v4f32_v2i64(<2 x i64> %p) {1700; SOFT-LABEL: test_v4f32_v2i64:1701; SOFT: @ %bb.0:1702; SOFT-NEXT: vmov d17, r3, r21703; SOFT-NEXT: vmov d16, r1, r01704; SOFT-NEXT: vadd.i64 q8, q8, q81705; SOFT-NEXT: vrev64.32 q8, q81706; SOFT-NEXT: vadd.f32 q8, q8, q81707; SOFT-NEXT: vrev64.32 q8, q81708; SOFT-NEXT: vmov r1, r0, d161709; SOFT-NEXT: vmov r3, r2, d171710; SOFT-NEXT: bx lr1711;1712; HARD-LABEL: test_v4f32_v2i64:1713; HARD: @ %bb.0:1714; HARD-NEXT: vadd.i64 q8, q0, q01715; HARD-NEXT: vrev64.32 q8, q81716; HARD-NEXT: vadd.f32 q8, q8, q81717; HARD-NEXT: vrev64.32 q0, q81718; HARD-NEXT: bx lr1719 %1 = add <2 x i64> %p, %p1720 %2 = bitcast <2 x i64> %1 to <4 x float>1721 %3 = fadd <4 x float> %2, %21722 ret <4 x float> %31723}1724 1725define <4 x float> @test_v4f32_v4i32(<4 x i32> %p) {1726; SOFT-LABEL: test_v4f32_v4i32:1727; SOFT: @ %bb.0:1728; SOFT-NEXT: vmov d17, r3, r21729; SOFT-NEXT: vmov d16, r1, r01730; SOFT-NEXT: vrev64.32 q8, q81731; SOFT-NEXT: vadd.i32 q8, q8, q81732; SOFT-NEXT: vadd.f32 q8, q8, q81733; SOFT-NEXT: vrev64.32 q8, q81734; SOFT-NEXT: vmov r1, r0, d161735; SOFT-NEXT: vmov r3, r2, d171736; SOFT-NEXT: bx lr1737;1738; HARD-LABEL: test_v4f32_v4i32:1739; HARD: @ %bb.0:1740; HARD-NEXT: vrev64.32 q8, q01741; HARD-NEXT: vadd.i32 q8, q8, q81742; HARD-NEXT: vadd.f32 q8, q8, q81743; HARD-NEXT: vrev64.32 q0, q81744; HARD-NEXT: bx lr1745 %1 = add <4 x i32> %p, %p1746 %2 = bitcast <4 x i32> %1 to <4 x float>1747 %3 = fadd <4 x float> %2, %21748 ret <4 x float> %31749}1750 1751define <4 x float> @test_v4f32_v8i16(<8 x i16> %p) {1752; SOFT-LABEL: test_v4f32_v8i16:1753; SOFT: @ %bb.0:1754; SOFT-NEXT: vmov d17, r3, r21755; SOFT-NEXT: vmov d16, r1, r01756; SOFT-NEXT: vrev64.16 q8, q81757; SOFT-NEXT: vadd.i16 q8, q8, q81758; SOFT-NEXT: vrev32.16 q8, q81759; SOFT-NEXT: vadd.f32 q8, q8, q81760; SOFT-NEXT: vrev64.32 q8, q81761; SOFT-NEXT: vmov r1, r0, d161762; SOFT-NEXT: vmov r3, r2, d171763; SOFT-NEXT: bx lr1764;1765; HARD-LABEL: test_v4f32_v8i16:1766; HARD: @ %bb.0:1767; HARD-NEXT: vrev64.16 q8, q01768; HARD-NEXT: vadd.i16 q8, q8, q81769; HARD-NEXT: vrev32.16 q8, q81770; HARD-NEXT: vadd.f32 q8, q8, q81771; HARD-NEXT: vrev64.32 q0, q81772; HARD-NEXT: bx lr1773 %1 = add <8 x i16> %p, %p1774 %2 = bitcast <8 x i16> %1 to <4 x float>1775 %3 = fadd <4 x float> %2, %21776 ret <4 x float> %31777}1778 1779define <4 x float> @test_v4f32_v16i8(<16 x i8> %p) {1780; SOFT-LABEL: test_v4f32_v16i8:1781; SOFT: @ %bb.0:1782; SOFT-NEXT: vmov d17, r3, r21783; SOFT-NEXT: vmov d16, r1, r01784; SOFT-NEXT: vrev64.8 q8, q81785; SOFT-NEXT: vadd.i8 q8, q8, q81786; SOFT-NEXT: vrev32.8 q8, q81787; SOFT-NEXT: vadd.f32 q8, q8, q81788; SOFT-NEXT: vrev64.32 q8, q81789; SOFT-NEXT: vmov r1, r0, d161790; SOFT-NEXT: vmov r3, r2, d171791; SOFT-NEXT: bx lr1792;1793; HARD-LABEL: test_v4f32_v16i8:1794; HARD: @ %bb.0:1795; HARD-NEXT: vrev64.8 q8, q01796; HARD-NEXT: vadd.i8 q8, q8, q81797; HARD-NEXT: vrev32.8 q8, q81798; HARD-NEXT: vadd.f32 q8, q8, q81799; HARD-NEXT: vrev64.32 q0, q81800; HARD-NEXT: bx lr1801 %1 = add <16 x i8> %p, %p1802 %2 = bitcast <16 x i8> %1 to <4 x float>1803 %3 = fadd <4 x float> %2, %21804 ret <4 x float> %31805}1806 1807define <4 x i32> @test_v4i32_f128(fp128 %p) {1808; SOFT-LABEL: test_v4i32_f128:1809; SOFT: @ %bb.0:1810; SOFT-NEXT: .save {r11, lr}1811; SOFT-NEXT: push {r11, lr}1812; SOFT-NEXT: .pad #161813; SOFT-NEXT: sub sp, sp, #161814; SOFT-NEXT: stm sp, {r0, r1, r2, r3}1815; SOFT-NEXT: bl __addtf31816; SOFT-NEXT: vmov.32 d17[0], r21817; SOFT-NEXT: vmov.32 d16[0], r01818; SOFT-NEXT: vmov.32 d17[1], r31819; SOFT-NEXT: vmov.32 d16[1], r11820; SOFT-NEXT: vadd.i32 q8, q8, q81821; SOFT-NEXT: vrev64.32 q8, q81822; SOFT-NEXT: vmov r1, r0, d161823; SOFT-NEXT: vmov r3, r2, d171824; SOFT-NEXT: add sp, sp, #161825; SOFT-NEXT: pop {r11, pc}1826;1827; HARD-LABEL: test_v4i32_f128:1828; HARD: @ %bb.0:1829; HARD-NEXT: .save {r11, lr}1830; HARD-NEXT: push {r11, lr}1831; HARD-NEXT: .pad #161832; HARD-NEXT: sub sp, sp, #161833; HARD-NEXT: stm sp, {r0, r1, r2, r3}1834; HARD-NEXT: bl __addtf31835; HARD-NEXT: vmov.32 d17[0], r21836; HARD-NEXT: vmov.32 d16[0], r01837; HARD-NEXT: vmov.32 d17[1], r31838; HARD-NEXT: vmov.32 d16[1], r11839; HARD-NEXT: vadd.i32 q8, q8, q81840; HARD-NEXT: vrev64.32 q0, q81841; HARD-NEXT: add sp, sp, #161842; HARD-NEXT: pop {r11, pc}1843 %1 = fadd fp128 %p, %p1844 %2 = bitcast fp128 %1 to <4 x i32>1845 %3 = add <4 x i32> %2, %21846 ret <4 x i32> %31847}1848 1849define <4 x i32> @test_v4i32_v2f64(<2 x double> %p) {1850; SOFT-LABEL: test_v4i32_v2f64:1851; SOFT: @ %bb.0:1852; SOFT-NEXT: vmov d16, r3, r21853; SOFT-NEXT: vmov d17, r1, r01854; SOFT-NEXT: vadd.f64 d19, d16, d161855; SOFT-NEXT: vadd.f64 d18, d17, d171856; SOFT-NEXT: vrev64.32 q8, q91857; SOFT-NEXT: vadd.i32 q8, q8, q81858; SOFT-NEXT: vrev64.32 q8, q81859; SOFT-NEXT: vmov r1, r0, d161860; SOFT-NEXT: vmov r3, r2, d171861; SOFT-NEXT: bx lr1862;1863; HARD-LABEL: test_v4i32_v2f64:1864; HARD: @ %bb.0:1865; HARD-NEXT: vadd.f64 d17, d1, d11866; HARD-NEXT: vadd.f64 d16, d0, d01867; HARD-NEXT: vrev64.32 q8, q81868; HARD-NEXT: vadd.i32 q8, q8, q81869; HARD-NEXT: vrev64.32 q0, q81870; HARD-NEXT: bx lr1871 %1 = fadd <2 x double> %p, %p1872 %2 = bitcast <2 x double> %1 to <4 x i32>1873 %3 = add <4 x i32> %2, %21874 ret <4 x i32> %31875}1876 1877define <4 x i32> @test_v4i32_v2i64(<2 x i64> %p) {1878; SOFT-LABEL: test_v4i32_v2i64:1879; SOFT: @ %bb.0:1880; SOFT-NEXT: vmov d17, r3, r21881; SOFT-NEXT: vmov d16, r1, r01882; SOFT-NEXT: vadd.i64 q8, q8, q81883; SOFT-NEXT: vrev64.32 q8, q81884; SOFT-NEXT: vadd.i32 q8, q8, q81885; SOFT-NEXT: vrev64.32 q8, q81886; SOFT-NEXT: vmov r1, r0, d161887; SOFT-NEXT: vmov r3, r2, d171888; SOFT-NEXT: bx lr1889;1890; HARD-LABEL: test_v4i32_v2i64:1891; HARD: @ %bb.0:1892; HARD-NEXT: vadd.i64 q8, q0, q01893; HARD-NEXT: vrev64.32 q8, q81894; HARD-NEXT: vadd.i32 q8, q8, q81895; HARD-NEXT: vrev64.32 q0, q81896; HARD-NEXT: bx lr1897 %1 = add <2 x i64> %p, %p1898 %2 = bitcast <2 x i64> %1 to <4 x i32>1899 %3 = add <4 x i32> %2, %21900 ret <4 x i32> %31901}1902 1903define <4 x i32> @test_v4i32_v4f32(<4 x float> %p) {1904; SOFT-LABEL: test_v4i32_v4f32:1905; SOFT: @ %bb.0:1906; SOFT-NEXT: vmov d17, r3, r21907; SOFT-NEXT: vmov d16, r1, r01908; SOFT-NEXT: vrev64.32 q8, q81909; SOFT-NEXT: vadd.f32 q8, q8, q81910; SOFT-NEXT: vadd.i32 q8, q8, q81911; SOFT-NEXT: vrev64.32 q8, q81912; SOFT-NEXT: vmov r1, r0, d161913; SOFT-NEXT: vmov r3, r2, d171914; SOFT-NEXT: bx lr1915;1916; HARD-LABEL: test_v4i32_v4f32:1917; HARD: @ %bb.0:1918; HARD-NEXT: vrev64.32 q8, q01919; HARD-NEXT: vadd.f32 q8, q8, q81920; HARD-NEXT: vadd.i32 q8, q8, q81921; HARD-NEXT: vrev64.32 q0, q81922; HARD-NEXT: bx lr1923 %1 = fadd <4 x float> %p, %p1924 %2 = bitcast <4 x float> %1 to <4 x i32>1925 %3 = add <4 x i32> %2, %21926 ret <4 x i32> %31927}1928 1929define <4 x i32> @test_v4i32_v8i16(<8 x i16> %p) {1930; SOFT-LABEL: test_v4i32_v8i16:1931; SOFT: @ %bb.0:1932; SOFT-NEXT: vmov d17, r3, r21933; SOFT-NEXT: vmov d16, r1, r01934; SOFT-NEXT: vrev64.16 q8, q81935; SOFT-NEXT: vadd.i16 q8, q8, q81936; SOFT-NEXT: vrev32.16 q8, q81937; SOFT-NEXT: vadd.i32 q8, q8, q81938; SOFT-NEXT: vrev64.32 q8, q81939; SOFT-NEXT: vmov r1, r0, d161940; SOFT-NEXT: vmov r3, r2, d171941; SOFT-NEXT: bx lr1942;1943; HARD-LABEL: test_v4i32_v8i16:1944; HARD: @ %bb.0:1945; HARD-NEXT: vrev64.16 q8, q01946; HARD-NEXT: vadd.i16 q8, q8, q81947; HARD-NEXT: vrev32.16 q8, q81948; HARD-NEXT: vadd.i32 q8, q8, q81949; HARD-NEXT: vrev64.32 q0, q81950; HARD-NEXT: bx lr1951 %1 = add <8 x i16> %p, %p1952 %2 = bitcast <8 x i16> %1 to <4 x i32>1953 %3 = add <4 x i32> %2, %21954 ret <4 x i32> %31955}1956 1957define <4 x i32> @test_v4i32_v16i8(<16 x i8> %p) {1958; SOFT-LABEL: test_v4i32_v16i8:1959; SOFT: @ %bb.0:1960; SOFT-NEXT: vmov d17, r3, r21961; SOFT-NEXT: vmov d16, r1, r01962; SOFT-NEXT: vrev64.8 q8, q81963; SOFT-NEXT: vadd.i8 q8, q8, q81964; SOFT-NEXT: vrev32.8 q8, q81965; SOFT-NEXT: vadd.i32 q8, q8, q81966; SOFT-NEXT: vrev64.32 q8, q81967; SOFT-NEXT: vmov r1, r0, d161968; SOFT-NEXT: vmov r3, r2, d171969; SOFT-NEXT: bx lr1970;1971; HARD-LABEL: test_v4i32_v16i8:1972; HARD: @ %bb.0:1973; HARD-NEXT: vrev64.8 q8, q01974; HARD-NEXT: vadd.i8 q8, q8, q81975; HARD-NEXT: vrev32.8 q8, q81976; HARD-NEXT: vadd.i32 q8, q8, q81977; HARD-NEXT: vrev64.32 q0, q81978; HARD-NEXT: bx lr1979 %1 = add <16 x i8> %p, %p1980 %2 = bitcast <16 x i8> %1 to <4 x i32>1981 %3 = add <4 x i32> %2, %21982 ret <4 x i32> %31983}1984 1985define <8 x i16> @test_v8i16_f128(fp128 %p) {1986; SOFT-LABEL: test_v8i16_f128:1987; SOFT: @ %bb.0:1988; SOFT-NEXT: .save {r11, lr}1989; SOFT-NEXT: push {r11, lr}1990; SOFT-NEXT: .pad #161991; SOFT-NEXT: sub sp, sp, #161992; SOFT-NEXT: stm sp, {r0, r1, r2, r3}1993; SOFT-NEXT: bl __addtf31994; SOFT-NEXT: vmov.32 d17[0], r21995; SOFT-NEXT: vmov.32 d16[0], r01996; SOFT-NEXT: vmov.32 d17[1], r31997; SOFT-NEXT: vmov.32 d16[1], r11998; SOFT-NEXT: vrev32.16 q8, q81999; SOFT-NEXT: vadd.i16 q8, q8, q82000; SOFT-NEXT: vrev64.16 q8, q82001; SOFT-NEXT: vmov r1, r0, d162002; SOFT-NEXT: vmov r3, r2, d172003; SOFT-NEXT: add sp, sp, #162004; SOFT-NEXT: pop {r11, pc}2005;2006; HARD-LABEL: test_v8i16_f128:2007; HARD: @ %bb.0:2008; HARD-NEXT: .save {r11, lr}2009; HARD-NEXT: push {r11, lr}2010; HARD-NEXT: .pad #162011; HARD-NEXT: sub sp, sp, #162012; HARD-NEXT: stm sp, {r0, r1, r2, r3}2013; HARD-NEXT: bl __addtf32014; HARD-NEXT: vmov.32 d17[0], r22015; HARD-NEXT: vmov.32 d16[0], r02016; HARD-NEXT: vmov.32 d17[1], r32017; HARD-NEXT: vmov.32 d16[1], r12018; HARD-NEXT: vrev32.16 q8, q82019; HARD-NEXT: vadd.i16 q8, q8, q82020; HARD-NEXT: vrev64.16 q0, q82021; HARD-NEXT: add sp, sp, #162022; HARD-NEXT: pop {r11, pc}2023 %1 = fadd fp128 %p, %p2024 %2 = bitcast fp128 %1 to <8 x i16>2025 %3 = add <8 x i16> %2, %22026 ret <8 x i16> %32027}2028 2029define <8 x i16> @test_v8i16_v2f64(<2 x double> %p) {2030; SOFT-LABEL: test_v8i16_v2f64:2031; SOFT: @ %bb.0:2032; SOFT-NEXT: vmov d16, r3, r22033; SOFT-NEXT: vmov d17, r1, r02034; SOFT-NEXT: vadd.f64 d19, d16, d162035; SOFT-NEXT: vadd.f64 d18, d17, d172036; SOFT-NEXT: vrev64.16 q8, q92037; SOFT-NEXT: vadd.i16 q8, q8, q82038; SOFT-NEXT: vrev64.16 q8, q82039; SOFT-NEXT: vmov r1, r0, d162040; SOFT-NEXT: vmov r3, r2, d172041; SOFT-NEXT: bx lr2042;2043; HARD-LABEL: test_v8i16_v2f64:2044; HARD: @ %bb.0:2045; HARD-NEXT: vadd.f64 d17, d1, d12046; HARD-NEXT: vadd.f64 d16, d0, d02047; HARD-NEXT: vrev64.16 q8, q82048; HARD-NEXT: vadd.i16 q8, q8, q82049; HARD-NEXT: vrev64.16 q0, q82050; HARD-NEXT: bx lr2051 %1 = fadd <2 x double> %p, %p2052 %2 = bitcast <2 x double> %1 to <8 x i16>2053 %3 = add <8 x i16> %2, %22054 ret <8 x i16> %32055}2056 2057define <8 x i16> @test_v8i16_v2i64(<2 x i64> %p) {2058; SOFT-LABEL: test_v8i16_v2i64:2059; SOFT: @ %bb.0:2060; SOFT-NEXT: vmov d17, r3, r22061; SOFT-NEXT: vmov d16, r1, r02062; SOFT-NEXT: vadd.i64 q8, q8, q82063; SOFT-NEXT: vrev64.16 q8, q82064; SOFT-NEXT: vadd.i16 q8, q8, q82065; SOFT-NEXT: vrev64.16 q8, q82066; SOFT-NEXT: vmov r1, r0, d162067; SOFT-NEXT: vmov r3, r2, d172068; SOFT-NEXT: bx lr2069;2070; HARD-LABEL: test_v8i16_v2i64:2071; HARD: @ %bb.0:2072; HARD-NEXT: vadd.i64 q8, q0, q02073; HARD-NEXT: vrev64.16 q8, q82074; HARD-NEXT: vadd.i16 q8, q8, q82075; HARD-NEXT: vrev64.16 q0, q82076; HARD-NEXT: bx lr2077 %1 = add <2 x i64> %p, %p2078 %2 = bitcast <2 x i64> %1 to <8 x i16>2079 %3 = add <8 x i16> %2, %22080 ret <8 x i16> %32081}2082 2083define <8 x i16> @test_v8i16_v4f32(<4 x float> %p) {2084; SOFT-LABEL: test_v8i16_v4f32:2085; SOFT: @ %bb.0:2086; SOFT-NEXT: vmov d17, r3, r22087; SOFT-NEXT: vmov d16, r1, r02088; SOFT-NEXT: vrev64.32 q8, q82089; SOFT-NEXT: vadd.f32 q8, q8, q82090; SOFT-NEXT: vrev32.16 q8, q82091; SOFT-NEXT: vadd.i16 q8, q8, q82092; SOFT-NEXT: vrev64.16 q8, q82093; SOFT-NEXT: vmov r1, r0, d162094; SOFT-NEXT: vmov r3, r2, d172095; SOFT-NEXT: bx lr2096;2097; HARD-LABEL: test_v8i16_v4f32:2098; HARD: @ %bb.0:2099; HARD-NEXT: vrev64.32 q8, q02100; HARD-NEXT: vadd.f32 q8, q8, q82101; HARD-NEXT: vrev32.16 q8, q82102; HARD-NEXT: vadd.i16 q8, q8, q82103; HARD-NEXT: vrev64.16 q0, q82104; HARD-NEXT: bx lr2105 %1 = fadd <4 x float> %p, %p2106 %2 = bitcast <4 x float> %1 to <8 x i16>2107 %3 = add <8 x i16> %2, %22108 ret <8 x i16> %32109}2110 2111define <8 x i16> @test_v8i16_v4i32(<4 x i32> %p) {2112; SOFT-LABEL: test_v8i16_v4i32:2113; SOFT: @ %bb.0:2114; SOFT-NEXT: vmov d17, r3, r22115; SOFT-NEXT: vmov d16, r1, r02116; SOFT-NEXT: vrev64.32 q8, q82117; SOFT-NEXT: vadd.i32 q8, q8, q82118; SOFT-NEXT: vrev32.16 q8, q82119; SOFT-NEXT: vadd.i16 q8, q8, q82120; SOFT-NEXT: vrev64.16 q8, q82121; SOFT-NEXT: vmov r1, r0, d162122; SOFT-NEXT: vmov r3, r2, d172123; SOFT-NEXT: bx lr2124;2125; HARD-LABEL: test_v8i16_v4i32:2126; HARD: @ %bb.0:2127; HARD-NEXT: vrev64.32 q8, q02128; HARD-NEXT: vadd.i32 q8, q8, q82129; HARD-NEXT: vrev32.16 q8, q82130; HARD-NEXT: vadd.i16 q8, q8, q82131; HARD-NEXT: vrev64.16 q0, q82132; HARD-NEXT: bx lr2133 %1 = add <4 x i32> %p, %p2134 %2 = bitcast <4 x i32> %1 to <8 x i16>2135 %3 = add <8 x i16> %2, %22136 ret <8 x i16> %32137}2138 2139define <8 x i16> @test_v8i16_v16i8(<16 x i8> %p) {2140; SOFT-LABEL: test_v8i16_v16i8:2141; SOFT: @ %bb.0:2142; SOFT-NEXT: vmov d17, r3, r22143; SOFT-NEXT: vmov d16, r1, r02144; SOFT-NEXT: vrev64.8 q8, q82145; SOFT-NEXT: vadd.i8 q8, q8, q82146; SOFT-NEXT: vrev16.8 q8, q82147; SOFT-NEXT: vadd.i16 q8, q8, q82148; SOFT-NEXT: vrev64.16 q8, q82149; SOFT-NEXT: vmov r1, r0, d162150; SOFT-NEXT: vmov r3, r2, d172151; SOFT-NEXT: bx lr2152;2153; HARD-LABEL: test_v8i16_v16i8:2154; HARD: @ %bb.0:2155; HARD-NEXT: vrev64.8 q8, q02156; HARD-NEXT: vadd.i8 q8, q8, q82157; HARD-NEXT: vrev16.8 q8, q82158; HARD-NEXT: vadd.i16 q8, q8, q82159; HARD-NEXT: vrev64.16 q0, q82160; HARD-NEXT: bx lr2161 %1 = add <16 x i8> %p, %p2162 %2 = bitcast <16 x i8> %1 to <8 x i16>2163 %3 = add <8 x i16> %2, %22164 ret <8 x i16> %32165}2166 2167define <16 x i8> @test_v16i8_f128(fp128 %p) {2168; SOFT-LABEL: test_v16i8_f128:2169; SOFT: @ %bb.0:2170; SOFT-NEXT: .save {r11, lr}2171; SOFT-NEXT: push {r11, lr}2172; SOFT-NEXT: .pad #162173; SOFT-NEXT: sub sp, sp, #162174; SOFT-NEXT: stm sp, {r0, r1, r2, r3}2175; SOFT-NEXT: bl __addtf32176; SOFT-NEXT: vmov.32 d17[0], r22177; SOFT-NEXT: vmov.32 d16[0], r02178; SOFT-NEXT: vmov.32 d17[1], r32179; SOFT-NEXT: vmov.32 d16[1], r12180; SOFT-NEXT: vrev32.8 q8, q82181; SOFT-NEXT: vadd.i8 q8, q8, q82182; SOFT-NEXT: vrev64.8 q8, q82183; SOFT-NEXT: vmov r1, r0, d162184; SOFT-NEXT: vmov r3, r2, d172185; SOFT-NEXT: add sp, sp, #162186; SOFT-NEXT: pop {r11, pc}2187;2188; HARD-LABEL: test_v16i8_f128:2189; HARD: @ %bb.0:2190; HARD-NEXT: .save {r11, lr}2191; HARD-NEXT: push {r11, lr}2192; HARD-NEXT: .pad #162193; HARD-NEXT: sub sp, sp, #162194; HARD-NEXT: stm sp, {r0, r1, r2, r3}2195; HARD-NEXT: bl __addtf32196; HARD-NEXT: vmov.32 d17[0], r22197; HARD-NEXT: vmov.32 d16[0], r02198; HARD-NEXT: vmov.32 d17[1], r32199; HARD-NEXT: vmov.32 d16[1], r12200; HARD-NEXT: vrev32.8 q8, q82201; HARD-NEXT: vadd.i8 q8, q8, q82202; HARD-NEXT: vrev64.8 q0, q82203; HARD-NEXT: add sp, sp, #162204; HARD-NEXT: pop {r11, pc}2205 %1 = fadd fp128 %p, %p2206 %2 = bitcast fp128 %1 to <16 x i8>2207 %3 = add <16 x i8> %2, %22208 ret <16 x i8> %32209}2210 2211define <16 x i8> @test_v16i8_v2f64(<2 x double> %p) {2212; SOFT-LABEL: test_v16i8_v2f64:2213; SOFT: @ %bb.0:2214; SOFT-NEXT: vmov d16, r3, r22215; SOFT-NEXT: vmov d17, r1, r02216; SOFT-NEXT: vadd.f64 d19, d16, d162217; SOFT-NEXT: vadd.f64 d18, d17, d172218; SOFT-NEXT: vrev64.8 q8, q92219; SOFT-NEXT: vadd.i8 q8, q8, q82220; SOFT-NEXT: vrev64.8 q8, q82221; SOFT-NEXT: vmov r1, r0, d162222; SOFT-NEXT: vmov r3, r2, d172223; SOFT-NEXT: bx lr2224;2225; HARD-LABEL: test_v16i8_v2f64:2226; HARD: @ %bb.0:2227; HARD-NEXT: vadd.f64 d17, d1, d12228; HARD-NEXT: vadd.f64 d16, d0, d02229; HARD-NEXT: vrev64.8 q8, q82230; HARD-NEXT: vadd.i8 q8, q8, q82231; HARD-NEXT: vrev64.8 q0, q82232; HARD-NEXT: bx lr2233 %1 = fadd <2 x double> %p, %p2234 %2 = bitcast <2 x double> %1 to <16 x i8>2235 %3 = add <16 x i8> %2, %22236 ret <16 x i8> %32237}2238 2239define <16 x i8> @test_v16i8_v2i64(<2 x i64> %p) {2240; SOFT-LABEL: test_v16i8_v2i64:2241; SOFT: @ %bb.0:2242; SOFT-NEXT: vmov d17, r3, r22243; SOFT-NEXT: vmov d16, r1, r02244; SOFT-NEXT: vadd.i64 q8, q8, q82245; SOFT-NEXT: vrev64.8 q8, q82246; SOFT-NEXT: vadd.i8 q8, q8, q82247; SOFT-NEXT: vrev64.8 q8, q82248; SOFT-NEXT: vmov r1, r0, d162249; SOFT-NEXT: vmov r3, r2, d172250; SOFT-NEXT: bx lr2251;2252; HARD-LABEL: test_v16i8_v2i64:2253; HARD: @ %bb.0:2254; HARD-NEXT: vadd.i64 q8, q0, q02255; HARD-NEXT: vrev64.8 q8, q82256; HARD-NEXT: vadd.i8 q8, q8, q82257; HARD-NEXT: vrev64.8 q0, q82258; HARD-NEXT: bx lr2259 %1 = add <2 x i64> %p, %p2260 %2 = bitcast <2 x i64> %1 to <16 x i8>2261 %3 = add <16 x i8> %2, %22262 ret <16 x i8> %32263}2264 2265define <16 x i8> @test_v16i8_v4f32(<4 x float> %p) {2266; SOFT-LABEL: test_v16i8_v4f32:2267; SOFT: @ %bb.0:2268; SOFT-NEXT: vmov d17, r3, r22269; SOFT-NEXT: vmov d16, r1, r02270; SOFT-NEXT: vrev64.32 q8, q82271; SOFT-NEXT: vadd.f32 q8, q8, q82272; SOFT-NEXT: vrev32.8 q8, q82273; SOFT-NEXT: vadd.i8 q8, q8, q82274; SOFT-NEXT: vrev64.8 q8, q82275; SOFT-NEXT: vmov r1, r0, d162276; SOFT-NEXT: vmov r3, r2, d172277; SOFT-NEXT: bx lr2278;2279; HARD-LABEL: test_v16i8_v4f32:2280; HARD: @ %bb.0:2281; HARD-NEXT: vrev64.32 q8, q02282; HARD-NEXT: vadd.f32 q8, q8, q82283; HARD-NEXT: vrev32.8 q8, q82284; HARD-NEXT: vadd.i8 q8, q8, q82285; HARD-NEXT: vrev64.8 q0, q82286; HARD-NEXT: bx lr2287 %1 = fadd <4 x float> %p, %p2288 %2 = bitcast <4 x float> %1 to <16 x i8>2289 %3 = add <16 x i8> %2, %22290 ret <16 x i8> %32291}2292 2293define <16 x i8> @test_v16i8_v4i32(<4 x i32> %p) {2294; SOFT-LABEL: test_v16i8_v4i32:2295; SOFT: @ %bb.0:2296; SOFT-NEXT: vmov d17, r3, r22297; SOFT-NEXT: vmov d16, r1, r02298; SOFT-NEXT: vrev64.32 q8, q82299; SOFT-NEXT: vadd.i32 q8, q8, q82300; SOFT-NEXT: vrev32.8 q8, q82301; SOFT-NEXT: vadd.i8 q8, q8, q82302; SOFT-NEXT: vrev64.8 q8, q82303; SOFT-NEXT: vmov r1, r0, d162304; SOFT-NEXT: vmov r3, r2, d172305; SOFT-NEXT: bx lr2306;2307; HARD-LABEL: test_v16i8_v4i32:2308; HARD: @ %bb.0:2309; HARD-NEXT: vrev64.32 q8, q02310; HARD-NEXT: vadd.i32 q8, q8, q82311; HARD-NEXT: vrev32.8 q8, q82312; HARD-NEXT: vadd.i8 q8, q8, q82313; HARD-NEXT: vrev64.8 q0, q82314; HARD-NEXT: bx lr2315 %1 = add <4 x i32> %p, %p2316 %2 = bitcast <4 x i32> %1 to <16 x i8>2317 %3 = add <16 x i8> %2, %22318 ret <16 x i8> %32319}2320 2321define <16 x i8> @test_v16i8_v8i16(<8 x i16> %p) {2322; SOFT-LABEL: test_v16i8_v8i16:2323; SOFT: @ %bb.0:2324; SOFT-NEXT: vmov d17, r3, r22325; SOFT-NEXT: vmov d16, r1, r02326; SOFT-NEXT: vrev64.16 q8, q82327; SOFT-NEXT: vadd.i16 q8, q8, q82328; SOFT-NEXT: vrev16.8 q8, q82329; SOFT-NEXT: vadd.i8 q8, q8, q82330; SOFT-NEXT: vrev64.8 q8, q82331; SOFT-NEXT: vmov r1, r0, d162332; SOFT-NEXT: vmov r3, r2, d172333; SOFT-NEXT: bx lr2334;2335; HARD-LABEL: test_v16i8_v8i16:2336; HARD: @ %bb.0:2337; HARD-NEXT: vrev64.16 q8, q02338; HARD-NEXT: vadd.i16 q8, q8, q82339; HARD-NEXT: vrev16.8 q8, q82340; HARD-NEXT: vadd.i8 q8, q8, q82341; HARD-NEXT: vrev64.8 q0, q82342; HARD-NEXT: bx lr2343 %1 = add <8 x i16> %p, %p2344 %2 = bitcast <8 x i16> %1 to <16 x i8>2345 %3 = add <16 x i8> %2, %22346 ret <16 x i8> %32347}2348