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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple armeb-eabi -mattr v7,neon -float-abi soft %s -o - | FileCheck %s -check-prefix SOFT3; RUN: llc -mtriple armeb-eabi -mattr v7,neon -float-abi hard %s -o - | FileCheck %s -check-prefix HARD4 5declare i64 @test_i64_f64_helper(double %p)6define void @test_i64_f64(ptr %p, ptr %q) {7; SOFT-LABEL: test_i64_f64:8; SOFT:       @ %bb.0:9; SOFT-NEXT:    .save {r4, lr}10; SOFT-NEXT:    push {r4, lr}11; SOFT-NEXT:    vldr d16, [r0]12; SOFT-NEXT:    mov r4, r113; SOFT-NEXT:    vadd.f64 d16, d16, d1614; SOFT-NEXT:    vmov r1, r0, d1615; SOFT-NEXT:    bl test_i64_f64_helper16; SOFT-NEXT:    adds r1, r1, r117; SOFT-NEXT:    adc r0, r0, r018; SOFT-NEXT:    strd r0, r1, [r4]19; SOFT-NEXT:    pop {r4, pc}20;21; HARD-LABEL: test_i64_f64:22; HARD:       @ %bb.0:23; HARD-NEXT:    .save {r4, lr}24; HARD-NEXT:    push {r4, lr}25; HARD-NEXT:    vldr d16, [r0]26; HARD-NEXT:    mov r4, r127; HARD-NEXT:    vadd.f64 d0, d16, d1628; HARD-NEXT:    bl test_i64_f64_helper29; HARD-NEXT:    adds r1, r1, r130; HARD-NEXT:    adc r0, r0, r031; HARD-NEXT:    strd r0, r1, [r4]32; HARD-NEXT:    pop {r4, pc}33    %1 = load double, ptr %p34    %2 = fadd double %1, %135    %3 = call i64 @test_i64_f64_helper(double %2)36    %4 = add i64 %3, %337    store i64 %4, ptr %q38    ret void39}40 41declare i64 @test_i64_v1i64_helper(<1 x i64> %p)42define void @test_i64_v1i64(ptr %p, ptr %q) {43; SOFT-LABEL: test_i64_v1i64:44; SOFT:       @ %bb.0:45; SOFT-NEXT:    .save {r4, lr}46; SOFT-NEXT:    push {r4, lr}47; SOFT-NEXT:    vldr d16, [r0]48; SOFT-NEXT:    mov r4, r149; SOFT-NEXT:    vadd.i64 d16, d16, d1650; SOFT-NEXT:    vmov r1, r0, d1651; SOFT-NEXT:    bl test_i64_v1i64_helper52; SOFT-NEXT:    adds r1, r1, r153; SOFT-NEXT:    adc r0, r0, r054; SOFT-NEXT:    strd r0, r1, [r4]55; SOFT-NEXT:    pop {r4, pc}56;57; HARD-LABEL: test_i64_v1i64:58; HARD:       @ %bb.0:59; HARD-NEXT:    .save {r4, lr}60; HARD-NEXT:    push {r4, lr}61; HARD-NEXT:    vldr d16, [r0]62; HARD-NEXT:    mov r4, r163; HARD-NEXT:    vadd.i64 d0, d16, d1664; HARD-NEXT:    bl test_i64_v1i64_helper65; HARD-NEXT:    adds r1, r1, r166; HARD-NEXT:    adc r0, r0, r067; HARD-NEXT:    strd r0, r1, [r4]68; HARD-NEXT:    pop {r4, pc}69    %1 = load <1 x i64>, ptr %p70    %2 = add <1 x i64> %1, %171    %3 = call i64 @test_i64_v1i64_helper(<1 x i64> %2)72    %4 = add i64 %3, %373    store i64 %4, ptr %q74    ret void75}76 77declare i64 @test_i64_v2f32_helper(<2 x float> %p)78define void @test_i64_v2f32(ptr %p, ptr %q) {79; SOFT-LABEL: test_i64_v2f32:80; SOFT:       @ %bb.0:81; SOFT-NEXT:    .save {r4, lr}82; SOFT-NEXT:    push {r4, lr}83; SOFT-NEXT:    vldr d16, [r0]84; SOFT-NEXT:    mov r4, r185; SOFT-NEXT:    vrev64.32 d16, d1686; SOFT-NEXT:    vadd.f32 d16, d16, d1687; SOFT-NEXT:    vrev64.32 d16, d1688; SOFT-NEXT:    vmov r1, r0, d1689; SOFT-NEXT:    bl test_i64_v2f32_helper90; SOFT-NEXT:    adds r1, r1, r191; SOFT-NEXT:    adc r0, r0, r092; SOFT-NEXT:    strd r0, r1, [r4]93; SOFT-NEXT:    pop {r4, pc}94;95; HARD-LABEL: test_i64_v2f32:96; HARD:       @ %bb.0:97; HARD-NEXT:    .save {r4, lr}98; HARD-NEXT:    push {r4, lr}99; HARD-NEXT:    vldr d16, [r0]100; HARD-NEXT:    mov r4, r1101; HARD-NEXT:    vrev64.32 d16, d16102; HARD-NEXT:    vadd.f32 d16, d16, d16103; HARD-NEXT:    vrev64.32 d0, d16104; HARD-NEXT:    bl test_i64_v2f32_helper105; HARD-NEXT:    adds r1, r1, r1106; HARD-NEXT:    adc r0, r0, r0107; HARD-NEXT:    strd r0, r1, [r4]108; HARD-NEXT:    pop {r4, pc}109    %1 = load <2 x float>, ptr %p110    %2 = fadd <2 x float> %1, %1111    %3 = call i64 @test_i64_v2f32_helper(<2 x float> %2)112    %4 = add i64 %3, %3113    store i64 %4, ptr %q114    ret void115}116 117declare i64 @test_i64_v2i32_helper(<2 x i32> %p)118define void @test_i64_v2i32(ptr %p, ptr %q) {119; SOFT-LABEL: test_i64_v2i32:120; SOFT:       @ %bb.0:121; SOFT-NEXT:    .save {r4, lr}122; SOFT-NEXT:    push {r4, lr}123; SOFT-NEXT:    vldr d16, [r0]124; SOFT-NEXT:    mov r4, r1125; SOFT-NEXT:    vrev64.32 d16, d16126; SOFT-NEXT:    vadd.i32 d16, d16, d16127; SOFT-NEXT:    vrev64.32 d16, d16128; SOFT-NEXT:    vmov r1, r0, d16129; SOFT-NEXT:    bl test_i64_v2i32_helper130; SOFT-NEXT:    adds r1, r1, r1131; SOFT-NEXT:    adc r0, r0, r0132; SOFT-NEXT:    strd r0, r1, [r4]133; SOFT-NEXT:    pop {r4, pc}134;135; HARD-LABEL: test_i64_v2i32:136; HARD:       @ %bb.0:137; HARD-NEXT:    .save {r4, lr}138; HARD-NEXT:    push {r4, lr}139; HARD-NEXT:    vldr d16, [r0]140; HARD-NEXT:    mov r4, r1141; HARD-NEXT:    vrev64.32 d16, d16142; HARD-NEXT:    vadd.i32 d16, d16, d16143; HARD-NEXT:    vrev64.32 d0, d16144; HARD-NEXT:    bl test_i64_v2i32_helper145; HARD-NEXT:    adds r1, r1, r1146; HARD-NEXT:    adc r0, r0, r0147; HARD-NEXT:    strd r0, r1, [r4]148; HARD-NEXT:    pop {r4, pc}149    %1 = load <2 x i32>, ptr %p150    %2 = add <2 x i32> %1, %1151    %3 = call i64 @test_i64_v2i32_helper(<2 x i32> %2)152    %4 = add i64 %3, %3153    store i64 %4, ptr %q154    ret void155}156 157declare i64 @test_i64_v4i16_helper(<4 x i16> %p)158define void @test_i64_v4i16(ptr %p, ptr %q) {159; SOFT-LABEL: test_i64_v4i16:160; SOFT:       @ %bb.0:161; SOFT-NEXT:    .save {r4, lr}162; SOFT-NEXT:    push {r4, lr}163; SOFT-NEXT:    vldr d16, [r0]164; SOFT-NEXT:    mov r4, r1165; SOFT-NEXT:    vrev64.16 d16, d16166; SOFT-NEXT:    vadd.i16 d16, d16, d16167; SOFT-NEXT:    vrev64.16 d16, d16168; SOFT-NEXT:    vmov r1, r0, d16169; SOFT-NEXT:    bl test_i64_v4i16_helper170; SOFT-NEXT:    adds r1, r1, r1171; SOFT-NEXT:    adc r0, r0, r0172; SOFT-NEXT:    strd r0, r1, [r4]173; SOFT-NEXT:    pop {r4, pc}174;175; HARD-LABEL: test_i64_v4i16:176; HARD:       @ %bb.0:177; HARD-NEXT:    .save {r4, lr}178; HARD-NEXT:    push {r4, lr}179; HARD-NEXT:    vldr d16, [r0]180; HARD-NEXT:    mov r4, r1181; HARD-NEXT:    vrev64.16 d16, d16182; HARD-NEXT:    vadd.i16 d16, d16, d16183; HARD-NEXT:    vrev64.16 d0, d16184; HARD-NEXT:    bl test_i64_v4i16_helper185; HARD-NEXT:    adds r1, r1, r1186; HARD-NEXT:    adc r0, r0, r0187; HARD-NEXT:    strd r0, r1, [r4]188; HARD-NEXT:    pop {r4, pc}189    %1 = load <4 x i16>, ptr %p190    %2 = add <4 x i16> %1, %1191    %3 = call i64 @test_i64_v4i16_helper(<4 x i16> %2)192    %4 = add i64 %3, %3193    store i64 %4, ptr %q194    ret void195}196 197declare i64 @test_i64_v8i8_helper(<8 x i8> %p)198define void @test_i64_v8i8(ptr %p, ptr %q) {199; SOFT-LABEL: test_i64_v8i8:200; SOFT:       @ %bb.0:201; SOFT-NEXT:    .save {r4, lr}202; SOFT-NEXT:    push {r4, lr}203; SOFT-NEXT:    vldr d16, [r0]204; SOFT-NEXT:    mov r4, r1205; SOFT-NEXT:    vrev64.8 d16, d16206; SOFT-NEXT:    vadd.i8 d16, d16, d16207; SOFT-NEXT:    vrev64.8 d16, d16208; SOFT-NEXT:    vmov r1, r0, d16209; SOFT-NEXT:    bl test_i64_v8i8_helper210; SOFT-NEXT:    adds r1, r1, r1211; SOFT-NEXT:    adc r0, r0, r0212; SOFT-NEXT:    strd r0, r1, [r4]213; SOFT-NEXT:    pop {r4, pc}214;215; HARD-LABEL: test_i64_v8i8:216; HARD:       @ %bb.0:217; HARD-NEXT:    .save {r4, lr}218; HARD-NEXT:    push {r4, lr}219; HARD-NEXT:    vldr d16, [r0]220; HARD-NEXT:    mov r4, r1221; HARD-NEXT:    vrev64.8 d16, d16222; HARD-NEXT:    vadd.i8 d16, d16, d16223; HARD-NEXT:    vrev64.8 d0, d16224; HARD-NEXT:    bl test_i64_v8i8_helper225; HARD-NEXT:    adds r1, r1, r1226; HARD-NEXT:    adc r0, r0, r0227; HARD-NEXT:    strd r0, r1, [r4]228; HARD-NEXT:    pop {r4, pc}229    %1 = load <8 x i8>, ptr %p230    %2 = add <8 x i8> %1, %1231    %3 = call i64 @test_i64_v8i8_helper(<8 x i8> %2)232    %4 = add i64 %3, %3233    store i64 %4, ptr %q234    ret void235}236 237declare double @test_f64_i64_helper(i64 %p)238define void @test_f64_i64(ptr %p, ptr %q) {239; SOFT-LABEL: test_f64_i64:240; SOFT:       @ %bb.0:241; SOFT-NEXT:    .save {r4, lr}242; SOFT-NEXT:    push {r4, lr}243; SOFT-NEXT:    mov r4, r1244; SOFT-NEXT:    ldrd r0, r1, [r0]245; SOFT-NEXT:    adds r1, r1, r1246; SOFT-NEXT:    adc r0, r0, r0247; SOFT-NEXT:    bl test_f64_i64_helper248; SOFT-NEXT:    vmov d16, r1, r0249; SOFT-NEXT:    vadd.f64 d16, d16, d16250; SOFT-NEXT:    vstr d16, [r4]251; SOFT-NEXT:    pop {r4, pc}252;253; HARD-LABEL: test_f64_i64:254; HARD:       @ %bb.0:255; HARD-NEXT:    .save {r4, lr}256; HARD-NEXT:    push {r4, lr}257; HARD-NEXT:    mov r4, r1258; HARD-NEXT:    ldrd r0, r1, [r0]259; HARD-NEXT:    adds r1, r1, r1260; HARD-NEXT:    adc r0, r0, r0261; HARD-NEXT:    bl test_f64_i64_helper262; HARD-NEXT:    vadd.f64 d16, d0, d0263; HARD-NEXT:    vstr d16, [r4]264; HARD-NEXT:    pop {r4, pc}265    %1 = load i64, ptr %p266    %2 = add i64 %1, %1267    %3 = call double @test_f64_i64_helper(i64 %2)268    %4 = fadd double %3, %3269    store double %4, ptr %q270    ret void271}272 273declare double @test_f64_v1i64_helper(<1 x i64> %p)274define void @test_f64_v1i64(ptr %p, ptr %q) {275; SOFT-LABEL: test_f64_v1i64:276; SOFT:       @ %bb.0:277; SOFT-NEXT:    .save {r4, lr}278; SOFT-NEXT:    push {r4, lr}279; SOFT-NEXT:    vldr d16, [r0]280; SOFT-NEXT:    mov r4, r1281; SOFT-NEXT:    vadd.i64 d16, d16, d16282; SOFT-NEXT:    vmov r1, r0, d16283; SOFT-NEXT:    bl test_f64_v1i64_helper284; SOFT-NEXT:    vmov d16, r1, r0285; SOFT-NEXT:    vadd.f64 d16, d16, d16286; SOFT-NEXT:    vstr d16, [r4]287; SOFT-NEXT:    pop {r4, pc}288;289; HARD-LABEL: test_f64_v1i64:290; HARD:       @ %bb.0:291; HARD-NEXT:    .save {r4, lr}292; HARD-NEXT:    push {r4, lr}293; HARD-NEXT:    vldr d16, [r0]294; HARD-NEXT:    mov r4, r1295; HARD-NEXT:    vadd.i64 d0, d16, d16296; HARD-NEXT:    bl test_f64_v1i64_helper297; HARD-NEXT:    vadd.f64 d16, d0, d0298; HARD-NEXT:    vstr d16, [r4]299; HARD-NEXT:    pop {r4, pc}300    %1 = load <1 x i64>, ptr %p301    %2 = add <1 x i64> %1, %1302    %3 = call double @test_f64_v1i64_helper(<1 x i64> %2)303    %4 = fadd double %3, %3304    store double %4, ptr %q305    ret void306}307 308declare double @test_f64_v2f32_helper(<2 x float> %p)309define void @test_f64_v2f32(ptr %p, ptr %q) {310; SOFT-LABEL: test_f64_v2f32:311; SOFT:       @ %bb.0:312; SOFT-NEXT:    .save {r4, lr}313; SOFT-NEXT:    push {r4, lr}314; SOFT-NEXT:    vldr d16, [r0]315; SOFT-NEXT:    mov r4, r1316; SOFT-NEXT:    vrev64.32 d16, d16317; SOFT-NEXT:    vadd.f32 d16, d16, d16318; SOFT-NEXT:    vrev64.32 d16, d16319; SOFT-NEXT:    vmov r1, r0, d16320; SOFT-NEXT:    bl test_f64_v2f32_helper321; SOFT-NEXT:    vmov d16, r1, r0322; SOFT-NEXT:    vadd.f64 d16, d16, d16323; SOFT-NEXT:    vstr d16, [r4]324; SOFT-NEXT:    pop {r4, pc}325;326; HARD-LABEL: test_f64_v2f32:327; HARD:       @ %bb.0:328; HARD-NEXT:    .save {r4, lr}329; HARD-NEXT:    push {r4, lr}330; HARD-NEXT:    vldr d16, [r0]331; HARD-NEXT:    mov r4, r1332; HARD-NEXT:    vrev64.32 d16, d16333; HARD-NEXT:    vadd.f32 d16, d16, d16334; HARD-NEXT:    vrev64.32 d0, d16335; HARD-NEXT:    bl test_f64_v2f32_helper336; HARD-NEXT:    vadd.f64 d16, d0, d0337; HARD-NEXT:    vstr d16, [r4]338; HARD-NEXT:    pop {r4, pc}339    %1 = load <2 x float>, ptr %p340    %2 = fadd <2 x float> %1, %1341    %3 = call double @test_f64_v2f32_helper(<2 x float> %2)342    %4 = fadd double %3, %3343    store double %4, ptr %q344    ret void345}346 347declare double @test_f64_v2i32_helper(<2 x i32> %p)348define void @test_f64_v2i32(ptr %p, ptr %q) {349; SOFT-LABEL: test_f64_v2i32:350; SOFT:       @ %bb.0:351; SOFT-NEXT:    .save {r4, lr}352; SOFT-NEXT:    push {r4, lr}353; SOFT-NEXT:    vldr d16, [r0]354; SOFT-NEXT:    mov r4, r1355; SOFT-NEXT:    vrev64.32 d16, d16356; SOFT-NEXT:    vadd.i32 d16, d16, d16357; SOFT-NEXT:    vrev64.32 d16, d16358; SOFT-NEXT:    vmov r1, r0, d16359; SOFT-NEXT:    bl test_f64_v2i32_helper360; SOFT-NEXT:    vmov d16, r1, r0361; SOFT-NEXT:    vadd.f64 d16, d16, d16362; SOFT-NEXT:    vstr d16, [r4]363; SOFT-NEXT:    pop {r4, pc}364;365; HARD-LABEL: test_f64_v2i32:366; HARD:       @ %bb.0:367; HARD-NEXT:    .save {r4, lr}368; HARD-NEXT:    push {r4, lr}369; HARD-NEXT:    vldr d16, [r0]370; HARD-NEXT:    mov r4, r1371; HARD-NEXT:    vrev64.32 d16, d16372; HARD-NEXT:    vadd.i32 d16, d16, d16373; HARD-NEXT:    vrev64.32 d0, d16374; HARD-NEXT:    bl test_f64_v2i32_helper375; HARD-NEXT:    vadd.f64 d16, d0, d0376; HARD-NEXT:    vstr d16, [r4]377; HARD-NEXT:    pop {r4, pc}378    %1 = load <2 x i32>, ptr %p379    %2 = add <2 x i32> %1, %1380    %3 = call double @test_f64_v2i32_helper(<2 x i32> %2)381    %4 = fadd double %3, %3382    store double %4, ptr %q383    ret void384}385 386declare double @test_f64_v4i16_helper(<4 x i16> %p)387define void @test_f64_v4i16(ptr %p, ptr %q) {388; SOFT-LABEL: test_f64_v4i16:389; SOFT:       @ %bb.0:390; SOFT-NEXT:    .save {r4, lr}391; SOFT-NEXT:    push {r4, lr}392; SOFT-NEXT:    vldr d16, [r0]393; SOFT-NEXT:    mov r4, r1394; SOFT-NEXT:    vrev64.16 d16, d16395; SOFT-NEXT:    vadd.i16 d16, d16, d16396; SOFT-NEXT:    vrev64.16 d16, d16397; SOFT-NEXT:    vmov r1, r0, d16398; SOFT-NEXT:    bl test_f64_v4i16_helper399; SOFT-NEXT:    vmov d16, r1, r0400; SOFT-NEXT:    vadd.f64 d16, d16, d16401; SOFT-NEXT:    vstr d16, [r4]402; SOFT-NEXT:    pop {r4, pc}403;404; HARD-LABEL: test_f64_v4i16:405; HARD:       @ %bb.0:406; HARD-NEXT:    .save {r4, lr}407; HARD-NEXT:    push {r4, lr}408; HARD-NEXT:    vldr d16, [r0]409; HARD-NEXT:    mov r4, r1410; HARD-NEXT:    vrev64.16 d16, d16411; HARD-NEXT:    vadd.i16 d16, d16, d16412; HARD-NEXT:    vrev64.16 d0, d16413; HARD-NEXT:    bl test_f64_v4i16_helper414; HARD-NEXT:    vadd.f64 d16, d0, d0415; HARD-NEXT:    vstr d16, [r4]416; HARD-NEXT:    pop {r4, pc}417    %1 = load <4 x i16>, ptr %p418    %2 = add <4 x i16> %1, %1419    %3 = call double @test_f64_v4i16_helper(<4 x i16> %2)420    %4 = fadd double %3, %3421    store double %4, ptr %q422    ret void423}424 425declare double @test_f64_v8i8_helper(<8 x i8> %p)426define void @test_f64_v8i8(ptr %p, ptr %q) {427; SOFT-LABEL: test_f64_v8i8:428; SOFT:       @ %bb.0:429; SOFT-NEXT:    .save {r4, lr}430; SOFT-NEXT:    push {r4, lr}431; SOFT-NEXT:    vldr d16, [r0]432; SOFT-NEXT:    mov r4, r1433; SOFT-NEXT:    vrev64.8 d16, d16434; SOFT-NEXT:    vadd.i8 d16, d16, d16435; SOFT-NEXT:    vrev64.8 d16, d16436; SOFT-NEXT:    vmov r1, r0, d16437; SOFT-NEXT:    bl test_f64_v8i8_helper438; SOFT-NEXT:    vmov d16, r1, r0439; SOFT-NEXT:    vadd.f64 d16, d16, d16440; SOFT-NEXT:    vstr d16, [r4]441; SOFT-NEXT:    pop {r4, pc}442;443; HARD-LABEL: test_f64_v8i8:444; HARD:       @ %bb.0:445; HARD-NEXT:    .save {r4, lr}446; HARD-NEXT:    push {r4, lr}447; HARD-NEXT:    vldr d16, [r0]448; HARD-NEXT:    mov r4, r1449; HARD-NEXT:    vrev64.8 d16, d16450; HARD-NEXT:    vadd.i8 d16, d16, d16451; HARD-NEXT:    vrev64.8 d0, d16452; HARD-NEXT:    bl test_f64_v8i8_helper453; HARD-NEXT:    vadd.f64 d16, d0, d0454; HARD-NEXT:    vstr d16, [r4]455; HARD-NEXT:    pop {r4, pc}456    %1 = load <8 x i8>, ptr %p457    %2 = add <8 x i8> %1, %1458    %3 = call double @test_f64_v8i8_helper(<8 x i8> %2)459    %4 = fadd double %3, %3460    store double %4, ptr %q461    ret void462}463 464declare <1 x i64> @test_v1i64_i64_helper(i64 %p)465define void @test_v1i64_i64(ptr %p, ptr %q) {466; SOFT-LABEL: test_v1i64_i64:467; SOFT:       @ %bb.0:468; SOFT-NEXT:    .save {r4, lr}469; SOFT-NEXT:    push {r4, lr}470; SOFT-NEXT:    mov r4, r1471; SOFT-NEXT:    ldrd r0, r1, [r0]472; SOFT-NEXT:    adds r1, r1, r1473; SOFT-NEXT:    adc r0, r0, r0474; SOFT-NEXT:    bl test_v1i64_i64_helper475; SOFT-NEXT:    vmov d16, r1, r0476; SOFT-NEXT:    vadd.i64 d16, d16, d16477; SOFT-NEXT:    vstr d16, [r4]478; SOFT-NEXT:    pop {r4, pc}479;480; HARD-LABEL: test_v1i64_i64:481; HARD:       @ %bb.0:482; HARD-NEXT:    .save {r4, lr}483; HARD-NEXT:    push {r4, lr}484; HARD-NEXT:    mov r4, r1485; HARD-NEXT:    ldrd r0, r1, [r0]486; HARD-NEXT:    adds r1, r1, r1487; HARD-NEXT:    adc r0, r0, r0488; HARD-NEXT:    bl test_v1i64_i64_helper489; HARD-NEXT:    vadd.i64 d16, d0, d0490; HARD-NEXT:    vstr d16, [r4]491; HARD-NEXT:    pop {r4, pc}492    %1 = load i64, ptr %p493    %2 = add i64 %1, %1494    %3 = call <1 x i64> @test_v1i64_i64_helper(i64 %2)495    %4 = add <1 x i64> %3, %3496    store <1 x i64> %4, ptr %q497    ret void498}499 500declare <1 x i64> @test_v1i64_f64_helper(double %p)501define void @test_v1i64_f64(ptr %p, ptr %q) {502; SOFT-LABEL: test_v1i64_f64:503; SOFT:       @ %bb.0:504; SOFT-NEXT:    .save {r4, lr}505; SOFT-NEXT:    push {r4, lr}506; SOFT-NEXT:    vldr d16, [r0]507; SOFT-NEXT:    mov r4, r1508; SOFT-NEXT:    vadd.f64 d16, d16, d16509; SOFT-NEXT:    vmov r1, r0, d16510; SOFT-NEXT:    bl test_v1i64_f64_helper511; SOFT-NEXT:    vmov d16, r1, r0512; SOFT-NEXT:    vadd.i64 d16, d16, d16513; SOFT-NEXT:    vstr d16, [r4]514; SOFT-NEXT:    pop {r4, pc}515;516; HARD-LABEL: test_v1i64_f64:517; HARD:       @ %bb.0:518; HARD-NEXT:    .save {r4, lr}519; HARD-NEXT:    push {r4, lr}520; HARD-NEXT:    vldr d16, [r0]521; HARD-NEXT:    mov r4, r1522; HARD-NEXT:    vadd.f64 d0, d16, d16523; HARD-NEXT:    bl test_v1i64_f64_helper524; HARD-NEXT:    vadd.i64 d16, d0, d0525; HARD-NEXT:    vstr d16, [r4]526; HARD-NEXT:    pop {r4, pc}527    %1 = load double, ptr %p528    %2 = fadd double %1, %1529    %3 = call <1 x i64> @test_v1i64_f64_helper(double %2)530    %4 = add <1 x i64> %3, %3531    store <1 x i64> %4, ptr %q532    ret void533}534 535declare <1 x i64> @test_v1i64_v2f32_helper(<2 x float> %p)536define void @test_v1i64_v2f32(ptr %p, ptr %q) {537; SOFT-LABEL: test_v1i64_v2f32:538; SOFT:       @ %bb.0:539; SOFT-NEXT:    .save {r4, lr}540; SOFT-NEXT:    push {r4, lr}541; SOFT-NEXT:    vldr d16, [r0]542; SOFT-NEXT:    mov r4, r1543; SOFT-NEXT:    vrev64.32 d16, d16544; SOFT-NEXT:    vadd.f32 d16, d16, d16545; SOFT-NEXT:    vrev64.32 d16, d16546; SOFT-NEXT:    vmov r1, r0, d16547; SOFT-NEXT:    bl test_v1i64_v2f32_helper548; SOFT-NEXT:    vmov d16, r1, r0549; SOFT-NEXT:    vadd.i64 d16, d16, d16550; SOFT-NEXT:    vstr d16, [r4]551; SOFT-NEXT:    pop {r4, pc}552;553; HARD-LABEL: test_v1i64_v2f32:554; HARD:       @ %bb.0:555; HARD-NEXT:    .save {r4, lr}556; HARD-NEXT:    push {r4, lr}557; HARD-NEXT:    vldr d16, [r0]558; HARD-NEXT:    mov r4, r1559; HARD-NEXT:    vrev64.32 d16, d16560; HARD-NEXT:    vadd.f32 d16, d16, d16561; HARD-NEXT:    vrev64.32 d0, d16562; HARD-NEXT:    bl test_v1i64_v2f32_helper563; HARD-NEXT:    vadd.i64 d16, d0, d0564; HARD-NEXT:    vstr d16, [r4]565; HARD-NEXT:    pop {r4, pc}566    %1 = load <2 x float>, ptr %p567    %2 = fadd <2 x float> %1, %1568    %3 = call <1 x i64> @test_v1i64_v2f32_helper(<2 x float> %2)569    %4 = add <1 x i64> %3, %3570    store <1 x i64> %4, ptr %q571    ret void572}573 574declare <1 x i64> @test_v1i64_v2i32_helper(<2 x i32> %p)575define void @test_v1i64_v2i32(ptr %p, ptr %q) {576; SOFT-LABEL: test_v1i64_v2i32:577; SOFT:       @ %bb.0:578; SOFT-NEXT:    .save {r4, lr}579; SOFT-NEXT:    push {r4, lr}580; SOFT-NEXT:    vldr d16, [r0]581; SOFT-NEXT:    mov r4, r1582; SOFT-NEXT:    vrev64.32 d16, d16583; SOFT-NEXT:    vadd.i32 d16, d16, d16584; SOFT-NEXT:    vrev64.32 d16, d16585; SOFT-NEXT:    vmov r1, r0, d16586; SOFT-NEXT:    bl test_v1i64_v2i32_helper587; SOFT-NEXT:    vmov d16, r1, r0588; SOFT-NEXT:    vadd.i64 d16, d16, d16589; SOFT-NEXT:    vstr d16, [r4]590; SOFT-NEXT:    pop {r4, pc}591;592; HARD-LABEL: test_v1i64_v2i32:593; HARD:       @ %bb.0:594; HARD-NEXT:    .save {r4, lr}595; HARD-NEXT:    push {r4, lr}596; HARD-NEXT:    vldr d16, [r0]597; HARD-NEXT:    mov r4, r1598; HARD-NEXT:    vrev64.32 d16, d16599; HARD-NEXT:    vadd.i32 d16, d16, d16600; HARD-NEXT:    vrev64.32 d0, d16601; HARD-NEXT:    bl test_v1i64_v2i32_helper602; HARD-NEXT:    vadd.i64 d16, d0, d0603; HARD-NEXT:    vstr d16, [r4]604; HARD-NEXT:    pop {r4, pc}605    %1 = load <2 x i32>, ptr %p606    %2 = add <2 x i32> %1, %1607    %3 = call <1 x i64> @test_v1i64_v2i32_helper(<2 x i32> %2)608    %4 = add <1 x i64> %3, %3609    store <1 x i64> %4, ptr %q610    ret void611}612 613declare <1 x i64> @test_v1i64_v4i16_helper(<4 x i16> %p)614define void @test_v1i64_v4i16(ptr %p, ptr %q) {615; SOFT-LABEL: test_v1i64_v4i16:616; SOFT:       @ %bb.0:617; SOFT-NEXT:    .save {r4, lr}618; SOFT-NEXT:    push {r4, lr}619; SOFT-NEXT:    vldr d16, [r0]620; SOFT-NEXT:    mov r4, r1621; SOFT-NEXT:    vrev64.16 d16, d16622; SOFT-NEXT:    vadd.i16 d16, d16, d16623; SOFT-NEXT:    vrev64.16 d16, d16624; SOFT-NEXT:    vmov r1, r0, d16625; SOFT-NEXT:    bl test_v1i64_v4i16_helper626; SOFT-NEXT:    vmov d16, r1, r0627; SOFT-NEXT:    vadd.i64 d16, d16, d16628; SOFT-NEXT:    vstr d16, [r4]629; SOFT-NEXT:    pop {r4, pc}630;631; HARD-LABEL: test_v1i64_v4i16:632; HARD:       @ %bb.0:633; HARD-NEXT:    .save {r4, lr}634; HARD-NEXT:    push {r4, lr}635; HARD-NEXT:    vldr d16, [r0]636; HARD-NEXT:    mov r4, r1637; HARD-NEXT:    vrev64.16 d16, d16638; HARD-NEXT:    vadd.i16 d16, d16, d16639; HARD-NEXT:    vrev64.16 d0, d16640; HARD-NEXT:    bl test_v1i64_v4i16_helper641; HARD-NEXT:    vadd.i64 d16, d0, d0642; HARD-NEXT:    vstr d16, [r4]643; HARD-NEXT:    pop {r4, pc}644    %1 = load <4 x i16>, ptr %p645    %2 = add <4 x i16> %1, %1646    %3 = call <1 x i64> @test_v1i64_v4i16_helper(<4 x i16> %2)647    %4 = add <1 x i64> %3, %3648    store <1 x i64> %4, ptr %q649    ret void650}651 652declare <1 x i64> @test_v1i64_v8i8_helper(<8 x i8> %p)653define void @test_v1i64_v8i8(ptr %p, ptr %q) {654; SOFT-LABEL: test_v1i64_v8i8:655; SOFT:       @ %bb.0:656; SOFT-NEXT:    .save {r4, lr}657; SOFT-NEXT:    push {r4, lr}658; SOFT-NEXT:    vldr d16, [r0]659; SOFT-NEXT:    mov r4, r1660; SOFT-NEXT:    vrev64.8 d16, d16661; SOFT-NEXT:    vadd.i8 d16, d16, d16662; SOFT-NEXT:    vrev64.8 d16, d16663; SOFT-NEXT:    vmov r1, r0, d16664; SOFT-NEXT:    bl test_v1i64_v8i8_helper665; SOFT-NEXT:    vmov d16, r1, r0666; SOFT-NEXT:    vadd.i64 d16, d16, d16667; SOFT-NEXT:    vstr d16, [r4]668; SOFT-NEXT:    pop {r4, pc}669;670; HARD-LABEL: test_v1i64_v8i8:671; HARD:       @ %bb.0:672; HARD-NEXT:    .save {r4, lr}673; HARD-NEXT:    push {r4, lr}674; HARD-NEXT:    vldr d16, [r0]675; HARD-NEXT:    mov r4, r1676; HARD-NEXT:    vrev64.8 d16, d16677; HARD-NEXT:    vadd.i8 d16, d16, d16678; HARD-NEXT:    vrev64.8 d0, d16679; HARD-NEXT:    bl test_v1i64_v8i8_helper680; HARD-NEXT:    vadd.i64 d16, d0, d0681; HARD-NEXT:    vstr d16, [r4]682; HARD-NEXT:    pop {r4, pc}683    %1 = load <8 x i8>, ptr %p684    %2 = add <8 x i8> %1, %1685    %3 = call <1 x i64> @test_v1i64_v8i8_helper(<8 x i8> %2)686    %4 = add <1 x i64> %3, %3687    store <1 x i64> %4, ptr %q688    ret void689}690 691declare <2 x float> @test_v2f32_i64_helper(i64 %p)692define void @test_v2f32_i64(ptr %p, ptr %q) {693; SOFT-LABEL: test_v2f32_i64:694; SOFT:       @ %bb.0:695; SOFT-NEXT:    .save {r4, lr}696; SOFT-NEXT:    push {r4, lr}697; SOFT-NEXT:    mov r4, r1698; SOFT-NEXT:    ldrd r0, r1, [r0]699; SOFT-NEXT:    adds r1, r1, r1700; SOFT-NEXT:    adc r0, r0, r0701; SOFT-NEXT:    bl test_v2f32_i64_helper702; SOFT-NEXT:    vmov d16, r1, r0703; SOFT-NEXT:    vrev64.32 d16, d16704; SOFT-NEXT:    vadd.f32 d16, d16, d16705; SOFT-NEXT:    vrev64.32 d16, d16706; SOFT-NEXT:    vstr d16, [r4]707; SOFT-NEXT:    pop {r4, pc}708;709; HARD-LABEL: test_v2f32_i64:710; HARD:       @ %bb.0:711; HARD-NEXT:    .save {r4, lr}712; HARD-NEXT:    push {r4, lr}713; HARD-NEXT:    mov r4, r1714; HARD-NEXT:    ldrd r0, r1, [r0]715; HARD-NEXT:    adds r1, r1, r1716; HARD-NEXT:    adc r0, r0, r0717; HARD-NEXT:    bl test_v2f32_i64_helper718; HARD-NEXT:    vrev64.32 d16, d0719; HARD-NEXT:    vadd.f32 d16, d16, d16720; HARD-NEXT:    vrev64.32 d16, d16721; HARD-NEXT:    vstr d16, [r4]722; HARD-NEXT:    pop {r4, pc}723    %1 = load i64, ptr %p724    %2 = add i64 %1, %1725    %3 = call <2 x float> @test_v2f32_i64_helper(i64 %2)726    %4 = fadd <2 x float> %3, %3727    store <2 x float> %4, ptr %q728    ret void729}730 731declare <2 x float> @test_v2f32_f64_helper(double %p)732define void @test_v2f32_f64(ptr %p, ptr %q) {733; SOFT-LABEL: test_v2f32_f64:734; SOFT:       @ %bb.0:735; SOFT-NEXT:    .save {r4, lr}736; SOFT-NEXT:    push {r4, lr}737; SOFT-NEXT:    vldr d16, [r0]738; SOFT-NEXT:    mov r4, r1739; SOFT-NEXT:    vadd.f64 d16, d16, d16740; SOFT-NEXT:    vmov r1, r0, d16741; SOFT-NEXT:    bl test_v2f32_f64_helper742; SOFT-NEXT:    vmov d16, r1, r0743; SOFT-NEXT:    vrev64.32 d16, d16744; SOFT-NEXT:    vadd.f32 d16, d16, d16745; SOFT-NEXT:    vrev64.32 d16, d16746; SOFT-NEXT:    vstr d16, [r4]747; SOFT-NEXT:    pop {r4, pc}748;749; HARD-LABEL: test_v2f32_f64:750; HARD:       @ %bb.0:751; HARD-NEXT:    .save {r4, lr}752; HARD-NEXT:    push {r4, lr}753; HARD-NEXT:    vldr d16, [r0]754; HARD-NEXT:    mov r4, r1755; HARD-NEXT:    vadd.f64 d0, d16, d16756; HARD-NEXT:    bl test_v2f32_f64_helper757; HARD-NEXT:    vrev64.32 d16, d0758; HARD-NEXT:    vadd.f32 d16, d16, d16759; HARD-NEXT:    vrev64.32 d16, d16760; HARD-NEXT:    vstr d16, [r4]761; HARD-NEXT:    pop {r4, pc}762    %1 = load double, ptr %p763    %2 = fadd double %1, %1764    %3 = call <2 x float> @test_v2f32_f64_helper(double %2)765    %4 = fadd <2 x float> %3, %3766    store <2 x float> %4, ptr %q767    ret void768}769 770declare <2 x float> @test_v2f32_v1i64_helper(<1 x i64> %p)771define void @test_v2f32_v1i64(ptr %p, ptr %q) {772; SOFT-LABEL: test_v2f32_v1i64:773; SOFT:       @ %bb.0:774; SOFT-NEXT:    .save {r4, lr}775; SOFT-NEXT:    push {r4, lr}776; SOFT-NEXT:    vldr d16, [r0]777; SOFT-NEXT:    mov r4, r1778; SOFT-NEXT:    vadd.i64 d16, d16, d16779; SOFT-NEXT:    vmov r1, r0, d16780; SOFT-NEXT:    bl test_v2f32_v1i64_helper781; SOFT-NEXT:    vmov d16, r1, r0782; SOFT-NEXT:    vrev64.32 d16, d16783; SOFT-NEXT:    vadd.f32 d16, d16, d16784; SOFT-NEXT:    vrev64.32 d16, d16785; SOFT-NEXT:    vstr d16, [r4]786; SOFT-NEXT:    pop {r4, pc}787;788; HARD-LABEL: test_v2f32_v1i64:789; HARD:       @ %bb.0:790; HARD-NEXT:    .save {r4, lr}791; HARD-NEXT:    push {r4, lr}792; HARD-NEXT:    vldr d16, [r0]793; HARD-NEXT:    mov r4, r1794; HARD-NEXT:    vadd.i64 d0, d16, d16795; HARD-NEXT:    bl test_v2f32_v1i64_helper796; HARD-NEXT:    vrev64.32 d16, d0797; HARD-NEXT:    vadd.f32 d16, d16, d16798; HARD-NEXT:    vrev64.32 d16, d16799; HARD-NEXT:    vstr d16, [r4]800; HARD-NEXT:    pop {r4, pc}801    %1 = load <1 x i64>, ptr %p802    %2 = add <1 x i64> %1, %1803    %3 = call <2 x float> @test_v2f32_v1i64_helper(<1 x i64> %2)804    %4 = fadd <2 x float> %3, %3805    store <2 x float> %4, ptr %q806    ret void807}808 809declare <2 x float> @test_v2f32_v2i32_helper(<2 x i32> %p)810define void @test_v2f32_v2i32(ptr %p, ptr %q) {811; SOFT-LABEL: test_v2f32_v2i32:812; SOFT:       @ %bb.0:813; SOFT-NEXT:    .save {r4, lr}814; SOFT-NEXT:    push {r4, lr}815; SOFT-NEXT:    vldr d16, [r0]816; SOFT-NEXT:    mov r4, r1817; SOFT-NEXT:    vrev64.32 d16, d16818; SOFT-NEXT:    vadd.i32 d16, d16, d16819; SOFT-NEXT:    vrev64.32 d16, d16820; SOFT-NEXT:    vmov r1, r0, d16821; SOFT-NEXT:    bl test_v2f32_v2i32_helper822; SOFT-NEXT:    vmov d16, r1, r0823; SOFT-NEXT:    vrev64.32 d16, d16824; SOFT-NEXT:    vadd.f32 d16, d16, d16825; SOFT-NEXT:    vrev64.32 d16, d16826; SOFT-NEXT:    vstr d16, [r4]827; SOFT-NEXT:    pop {r4, pc}828;829; HARD-LABEL: test_v2f32_v2i32:830; HARD:       @ %bb.0:831; HARD-NEXT:    .save {r4, lr}832; HARD-NEXT:    push {r4, lr}833; HARD-NEXT:    vldr d16, [r0]834; HARD-NEXT:    mov r4, r1835; HARD-NEXT:    vrev64.32 d16, d16836; HARD-NEXT:    vadd.i32 d16, d16, d16837; HARD-NEXT:    vrev64.32 d0, d16838; HARD-NEXT:    bl test_v2f32_v2i32_helper839; HARD-NEXT:    vrev64.32 d16, d0840; HARD-NEXT:    vadd.f32 d16, d16, d16841; HARD-NEXT:    vrev64.32 d16, d16842; HARD-NEXT:    vstr d16, [r4]843; HARD-NEXT:    pop {r4, pc}844    %1 = load <2 x i32>, ptr %p845    %2 = add <2 x i32> %1, %1846    %3 = call <2 x float> @test_v2f32_v2i32_helper(<2 x i32> %2)847    %4 = fadd <2 x float> %3, %3848    store <2 x float> %4, ptr %q849    ret void850}851 852declare <2 x float> @test_v2f32_v4i16_helper(<4 x i16> %p)853define void @test_v2f32_v4i16(ptr %p, ptr %q) {854; SOFT-LABEL: test_v2f32_v4i16:855; SOFT:       @ %bb.0:856; SOFT-NEXT:    .save {r4, lr}857; SOFT-NEXT:    push {r4, lr}858; SOFT-NEXT:    vldr d16, [r0]859; SOFT-NEXT:    mov r4, r1860; SOFT-NEXT:    vrev64.16 d16, d16861; SOFT-NEXT:    vadd.i16 d16, d16, d16862; SOFT-NEXT:    vrev64.16 d16, d16863; SOFT-NEXT:    vmov r1, r0, d16864; SOFT-NEXT:    bl test_v2f32_v4i16_helper865; SOFT-NEXT:    vmov d16, r1, r0866; SOFT-NEXT:    vrev64.32 d16, d16867; SOFT-NEXT:    vadd.f32 d16, d16, d16868; SOFT-NEXT:    vrev64.32 d16, d16869; SOFT-NEXT:    vstr d16, [r4]870; SOFT-NEXT:    pop {r4, pc}871;872; HARD-LABEL: test_v2f32_v4i16:873; HARD:       @ %bb.0:874; HARD-NEXT:    .save {r4, lr}875; HARD-NEXT:    push {r4, lr}876; HARD-NEXT:    vldr d16, [r0]877; HARD-NEXT:    mov r4, r1878; HARD-NEXT:    vrev64.16 d16, d16879; HARD-NEXT:    vadd.i16 d16, d16, d16880; HARD-NEXT:    vrev64.16 d0, d16881; HARD-NEXT:    bl test_v2f32_v4i16_helper882; HARD-NEXT:    vrev64.32 d16, d0883; HARD-NEXT:    vadd.f32 d16, d16, d16884; HARD-NEXT:    vrev64.32 d16, d16885; HARD-NEXT:    vstr d16, [r4]886; HARD-NEXT:    pop {r4, pc}887    %1 = load <4 x i16>, ptr %p888    %2 = add <4 x i16> %1, %1889    %3 = call <2 x float> @test_v2f32_v4i16_helper(<4 x i16> %2)890    %4 = fadd <2 x float> %3, %3891    store <2 x float> %4, ptr %q892    ret void893}894 895declare <2 x float> @test_v2f32_v8i8_helper(<8 x i8> %p)896define void @test_v2f32_v8i8(ptr %p, ptr %q) {897; SOFT-LABEL: test_v2f32_v8i8:898; SOFT:       @ %bb.0:899; SOFT-NEXT:    .save {r4, lr}900; SOFT-NEXT:    push {r4, lr}901; SOFT-NEXT:    vldr d16, [r0]902; SOFT-NEXT:    mov r4, r1903; SOFT-NEXT:    vrev64.8 d16, d16904; SOFT-NEXT:    vadd.i8 d16, d16, d16905; SOFT-NEXT:    vrev64.8 d16, d16906; SOFT-NEXT:    vmov r1, r0, d16907; SOFT-NEXT:    bl test_v2f32_v8i8_helper908; SOFT-NEXT:    vmov d16, r1, r0909; SOFT-NEXT:    vrev64.32 d16, d16910; SOFT-NEXT:    vadd.f32 d16, d16, d16911; SOFT-NEXT:    vrev64.32 d16, d16912; SOFT-NEXT:    vstr d16, [r4]913; SOFT-NEXT:    pop {r4, pc}914;915; HARD-LABEL: test_v2f32_v8i8:916; HARD:       @ %bb.0:917; HARD-NEXT:    .save {r4, lr}918; HARD-NEXT:    push {r4, lr}919; HARD-NEXT:    vldr d16, [r0]920; HARD-NEXT:    mov r4, r1921; HARD-NEXT:    vrev64.8 d16, d16922; HARD-NEXT:    vadd.i8 d16, d16, d16923; HARD-NEXT:    vrev64.8 d0, d16924; HARD-NEXT:    bl test_v2f32_v8i8_helper925; HARD-NEXT:    vrev64.32 d16, d0926; HARD-NEXT:    vadd.f32 d16, d16, d16927; HARD-NEXT:    vrev64.32 d16, d16928; HARD-NEXT:    vstr d16, [r4]929; HARD-NEXT:    pop {r4, pc}930    %1 = load <8 x i8>, ptr %p931    %2 = add <8 x i8> %1, %1932    %3 = call <2 x float> @test_v2f32_v8i8_helper(<8 x i8> %2)933    %4 = fadd <2 x float> %3, %3934    store <2 x float> %4, ptr %q935    ret void936}937 938declare <2 x i32> @test_v2i32_i64_helper(i64 %p)939define void @test_v2i32_i64(ptr %p, ptr %q) {940; SOFT-LABEL: test_v2i32_i64:941; SOFT:       @ %bb.0:942; SOFT-NEXT:    .save {r4, lr}943; SOFT-NEXT:    push {r4, lr}944; SOFT-NEXT:    mov r4, r1945; SOFT-NEXT:    ldrd r0, r1, [r0]946; SOFT-NEXT:    adds r1, r1, r1947; SOFT-NEXT:    adc r0, r0, r0948; SOFT-NEXT:    bl test_v2i32_i64_helper949; SOFT-NEXT:    vmov d16, r1, r0950; SOFT-NEXT:    vrev64.32 d16, d16951; SOFT-NEXT:    vadd.i32 d16, d16, d16952; SOFT-NEXT:    vrev64.32 d16, d16953; SOFT-NEXT:    vstr d16, [r4]954; SOFT-NEXT:    pop {r4, pc}955;956; HARD-LABEL: test_v2i32_i64:957; HARD:       @ %bb.0:958; HARD-NEXT:    .save {r4, lr}959; HARD-NEXT:    push {r4, lr}960; HARD-NEXT:    mov r4, r1961; HARD-NEXT:    ldrd r0, r1, [r0]962; HARD-NEXT:    adds r1, r1, r1963; HARD-NEXT:    adc r0, r0, r0964; HARD-NEXT:    bl test_v2i32_i64_helper965; HARD-NEXT:    vrev64.32 d16, d0966; HARD-NEXT:    vadd.i32 d16, d16, d16967; HARD-NEXT:    vrev64.32 d16, d16968; HARD-NEXT:    vstr d16, [r4]969; HARD-NEXT:    pop {r4, pc}970    %1 = load i64, ptr %p971    %2 = add i64 %1, %1972    %3 = call <2 x i32> @test_v2i32_i64_helper(i64 %2)973    %4 = add <2 x i32> %3, %3974    store <2 x i32> %4, ptr %q975    ret void976}977 978declare <2 x i32> @test_v2i32_f64_helper(double %p)979define void @test_v2i32_f64(ptr %p, ptr %q) {980; SOFT-LABEL: test_v2i32_f64:981; SOFT:       @ %bb.0:982; SOFT-NEXT:    .save {r4, lr}983; SOFT-NEXT:    push {r4, lr}984; SOFT-NEXT:    vldr d16, [r0]985; SOFT-NEXT:    mov r4, r1986; SOFT-NEXT:    vadd.f64 d16, d16, d16987; SOFT-NEXT:    vmov r1, r0, d16988; SOFT-NEXT:    bl test_v2i32_f64_helper989; SOFT-NEXT:    vmov d16, r1, r0990; SOFT-NEXT:    vrev64.32 d16, d16991; SOFT-NEXT:    vadd.i32 d16, d16, d16992; SOFT-NEXT:    vrev64.32 d16, d16993; SOFT-NEXT:    vstr d16, [r4]994; SOFT-NEXT:    pop {r4, pc}995;996; HARD-LABEL: test_v2i32_f64:997; HARD:       @ %bb.0:998; HARD-NEXT:    .save {r4, lr}999; HARD-NEXT:    push {r4, lr}1000; HARD-NEXT:    vldr d16, [r0]1001; HARD-NEXT:    mov r4, r11002; HARD-NEXT:    vadd.f64 d0, d16, d161003; HARD-NEXT:    bl test_v2i32_f64_helper1004; HARD-NEXT:    vrev64.32 d16, d01005; HARD-NEXT:    vadd.i32 d16, d16, d161006; HARD-NEXT:    vrev64.32 d16, d161007; HARD-NEXT:    vstr d16, [r4]1008; HARD-NEXT:    pop {r4, pc}1009    %1 = load double, ptr %p1010    %2 = fadd double %1, %11011    %3 = call <2 x i32> @test_v2i32_f64_helper(double %2)1012    %4 = add <2 x i32> %3, %31013    store <2 x i32> %4, ptr %q1014    ret void1015}1016 1017declare <2 x i32> @test_v2i32_v1i64_helper(<1 x i64> %p)1018define void @test_v2i32_v1i64(ptr %p, ptr %q) {1019; SOFT-LABEL: test_v2i32_v1i64:1020; SOFT:       @ %bb.0:1021; SOFT-NEXT:    .save {r4, lr}1022; SOFT-NEXT:    push {r4, lr}1023; SOFT-NEXT:    vldr d16, [r0]1024; SOFT-NEXT:    mov r4, r11025; SOFT-NEXT:    vadd.i64 d16, d16, d161026; SOFT-NEXT:    vmov r1, r0, d161027; SOFT-NEXT:    bl test_v2i32_v1i64_helper1028; SOFT-NEXT:    vmov d16, r1, r01029; SOFT-NEXT:    vrev64.32 d16, d161030; SOFT-NEXT:    vadd.i32 d16, d16, d161031; SOFT-NEXT:    vrev64.32 d16, d161032; SOFT-NEXT:    vstr d16, [r4]1033; SOFT-NEXT:    pop {r4, pc}1034;1035; HARD-LABEL: test_v2i32_v1i64:1036; HARD:       @ %bb.0:1037; HARD-NEXT:    .save {r4, lr}1038; HARD-NEXT:    push {r4, lr}1039; HARD-NEXT:    vldr d16, [r0]1040; HARD-NEXT:    mov r4, r11041; HARD-NEXT:    vadd.i64 d0, d16, d161042; HARD-NEXT:    bl test_v2i32_v1i64_helper1043; HARD-NEXT:    vrev64.32 d16, d01044; HARD-NEXT:    vadd.i32 d16, d16, d161045; HARD-NEXT:    vrev64.32 d16, d161046; HARD-NEXT:    vstr d16, [r4]1047; HARD-NEXT:    pop {r4, pc}1048    %1 = load <1 x i64>, ptr %p1049    %2 = add <1 x i64> %1, %11050    %3 = call <2 x i32> @test_v2i32_v1i64_helper(<1 x i64> %2)1051    %4 = add <2 x i32> %3, %31052    store <2 x i32> %4, ptr %q1053    ret void1054}1055 1056declare <2 x i32> @test_v2i32_v2f32_helper(<2 x float> %p)1057define void @test_v2i32_v2f32(ptr %p, ptr %q) {1058; SOFT-LABEL: test_v2i32_v2f32:1059; SOFT:       @ %bb.0:1060; SOFT-NEXT:    .save {r4, lr}1061; SOFT-NEXT:    push {r4, lr}1062; SOFT-NEXT:    vldr d16, [r0]1063; SOFT-NEXT:    mov r4, r11064; SOFT-NEXT:    vrev64.32 d16, d161065; SOFT-NEXT:    vadd.f32 d16, d16, d161066; SOFT-NEXT:    vrev64.32 d16, d161067; SOFT-NEXT:    vmov r1, r0, d161068; SOFT-NEXT:    bl test_v2i32_v2f32_helper1069; SOFT-NEXT:    vmov d16, r1, r01070; SOFT-NEXT:    vrev64.32 d16, d161071; SOFT-NEXT:    vadd.i32 d16, d16, d161072; SOFT-NEXT:    vrev64.32 d16, d161073; SOFT-NEXT:    vstr d16, [r4]1074; SOFT-NEXT:    pop {r4, pc}1075;1076; HARD-LABEL: test_v2i32_v2f32:1077; HARD:       @ %bb.0:1078; HARD-NEXT:    .save {r4, lr}1079; HARD-NEXT:    push {r4, lr}1080; HARD-NEXT:    vldr d16, [r0]1081; HARD-NEXT:    mov r4, r11082; HARD-NEXT:    vrev64.32 d16, d161083; HARD-NEXT:    vadd.f32 d16, d16, d161084; HARD-NEXT:    vrev64.32 d0, d161085; HARD-NEXT:    bl test_v2i32_v2f32_helper1086; HARD-NEXT:    vrev64.32 d16, d01087; HARD-NEXT:    vadd.i32 d16, d16, d161088; HARD-NEXT:    vrev64.32 d16, d161089; HARD-NEXT:    vstr d16, [r4]1090; HARD-NEXT:    pop {r4, pc}1091    %1 = load <2 x float>, ptr %p1092    %2 = fadd <2 x float> %1, %11093    %3 = call <2 x i32> @test_v2i32_v2f32_helper(<2 x float> %2)1094    %4 = add <2 x i32> %3, %31095    store <2 x i32> %4, ptr %q1096    ret void1097}1098 1099declare <2 x i32> @test_v2i32_v4i16_helper(<4 x i16> %p)1100define void @test_v2i32_v4i16(ptr %p, ptr %q) {1101; SOFT-LABEL: test_v2i32_v4i16:1102; SOFT:       @ %bb.0:1103; SOFT-NEXT:    .save {r4, lr}1104; SOFT-NEXT:    push {r4, lr}1105; SOFT-NEXT:    vldr d16, [r0]1106; SOFT-NEXT:    mov r4, r11107; SOFT-NEXT:    vrev64.16 d16, d161108; SOFT-NEXT:    vadd.i16 d16, d16, d161109; SOFT-NEXT:    vrev64.16 d16, d161110; SOFT-NEXT:    vmov r1, r0, d161111; SOFT-NEXT:    bl test_v2i32_v4i16_helper1112; SOFT-NEXT:    vmov d16, r1, r01113; SOFT-NEXT:    vrev64.32 d16, d161114; SOFT-NEXT:    vadd.i32 d16, d16, d161115; SOFT-NEXT:    vrev64.32 d16, d161116; SOFT-NEXT:    vstr d16, [r4]1117; SOFT-NEXT:    pop {r4, pc}1118;1119; HARD-LABEL: test_v2i32_v4i16:1120; HARD:       @ %bb.0:1121; HARD-NEXT:    .save {r4, lr}1122; HARD-NEXT:    push {r4, lr}1123; HARD-NEXT:    vldr d16, [r0]1124; HARD-NEXT:    mov r4, r11125; HARD-NEXT:    vrev64.16 d16, d161126; HARD-NEXT:    vadd.i16 d16, d16, d161127; HARD-NEXT:    vrev64.16 d0, d161128; HARD-NEXT:    bl test_v2i32_v4i16_helper1129; HARD-NEXT:    vrev64.32 d16, d01130; HARD-NEXT:    vadd.i32 d16, d16, d161131; HARD-NEXT:    vrev64.32 d16, d161132; HARD-NEXT:    vstr d16, [r4]1133; HARD-NEXT:    pop {r4, pc}1134    %1 = load <4 x i16>, ptr %p1135    %2 = add <4 x i16> %1, %11136    %3 = call <2 x i32> @test_v2i32_v4i16_helper(<4 x i16> %2)1137    %4 = add <2 x i32> %3, %31138    store <2 x i32> %4, ptr %q1139    ret void1140}1141 1142declare <2 x i32> @test_v2i32_v8i8_helper(<8 x i8> %p)1143define void @test_v2i32_v8i8(ptr %p, ptr %q) {1144; SOFT-LABEL: test_v2i32_v8i8:1145; SOFT:       @ %bb.0:1146; SOFT-NEXT:    .save {r4, lr}1147; SOFT-NEXT:    push {r4, lr}1148; SOFT-NEXT:    vldr d16, [r0]1149; SOFT-NEXT:    mov r4, r11150; SOFT-NEXT:    vrev64.8 d16, d161151; SOFT-NEXT:    vadd.i8 d16, d16, d161152; SOFT-NEXT:    vrev64.8 d16, d161153; SOFT-NEXT:    vmov r1, r0, d161154; SOFT-NEXT:    bl test_v2i32_v8i8_helper1155; SOFT-NEXT:    vmov d16, r1, r01156; SOFT-NEXT:    vrev64.32 d16, d161157; SOFT-NEXT:    vadd.i32 d16, d16, d161158; SOFT-NEXT:    vrev64.32 d16, d161159; SOFT-NEXT:    vstr d16, [r4]1160; SOFT-NEXT:    pop {r4, pc}1161;1162; HARD-LABEL: test_v2i32_v8i8:1163; HARD:       @ %bb.0:1164; HARD-NEXT:    .save {r4, lr}1165; HARD-NEXT:    push {r4, lr}1166; HARD-NEXT:    vldr d16, [r0]1167; HARD-NEXT:    mov r4, r11168; HARD-NEXT:    vrev64.8 d16, d161169; HARD-NEXT:    vadd.i8 d16, d16, d161170; HARD-NEXT:    vrev64.8 d0, d161171; HARD-NEXT:    bl test_v2i32_v8i8_helper1172; HARD-NEXT:    vrev64.32 d16, d01173; HARD-NEXT:    vadd.i32 d16, d16, d161174; HARD-NEXT:    vrev64.32 d16, d161175; HARD-NEXT:    vstr d16, [r4]1176; HARD-NEXT:    pop {r4, pc}1177    %1 = load <8 x i8>, ptr %p1178    %2 = add <8 x i8> %1, %11179    %3 = call <2 x i32> @test_v2i32_v8i8_helper(<8 x i8> %2)1180    %4 = add <2 x i32> %3, %31181    store <2 x i32> %4, ptr %q1182    ret void1183}1184 1185declare <4 x i16> @test_v4i16_i64_helper(i64 %p)1186define void @test_v4i16_i64(ptr %p, ptr %q) {1187; SOFT-LABEL: test_v4i16_i64:1188; SOFT:       @ %bb.0:1189; SOFT-NEXT:    .save {r4, lr}1190; SOFT-NEXT:    push {r4, lr}1191; SOFT-NEXT:    mov r4, r11192; SOFT-NEXT:    ldrd r0, r1, [r0]1193; SOFT-NEXT:    adds r1, r1, r11194; SOFT-NEXT:    adc r0, r0, r01195; SOFT-NEXT:    bl test_v4i16_i64_helper1196; SOFT-NEXT:    vmov d16, r1, r01197; SOFT-NEXT:    vrev64.16 d16, d161198; SOFT-NEXT:    vadd.i16 d16, d16, d161199; SOFT-NEXT:    vrev64.16 d16, d161200; SOFT-NEXT:    vstr d16, [r4]1201; SOFT-NEXT:    pop {r4, pc}1202;1203; HARD-LABEL: test_v4i16_i64:1204; HARD:       @ %bb.0:1205; HARD-NEXT:    .save {r4, lr}1206; HARD-NEXT:    push {r4, lr}1207; HARD-NEXT:    mov r4, r11208; HARD-NEXT:    ldrd r0, r1, [r0]1209; HARD-NEXT:    adds r1, r1, r11210; HARD-NEXT:    adc r0, r0, r01211; HARD-NEXT:    bl test_v4i16_i64_helper1212; HARD-NEXT:    vrev64.16 d16, d01213; HARD-NEXT:    vadd.i16 d16, d16, d161214; HARD-NEXT:    vrev64.16 d16, d161215; HARD-NEXT:    vstr d16, [r4]1216; HARD-NEXT:    pop {r4, pc}1217    %1 = load i64, ptr %p1218    %2 = add i64 %1, %11219    %3 = call <4 x i16> @test_v4i16_i64_helper(i64 %2)1220    %4 = add <4 x i16> %3, %31221    store <4 x i16> %4, ptr %q1222    ret void1223}1224 1225declare <4 x i16> @test_v4i16_f64_helper(double %p)1226define void @test_v4i16_f64(ptr %p, ptr %q) {1227; SOFT-LABEL: test_v4i16_f64:1228; SOFT:       @ %bb.0:1229; SOFT-NEXT:    .save {r4, lr}1230; SOFT-NEXT:    push {r4, lr}1231; SOFT-NEXT:    vldr d16, [r0]1232; SOFT-NEXT:    mov r4, r11233; SOFT-NEXT:    vadd.f64 d16, d16, d161234; SOFT-NEXT:    vmov r1, r0, d161235; SOFT-NEXT:    bl test_v4i16_f64_helper1236; SOFT-NEXT:    vmov d16, r1, r01237; SOFT-NEXT:    vrev64.16 d16, d161238; SOFT-NEXT:    vadd.i16 d16, d16, d161239; SOFT-NEXT:    vrev64.16 d16, d161240; SOFT-NEXT:    vstr d16, [r4]1241; SOFT-NEXT:    pop {r4, pc}1242;1243; HARD-LABEL: test_v4i16_f64:1244; HARD:       @ %bb.0:1245; HARD-NEXT:    .save {r4, lr}1246; HARD-NEXT:    push {r4, lr}1247; HARD-NEXT:    vldr d16, [r0]1248; HARD-NEXT:    mov r4, r11249; HARD-NEXT:    vadd.f64 d0, d16, d161250; HARD-NEXT:    bl test_v4i16_f64_helper1251; HARD-NEXT:    vrev64.16 d16, d01252; HARD-NEXT:    vadd.i16 d16, d16, d161253; HARD-NEXT:    vrev64.16 d16, d161254; HARD-NEXT:    vstr d16, [r4]1255; HARD-NEXT:    pop {r4, pc}1256    %1 = load double, ptr %p1257    %2 = fadd double %1, %11258    %3 = call <4 x i16> @test_v4i16_f64_helper(double %2)1259    %4 = add <4 x i16> %3, %31260    store <4 x i16> %4, ptr %q1261    ret void1262}1263 1264declare <4 x i16> @test_v4i16_v1i64_helper(<1 x i64> %p)1265define void @test_v4i16_v1i64(ptr %p, ptr %q) {1266; SOFT-LABEL: test_v4i16_v1i64:1267; SOFT:       @ %bb.0:1268; SOFT-NEXT:    .save {r4, lr}1269; SOFT-NEXT:    push {r4, lr}1270; SOFT-NEXT:    vldr d16, [r0]1271; SOFT-NEXT:    mov r4, r11272; SOFT-NEXT:    vadd.i64 d16, d16, d161273; SOFT-NEXT:    vmov r1, r0, d161274; SOFT-NEXT:    bl test_v4i16_v1i64_helper1275; SOFT-NEXT:    vmov d16, r1, r01276; SOFT-NEXT:    vrev64.16 d16, d161277; SOFT-NEXT:    vadd.i16 d16, d16, d161278; SOFT-NEXT:    vrev64.16 d16, d161279; SOFT-NEXT:    vstr d16, [r4]1280; SOFT-NEXT:    pop {r4, pc}1281;1282; HARD-LABEL: test_v4i16_v1i64:1283; HARD:       @ %bb.0:1284; HARD-NEXT:    .save {r4, lr}1285; HARD-NEXT:    push {r4, lr}1286; HARD-NEXT:    vldr d16, [r0]1287; HARD-NEXT:    mov r4, r11288; HARD-NEXT:    vadd.i64 d0, d16, d161289; HARD-NEXT:    bl test_v4i16_v1i64_helper1290; HARD-NEXT:    vrev64.16 d16, d01291; HARD-NEXT:    vadd.i16 d16, d16, d161292; HARD-NEXT:    vrev64.16 d16, d161293; HARD-NEXT:    vstr d16, [r4]1294; HARD-NEXT:    pop {r4, pc}1295    %1 = load <1 x i64>, ptr %p1296    %2 = add <1 x i64> %1, %11297    %3 = call <4 x i16> @test_v4i16_v1i64_helper(<1 x i64> %2)1298    %4 = add <4 x i16> %3, %31299    store <4 x i16> %4, ptr %q1300    ret void1301}1302 1303declare <4 x i16> @test_v4i16_v2f32_helper(<2 x float> %p)1304define void @test_v4i16_v2f32(ptr %p, ptr %q) {1305; SOFT-LABEL: test_v4i16_v2f32:1306; SOFT:       @ %bb.0:1307; SOFT-NEXT:    .save {r4, lr}1308; SOFT-NEXT:    push {r4, lr}1309; SOFT-NEXT:    vldr d16, [r0]1310; SOFT-NEXT:    mov r4, r11311; SOFT-NEXT:    vrev64.32 d16, d161312; SOFT-NEXT:    vadd.f32 d16, d16, d161313; SOFT-NEXT:    vrev64.32 d16, d161314; SOFT-NEXT:    vmov r1, r0, d161315; SOFT-NEXT:    bl test_v4i16_v2f32_helper1316; SOFT-NEXT:    vmov d16, r1, r01317; SOFT-NEXT:    vrev64.16 d16, d161318; SOFT-NEXT:    vadd.i16 d16, d16, d161319; SOFT-NEXT:    vrev64.16 d16, d161320; SOFT-NEXT:    vstr d16, [r4]1321; SOFT-NEXT:    pop {r4, pc}1322;1323; HARD-LABEL: test_v4i16_v2f32:1324; HARD:       @ %bb.0:1325; HARD-NEXT:    .save {r4, lr}1326; HARD-NEXT:    push {r4, lr}1327; HARD-NEXT:    vldr d16, [r0]1328; HARD-NEXT:    mov r4, r11329; HARD-NEXT:    vrev64.32 d16, d161330; HARD-NEXT:    vadd.f32 d16, d16, d161331; HARD-NEXT:    vrev64.32 d0, d161332; HARD-NEXT:    bl test_v4i16_v2f32_helper1333; HARD-NEXT:    vrev64.16 d16, d01334; HARD-NEXT:    vadd.i16 d16, d16, d161335; HARD-NEXT:    vrev64.16 d16, d161336; HARD-NEXT:    vstr d16, [r4]1337; HARD-NEXT:    pop {r4, pc}1338    %1 = load <2 x float>, ptr %p1339    %2 = fadd <2 x float> %1, %11340    %3 = call <4 x i16> @test_v4i16_v2f32_helper(<2 x float> %2)1341    %4 = add <4 x i16> %3, %31342    store <4 x i16> %4, ptr %q1343    ret void1344}1345 1346declare <4 x i16> @test_v4i16_v2i32_helper(<2 x i32> %p)1347define void @test_v4i16_v2i32(ptr %p, ptr %q) {1348; SOFT-LABEL: test_v4i16_v2i32:1349; SOFT:       @ %bb.0:1350; SOFT-NEXT:    .save {r4, lr}1351; SOFT-NEXT:    push {r4, lr}1352; SOFT-NEXT:    vldr d16, [r0]1353; SOFT-NEXT:    mov r4, r11354; SOFT-NEXT:    vrev64.32 d16, d161355; SOFT-NEXT:    vadd.i32 d16, d16, d161356; SOFT-NEXT:    vrev64.32 d16, d161357; SOFT-NEXT:    vmov r1, r0, d161358; SOFT-NEXT:    bl test_v4i16_v2i32_helper1359; SOFT-NEXT:    vmov d16, r1, r01360; SOFT-NEXT:    vrev64.16 d16, d161361; SOFT-NEXT:    vadd.i16 d16, d16, d161362; SOFT-NEXT:    vrev64.16 d16, d161363; SOFT-NEXT:    vstr d16, [r4]1364; SOFT-NEXT:    pop {r4, pc}1365;1366; HARD-LABEL: test_v4i16_v2i32:1367; HARD:       @ %bb.0:1368; HARD-NEXT:    .save {r4, lr}1369; HARD-NEXT:    push {r4, lr}1370; HARD-NEXT:    vldr d16, [r0]1371; HARD-NEXT:    mov r4, r11372; HARD-NEXT:    vrev64.32 d16, d161373; HARD-NEXT:    vadd.i32 d16, d16, d161374; HARD-NEXT:    vrev64.32 d0, d161375; HARD-NEXT:    bl test_v4i16_v2i32_helper1376; HARD-NEXT:    vrev64.16 d16, d01377; HARD-NEXT:    vadd.i16 d16, d16, d161378; HARD-NEXT:    vrev64.16 d16, d161379; HARD-NEXT:    vstr d16, [r4]1380; HARD-NEXT:    pop {r4, pc}1381    %1 = load <2 x i32>, ptr %p1382    %2 = add <2 x i32> %1, %11383    %3 = call <4 x i16> @test_v4i16_v2i32_helper(<2 x i32> %2)1384    %4 = add <4 x i16> %3, %31385    store <4 x i16> %4, ptr %q1386    ret void1387}1388 1389declare <4 x i16> @test_v4i16_v8i8_helper(<8 x i8> %p)1390define void @test_v4i16_v8i8(ptr %p, ptr %q) {1391; SOFT-LABEL: test_v4i16_v8i8:1392; SOFT:       @ %bb.0:1393; SOFT-NEXT:    .save {r4, lr}1394; SOFT-NEXT:    push {r4, lr}1395; SOFT-NEXT:    vldr d16, [r0]1396; SOFT-NEXT:    mov r4, r11397; SOFT-NEXT:    vrev64.8 d16, d161398; SOFT-NEXT:    vadd.i8 d16, d16, d161399; SOFT-NEXT:    vrev64.8 d16, d161400; SOFT-NEXT:    vmov r1, r0, d161401; SOFT-NEXT:    bl test_v4i16_v8i8_helper1402; SOFT-NEXT:    vmov d16, r1, r01403; SOFT-NEXT:    vrev64.16 d16, d161404; SOFT-NEXT:    vadd.i16 d16, d16, d161405; SOFT-NEXT:    vrev64.16 d16, d161406; SOFT-NEXT:    vstr d16, [r4]1407; SOFT-NEXT:    pop {r4, pc}1408;1409; HARD-LABEL: test_v4i16_v8i8:1410; HARD:       @ %bb.0:1411; HARD-NEXT:    .save {r4, lr}1412; HARD-NEXT:    push {r4, lr}1413; HARD-NEXT:    vldr d16, [r0]1414; HARD-NEXT:    mov r4, r11415; HARD-NEXT:    vrev64.8 d16, d161416; HARD-NEXT:    vadd.i8 d16, d16, d161417; HARD-NEXT:    vrev64.8 d0, d161418; HARD-NEXT:    bl test_v4i16_v8i8_helper1419; HARD-NEXT:    vrev64.16 d16, d01420; HARD-NEXT:    vadd.i16 d16, d16, d161421; HARD-NEXT:    vrev64.16 d16, d161422; HARD-NEXT:    vstr d16, [r4]1423; HARD-NEXT:    pop {r4, pc}1424    %1 = load <8 x i8>, ptr %p1425    %2 = add <8 x i8> %1, %11426    %3 = call <4 x i16> @test_v4i16_v8i8_helper(<8 x i8> %2)1427    %4 = add <4 x i16> %3, %31428    store <4 x i16> %4, ptr %q1429    ret void1430}1431 1432declare <8 x i8> @test_v8i8_i64_helper(i64 %p)1433define void @test_v8i8_i64(ptr %p, ptr %q) {1434; SOFT-LABEL: test_v8i8_i64:1435; SOFT:       @ %bb.0:1436; SOFT-NEXT:    .save {r4, lr}1437; SOFT-NEXT:    push {r4, lr}1438; SOFT-NEXT:    mov r4, r11439; SOFT-NEXT:    ldrd r0, r1, [r0]1440; SOFT-NEXT:    adds r1, r1, r11441; SOFT-NEXT:    adc r0, r0, r01442; SOFT-NEXT:    bl test_v8i8_i64_helper1443; SOFT-NEXT:    vmov d16, r1, r01444; SOFT-NEXT:    vrev64.8 d16, d161445; SOFT-NEXT:    vadd.i8 d16, d16, d161446; SOFT-NEXT:    vrev64.8 d16, d161447; SOFT-NEXT:    vstr d16, [r4]1448; SOFT-NEXT:    pop {r4, pc}1449;1450; HARD-LABEL: test_v8i8_i64:1451; HARD:       @ %bb.0:1452; HARD-NEXT:    .save {r4, lr}1453; HARD-NEXT:    push {r4, lr}1454; HARD-NEXT:    mov r4, r11455; HARD-NEXT:    ldrd r0, r1, [r0]1456; HARD-NEXT:    adds r1, r1, r11457; HARD-NEXT:    adc r0, r0, r01458; HARD-NEXT:    bl test_v8i8_i64_helper1459; HARD-NEXT:    vrev64.8 d16, d01460; HARD-NEXT:    vadd.i8 d16, d16, d161461; HARD-NEXT:    vrev64.8 d16, d161462; HARD-NEXT:    vstr d16, [r4]1463; HARD-NEXT:    pop {r4, pc}1464    %1 = load i64, ptr %p1465    %2 = add i64 %1, %11466    %3 = call <8 x i8> @test_v8i8_i64_helper(i64 %2)1467    %4 = add <8 x i8> %3, %31468    store <8 x i8> %4, ptr %q1469    ret void1470}1471 1472declare <8 x i8> @test_v8i8_f64_helper(double %p)1473define void @test_v8i8_f64(ptr %p, ptr %q) {1474; SOFT-LABEL: test_v8i8_f64:1475; SOFT:       @ %bb.0:1476; SOFT-NEXT:    .save {r4, lr}1477; SOFT-NEXT:    push {r4, lr}1478; SOFT-NEXT:    vldr d16, [r0]1479; SOFT-NEXT:    mov r4, r11480; SOFT-NEXT:    vadd.f64 d16, d16, d161481; SOFT-NEXT:    vmov r1, r0, d161482; SOFT-NEXT:    bl test_v8i8_f64_helper1483; SOFT-NEXT:    vmov d16, r1, r01484; SOFT-NEXT:    vrev64.8 d16, d161485; SOFT-NEXT:    vadd.i8 d16, d16, d161486; SOFT-NEXT:    vrev64.8 d16, d161487; SOFT-NEXT:    vstr d16, [r4]1488; SOFT-NEXT:    pop {r4, pc}1489;1490; HARD-LABEL: test_v8i8_f64:1491; HARD:       @ %bb.0:1492; HARD-NEXT:    .save {r4, lr}1493; HARD-NEXT:    push {r4, lr}1494; HARD-NEXT:    vldr d16, [r0]1495; HARD-NEXT:    mov r4, r11496; HARD-NEXT:    vadd.f64 d0, d16, d161497; HARD-NEXT:    bl test_v8i8_f64_helper1498; HARD-NEXT:    vrev64.8 d16, d01499; HARD-NEXT:    vadd.i8 d16, d16, d161500; HARD-NEXT:    vrev64.8 d16, d161501; HARD-NEXT:    vstr d16, [r4]1502; HARD-NEXT:    pop {r4, pc}1503    %1 = load double, ptr %p1504    %2 = fadd double %1, %11505    %3 = call <8 x i8> @test_v8i8_f64_helper(double %2)1506    %4 = add <8 x i8> %3, %31507    store <8 x i8> %4, ptr %q1508    ret void1509}1510 1511declare <8 x i8> @test_v8i8_v1i64_helper(<1 x i64> %p)1512define void @test_v8i8_v1i64(ptr %p, ptr %q) {1513; SOFT-LABEL: test_v8i8_v1i64:1514; SOFT:       @ %bb.0:1515; SOFT-NEXT:    .save {r4, lr}1516; SOFT-NEXT:    push {r4, lr}1517; SOFT-NEXT:    vldr d16, [r0]1518; SOFT-NEXT:    mov r4, r11519; SOFT-NEXT:    vadd.i64 d16, d16, d161520; SOFT-NEXT:    vmov r1, r0, d161521; SOFT-NEXT:    bl test_v8i8_v1i64_helper1522; SOFT-NEXT:    vmov d16, r1, r01523; SOFT-NEXT:    vrev64.8 d16, d161524; SOFT-NEXT:    vadd.i8 d16, d16, d161525; SOFT-NEXT:    vrev64.8 d16, d161526; SOFT-NEXT:    vstr d16, [r4]1527; SOFT-NEXT:    pop {r4, pc}1528;1529; HARD-LABEL: test_v8i8_v1i64:1530; HARD:       @ %bb.0:1531; HARD-NEXT:    .save {r4, lr}1532; HARD-NEXT:    push {r4, lr}1533; HARD-NEXT:    vldr d16, [r0]1534; HARD-NEXT:    mov r4, r11535; HARD-NEXT:    vadd.i64 d0, d16, d161536; HARD-NEXT:    bl test_v8i8_v1i64_helper1537; HARD-NEXT:    vrev64.8 d16, d01538; HARD-NEXT:    vadd.i8 d16, d16, d161539; HARD-NEXT:    vrev64.8 d16, d161540; HARD-NEXT:    vstr d16, [r4]1541; HARD-NEXT:    pop {r4, pc}1542    %1 = load <1 x i64>, ptr %p1543    %2 = add <1 x i64> %1, %11544    %3 = call <8 x i8> @test_v8i8_v1i64_helper(<1 x i64> %2)1545    %4 = add <8 x i8> %3, %31546    store <8 x i8> %4, ptr %q1547    ret void1548}1549 1550declare <8 x i8> @test_v8i8_v2f32_helper(<2 x float> %p)1551define void @test_v8i8_v2f32(ptr %p, ptr %q) {1552; SOFT-LABEL: test_v8i8_v2f32:1553; SOFT:       @ %bb.0:1554; SOFT-NEXT:    .save {r4, lr}1555; SOFT-NEXT:    push {r4, lr}1556; SOFT-NEXT:    vldr d16, [r0]1557; SOFT-NEXT:    mov r4, r11558; SOFT-NEXT:    vrev64.32 d16, d161559; SOFT-NEXT:    vadd.f32 d16, d16, d161560; SOFT-NEXT:    vrev64.32 d16, d161561; SOFT-NEXT:    vmov r1, r0, d161562; SOFT-NEXT:    bl test_v8i8_v2f32_helper1563; SOFT-NEXT:    vmov d16, r1, r01564; SOFT-NEXT:    vrev64.8 d16, d161565; SOFT-NEXT:    vadd.i8 d16, d16, d161566; SOFT-NEXT:    vrev64.8 d16, d161567; SOFT-NEXT:    vstr d16, [r4]1568; SOFT-NEXT:    pop {r4, pc}1569;1570; HARD-LABEL: test_v8i8_v2f32:1571; HARD:       @ %bb.0:1572; HARD-NEXT:    .save {r4, lr}1573; HARD-NEXT:    push {r4, lr}1574; HARD-NEXT:    vldr d16, [r0]1575; HARD-NEXT:    mov r4, r11576; HARD-NEXT:    vrev64.32 d16, d161577; HARD-NEXT:    vadd.f32 d16, d16, d161578; HARD-NEXT:    vrev64.32 d0, d161579; HARD-NEXT:    bl test_v8i8_v2f32_helper1580; HARD-NEXT:    vrev64.8 d16, d01581; HARD-NEXT:    vadd.i8 d16, d16, d161582; HARD-NEXT:    vrev64.8 d16, d161583; HARD-NEXT:    vstr d16, [r4]1584; HARD-NEXT:    pop {r4, pc}1585    %1 = load <2 x float>, ptr %p1586    %2 = fadd <2 x float> %1, %11587    %3 = call <8 x i8> @test_v8i8_v2f32_helper(<2 x float> %2)1588    %4 = add <8 x i8> %3, %31589    store <8 x i8> %4, ptr %q1590    ret void1591}1592 1593declare <8 x i8> @test_v8i8_v2i32_helper(<2 x i32> %p)1594define void @test_v8i8_v2i32(ptr %p, ptr %q) {1595; SOFT-LABEL: test_v8i8_v2i32:1596; SOFT:       @ %bb.0:1597; SOFT-NEXT:    .save {r4, lr}1598; SOFT-NEXT:    push {r4, lr}1599; SOFT-NEXT:    vldr d16, [r0]1600; SOFT-NEXT:    mov r4, r11601; SOFT-NEXT:    vrev64.32 d16, d161602; SOFT-NEXT:    vadd.i32 d16, d16, d161603; SOFT-NEXT:    vrev64.32 d16, d161604; SOFT-NEXT:    vmov r1, r0, d161605; SOFT-NEXT:    bl test_v8i8_v2i32_helper1606; SOFT-NEXT:    vmov d16, r1, r01607; SOFT-NEXT:    vrev64.8 d16, d161608; SOFT-NEXT:    vadd.i8 d16, d16, d161609; SOFT-NEXT:    vrev64.8 d16, d161610; SOFT-NEXT:    vstr d16, [r4]1611; SOFT-NEXT:    pop {r4, pc}1612;1613; HARD-LABEL: test_v8i8_v2i32:1614; HARD:       @ %bb.0:1615; HARD-NEXT:    .save {r4, lr}1616; HARD-NEXT:    push {r4, lr}1617; HARD-NEXT:    vldr d16, [r0]1618; HARD-NEXT:    mov r4, r11619; HARD-NEXT:    vrev64.32 d16, d161620; HARD-NEXT:    vadd.i32 d16, d16, d161621; HARD-NEXT:    vrev64.32 d0, d161622; HARD-NEXT:    bl test_v8i8_v2i32_helper1623; HARD-NEXT:    vrev64.8 d16, d01624; HARD-NEXT:    vadd.i8 d16, d16, d161625; HARD-NEXT:    vrev64.8 d16, d161626; HARD-NEXT:    vstr d16, [r4]1627; HARD-NEXT:    pop {r4, pc}1628    %1 = load <2 x i32>, ptr %p1629    %2 = add <2 x i32> %1, %11630    %3 = call <8 x i8> @test_v8i8_v2i32_helper(<2 x i32> %2)1631    %4 = add <8 x i8> %3, %31632    store <8 x i8> %4, ptr %q1633    ret void1634}1635 1636declare <8 x i8> @test_v8i8_v4i16_helper(<4 x i16> %p)1637define void @test_v8i8_v4i16(ptr %p, ptr %q) {1638; SOFT-LABEL: test_v8i8_v4i16:1639; SOFT:       @ %bb.0:1640; SOFT-NEXT:    .save {r4, lr}1641; SOFT-NEXT:    push {r4, lr}1642; SOFT-NEXT:    vldr d16, [r0]1643; SOFT-NEXT:    mov r4, r11644; SOFT-NEXT:    vrev64.16 d16, d161645; SOFT-NEXT:    vadd.i16 d16, d16, d161646; SOFT-NEXT:    vrev64.16 d16, d161647; SOFT-NEXT:    vmov r1, r0, d161648; SOFT-NEXT:    bl test_v8i8_v4i16_helper1649; SOFT-NEXT:    vmov d16, r1, r01650; SOFT-NEXT:    vrev64.8 d16, d161651; SOFT-NEXT:    vadd.i8 d16, d16, d161652; SOFT-NEXT:    vrev64.8 d16, d161653; SOFT-NEXT:    vstr d16, [r4]1654; SOFT-NEXT:    pop {r4, pc}1655;1656; HARD-LABEL: test_v8i8_v4i16:1657; HARD:       @ %bb.0:1658; HARD-NEXT:    .save {r4, lr}1659; HARD-NEXT:    push {r4, lr}1660; HARD-NEXT:    vldr d16, [r0]1661; HARD-NEXT:    mov r4, r11662; HARD-NEXT:    vrev64.16 d16, d161663; HARD-NEXT:    vadd.i16 d16, d16, d161664; HARD-NEXT:    vrev64.16 d0, d161665; HARD-NEXT:    bl test_v8i8_v4i16_helper1666; HARD-NEXT:    vrev64.8 d16, d01667; HARD-NEXT:    vadd.i8 d16, d16, d161668; HARD-NEXT:    vrev64.8 d16, d161669; HARD-NEXT:    vstr d16, [r4]1670; HARD-NEXT:    pop {r4, pc}1671    %1 = load <4 x i16>, ptr %p1672    %2 = add <4 x i16> %1, %11673    %3 = call <8 x i8> @test_v8i8_v4i16_helper(<4 x i16> %2)1674    %4 = add <8 x i8> %3, %31675    store <8 x i8> %4, ptr %q1676    ret void1677}1678 1679declare fp128 @test_f128_v2f64_helper(<2 x double> %p)1680define void @test_f128_v2f64(ptr %p, ptr %q) {1681; SOFT-LABEL: test_f128_v2f64:1682; SOFT:       @ %bb.0:1683; SOFT-NEXT:    .save {r4, lr}1684; SOFT-NEXT:    push {r4, lr}1685; SOFT-NEXT:    .pad #161686; SOFT-NEXT:    sub sp, sp, #161687; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]1688; SOFT-NEXT:    mov r4, r11689; SOFT-NEXT:    vadd.f64 d18, d16, d161690; SOFT-NEXT:    vadd.f64 d16, d17, d171691; SOFT-NEXT:    vmov r1, r0, d181692; SOFT-NEXT:    vmov r3, r2, d161693; SOFT-NEXT:    bl test_f128_v2f64_helper1694; SOFT-NEXT:    stm sp, {r0, r1, r2, r3}1695; SOFT-NEXT:    bl __addtf31696; SOFT-NEXT:    stm r4, {r0, r1, r2, r3}1697; SOFT-NEXT:    add sp, sp, #161698; SOFT-NEXT:    pop {r4, pc}1699;1700; HARD-LABEL: test_f128_v2f64:1701; HARD:       @ %bb.0:1702; HARD-NEXT:    .save {r4, lr}1703; HARD-NEXT:    push {r4, lr}1704; HARD-NEXT:    .pad #161705; HARD-NEXT:    sub sp, sp, #161706; HARD-NEXT:    vld1.64 {d16, d17}, [r0]1707; HARD-NEXT:    mov r4, r11708; HARD-NEXT:    vadd.f64 d1, d17, d171709; HARD-NEXT:    vadd.f64 d0, d16, d161710; HARD-NEXT:    bl test_f128_v2f64_helper1711; HARD-NEXT:    stm sp, {r0, r1, r2, r3}1712; HARD-NEXT:    bl __addtf31713; HARD-NEXT:    stm r4, {r0, r1, r2, r3}1714; HARD-NEXT:    add sp, sp, #161715; HARD-NEXT:    pop {r4, pc}1716    %1 = load <2 x double>, ptr %p1717    %2 = fadd <2 x double> %1, %11718    %3 = call fp128 @test_f128_v2f64_helper(<2 x double> %2)1719    %4 = fadd fp128 %3, %31720    store fp128 %4, ptr %q1721    ret void1722}1723 1724declare fp128 @test_f128_v2i64_helper(<2 x i64> %p)1725define void @test_f128_v2i64(ptr %p, ptr %q) {1726; SOFT-LABEL: test_f128_v2i64:1727; SOFT:       @ %bb.0:1728; SOFT-NEXT:    .save {r4, lr}1729; SOFT-NEXT:    push {r4, lr}1730; SOFT-NEXT:    .pad #161731; SOFT-NEXT:    sub sp, sp, #161732; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]1733; SOFT-NEXT:    mov r4, r11734; SOFT-NEXT:    vadd.i64 q8, q8, q81735; SOFT-NEXT:    vmov r1, r0, d161736; SOFT-NEXT:    vmov r3, r2, d171737; SOFT-NEXT:    bl test_f128_v2i64_helper1738; SOFT-NEXT:    stm sp, {r0, r1, r2, r3}1739; SOFT-NEXT:    bl __addtf31740; SOFT-NEXT:    stm r4, {r0, r1, r2, r3}1741; SOFT-NEXT:    add sp, sp, #161742; SOFT-NEXT:    pop {r4, pc}1743;1744; HARD-LABEL: test_f128_v2i64:1745; HARD:       @ %bb.0:1746; HARD-NEXT:    .save {r4, lr}1747; HARD-NEXT:    push {r4, lr}1748; HARD-NEXT:    .pad #161749; HARD-NEXT:    sub sp, sp, #161750; HARD-NEXT:    vld1.64 {d16, d17}, [r0]1751; HARD-NEXT:    mov r4, r11752; HARD-NEXT:    vadd.i64 q0, q8, q81753; HARD-NEXT:    bl test_f128_v2i64_helper1754; HARD-NEXT:    stm sp, {r0, r1, r2, r3}1755; HARD-NEXT:    bl __addtf31756; HARD-NEXT:    stm r4, {r0, r1, r2, r3}1757; HARD-NEXT:    add sp, sp, #161758; HARD-NEXT:    pop {r4, pc}1759    %1 = load <2 x i64>, ptr %p1760    %2 = add <2 x i64> %1, %11761    %3 = call fp128 @test_f128_v2i64_helper(<2 x i64> %2)1762    %4 = fadd fp128 %3, %31763    store fp128 %4, ptr %q1764    ret void1765}1766 1767declare fp128 @test_f128_v4f32_helper(<4 x float> %p)1768define void @test_f128_v4f32(ptr %p, ptr %q) {1769; SOFT-LABEL: test_f128_v4f32:1770; SOFT:       @ %bb.0:1771; SOFT-NEXT:    .save {r4, lr}1772; SOFT-NEXT:    push {r4, lr}1773; SOFT-NEXT:    .pad #161774; SOFT-NEXT:    sub sp, sp, #161775; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]1776; SOFT-NEXT:    mov r4, r11777; SOFT-NEXT:    vrev64.32 q8, q81778; SOFT-NEXT:    vadd.f32 q8, q8, q81779; SOFT-NEXT:    vrev64.32 q8, q81780; SOFT-NEXT:    vmov r1, r0, d161781; SOFT-NEXT:    vmov r3, r2, d171782; SOFT-NEXT:    bl test_f128_v4f32_helper1783; SOFT-NEXT:    stm sp, {r0, r1, r2, r3}1784; SOFT-NEXT:    bl __addtf31785; SOFT-NEXT:    stm r4, {r0, r1, r2, r3}1786; SOFT-NEXT:    add sp, sp, #161787; SOFT-NEXT:    pop {r4, pc}1788;1789; HARD-LABEL: test_f128_v4f32:1790; HARD:       @ %bb.0:1791; HARD-NEXT:    .save {r4, lr}1792; HARD-NEXT:    push {r4, lr}1793; HARD-NEXT:    .pad #161794; HARD-NEXT:    sub sp, sp, #161795; HARD-NEXT:    vld1.64 {d16, d17}, [r0]1796; HARD-NEXT:    mov r4, r11797; HARD-NEXT:    vrev64.32 q8, q81798; HARD-NEXT:    vadd.f32 q8, q8, q81799; HARD-NEXT:    vrev64.32 q0, q81800; HARD-NEXT:    bl test_f128_v4f32_helper1801; HARD-NEXT:    stm sp, {r0, r1, r2, r3}1802; HARD-NEXT:    bl __addtf31803; HARD-NEXT:    stm r4, {r0, r1, r2, r3}1804; HARD-NEXT:    add sp, sp, #161805; HARD-NEXT:    pop {r4, pc}1806    %1 = load <4 x float>, ptr %p1807    %2 = fadd <4 x float> %1, %11808    %3 = call fp128 @test_f128_v4f32_helper(<4 x float> %2)1809    %4 = fadd fp128 %3, %31810    store fp128 %4, ptr %q1811    ret void1812}1813 1814declare fp128 @test_f128_v4i32_helper(<4 x i32> %p)1815define void @test_f128_v4i32(ptr %p, ptr %q) {1816; SOFT-LABEL: test_f128_v4i32:1817; SOFT:       @ %bb.0:1818; SOFT-NEXT:    .save {r4, lr}1819; SOFT-NEXT:    push {r4, lr}1820; SOFT-NEXT:    .pad #161821; SOFT-NEXT:    sub sp, sp, #161822; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]1823; SOFT-NEXT:    mov r4, r11824; SOFT-NEXT:    vrev64.32 q8, q81825; SOFT-NEXT:    vadd.i32 q8, q8, q81826; SOFT-NEXT:    vrev64.32 q8, q81827; SOFT-NEXT:    vmov r1, r0, d161828; SOFT-NEXT:    vmov r3, r2, d171829; SOFT-NEXT:    bl test_f128_v4i32_helper1830; SOFT-NEXT:    stm sp, {r0, r1, r2, r3}1831; SOFT-NEXT:    bl __addtf31832; SOFT-NEXT:    stm r4, {r0, r1, r2, r3}1833; SOFT-NEXT:    add sp, sp, #161834; SOFT-NEXT:    pop {r4, pc}1835;1836; HARD-LABEL: test_f128_v4i32:1837; HARD:       @ %bb.0:1838; HARD-NEXT:    .save {r4, lr}1839; HARD-NEXT:    push {r4, lr}1840; HARD-NEXT:    .pad #161841; HARD-NEXT:    sub sp, sp, #161842; HARD-NEXT:    vld1.64 {d16, d17}, [r0]1843; HARD-NEXT:    mov r4, r11844; HARD-NEXT:    vrev64.32 q8, q81845; HARD-NEXT:    vadd.i32 q8, q8, q81846; HARD-NEXT:    vrev64.32 q0, q81847; HARD-NEXT:    bl test_f128_v4i32_helper1848; HARD-NEXT:    stm sp, {r0, r1, r2, r3}1849; HARD-NEXT:    bl __addtf31850; HARD-NEXT:    stm r4, {r0, r1, r2, r3}1851; HARD-NEXT:    add sp, sp, #161852; HARD-NEXT:    pop {r4, pc}1853    %1 = load <4 x i32>, ptr %p1854    %2 = add <4 x i32> %1, %11855    %3 = call fp128 @test_f128_v4i32_helper(<4 x i32> %2)1856    %4 = fadd fp128 %3, %31857    store fp128 %4, ptr %q1858    ret void1859}1860 1861declare fp128 @test_f128_v8i16_helper(<8 x i16> %p)1862define void @test_f128_v8i16(ptr %p, ptr %q) {1863; SOFT-LABEL: test_f128_v8i16:1864; SOFT:       @ %bb.0:1865; SOFT-NEXT:    .save {r4, lr}1866; SOFT-NEXT:    push {r4, lr}1867; SOFT-NEXT:    .pad #161868; SOFT-NEXT:    sub sp, sp, #161869; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]1870; SOFT-NEXT:    mov r4, r11871; SOFT-NEXT:    vrev64.16 q8, q81872; SOFT-NEXT:    vadd.i16 q8, q8, q81873; SOFT-NEXT:    vrev64.16 q8, q81874; SOFT-NEXT:    vmov r1, r0, d161875; SOFT-NEXT:    vmov r3, r2, d171876; SOFT-NEXT:    bl test_f128_v8i16_helper1877; SOFT-NEXT:    stm sp, {r0, r1, r2, r3}1878; SOFT-NEXT:    bl __addtf31879; SOFT-NEXT:    stm r4, {r0, r1, r2, r3}1880; SOFT-NEXT:    add sp, sp, #161881; SOFT-NEXT:    pop {r4, pc}1882;1883; HARD-LABEL: test_f128_v8i16:1884; HARD:       @ %bb.0:1885; HARD-NEXT:    .save {r4, lr}1886; HARD-NEXT:    push {r4, lr}1887; HARD-NEXT:    .pad #161888; HARD-NEXT:    sub sp, sp, #161889; HARD-NEXT:    vld1.64 {d16, d17}, [r0]1890; HARD-NEXT:    mov r4, r11891; HARD-NEXT:    vrev64.16 q8, q81892; HARD-NEXT:    vadd.i16 q8, q8, q81893; HARD-NEXT:    vrev64.16 q0, q81894; HARD-NEXT:    bl test_f128_v8i16_helper1895; HARD-NEXT:    stm sp, {r0, r1, r2, r3}1896; HARD-NEXT:    bl __addtf31897; HARD-NEXT:    stm r4, {r0, r1, r2, r3}1898; HARD-NEXT:    add sp, sp, #161899; HARD-NEXT:    pop {r4, pc}1900    %1 = load <8 x i16>, ptr %p1901    %2 = add <8 x i16> %1, %11902    %3 = call fp128 @test_f128_v8i16_helper(<8 x i16> %2)1903    %4 = fadd fp128 %3, %31904    store fp128 %4, ptr %q1905    ret void1906}1907 1908declare fp128 @test_f128_v16i8_helper(<16 x i8> %p)1909define void @test_f128_v16i8(ptr %p, ptr %q) {1910; SOFT-LABEL: test_f128_v16i8:1911; SOFT:       @ %bb.0:1912; SOFT-NEXT:    .save {r4, lr}1913; SOFT-NEXT:    push {r4, lr}1914; SOFT-NEXT:    .pad #161915; SOFT-NEXT:    sub sp, sp, #161916; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]1917; SOFT-NEXT:    mov r4, r11918; SOFT-NEXT:    vrev64.8 q8, q81919; SOFT-NEXT:    vadd.i8 q8, q8, q81920; SOFT-NEXT:    vrev64.8 q8, q81921; SOFT-NEXT:    vmov r1, r0, d161922; SOFT-NEXT:    vmov r3, r2, d171923; SOFT-NEXT:    bl test_f128_v16i8_helper1924; SOFT-NEXT:    stm sp, {r0, r1, r2, r3}1925; SOFT-NEXT:    bl __addtf31926; SOFT-NEXT:    stm r4, {r0, r1, r2, r3}1927; SOFT-NEXT:    add sp, sp, #161928; SOFT-NEXT:    pop {r4, pc}1929;1930; HARD-LABEL: test_f128_v16i8:1931; HARD:       @ %bb.0:1932; HARD-NEXT:    .save {r4, lr}1933; HARD-NEXT:    push {r4, lr}1934; HARD-NEXT:    .pad #161935; HARD-NEXT:    sub sp, sp, #161936; HARD-NEXT:    vld1.64 {d16, d17}, [r0]1937; HARD-NEXT:    mov r4, r11938; HARD-NEXT:    vrev64.8 q8, q81939; HARD-NEXT:    vadd.i8 q8, q8, q81940; HARD-NEXT:    vrev64.8 q0, q81941; HARD-NEXT:    bl test_f128_v16i8_helper1942; HARD-NEXT:    stm sp, {r0, r1, r2, r3}1943; HARD-NEXT:    bl __addtf31944; HARD-NEXT:    stm r4, {r0, r1, r2, r3}1945; HARD-NEXT:    add sp, sp, #161946; HARD-NEXT:    pop {r4, pc}1947    %1 = load <16 x i8>, ptr %p1948    %2 = add <16 x i8> %1, %11949    %3 = call fp128 @test_f128_v16i8_helper(<16 x i8> %2)1950    %4 = fadd fp128 %3, %31951    store fp128 %4, ptr %q1952    ret void1953}1954 1955declare <2 x double> @test_v2f64_f128_helper(fp128 %p)1956define void @test_v2f64_f128(ptr %p, ptr %q) {1957; SOFT-LABEL: test_v2f64_f128:1958; SOFT:       @ %bb.0:1959; SOFT-NEXT:    .save {r4, r5, r11, lr}1960; SOFT-NEXT:    push {r4, r5, r11, lr}1961; SOFT-NEXT:    .pad #161962; SOFT-NEXT:    sub sp, sp, #161963; SOFT-NEXT:    ldr r4, [r0]1964; SOFT-NEXT:    mov r5, r11965; SOFT-NEXT:    ldmib r0, {r1, r2, r3}1966; SOFT-NEXT:    mov r0, r41967; SOFT-NEXT:    str r4, [sp]1968; SOFT-NEXT:    stmib sp, {r1, r2, r3}1969; SOFT-NEXT:    bl __addtf31970; SOFT-NEXT:    bl test_v2f64_f128_helper1971; SOFT-NEXT:    vmov d16, r3, r21972; SOFT-NEXT:    vmov d17, r1, r01973; SOFT-NEXT:    vadd.f64 d19, d16, d161974; SOFT-NEXT:    vadd.f64 d18, d17, d171975; SOFT-NEXT:    vst1.64 {d18, d19}, [r5]1976; SOFT-NEXT:    add sp, sp, #161977; SOFT-NEXT:    pop {r4, r5, r11, pc}1978;1979; HARD-LABEL: test_v2f64_f128:1980; HARD:       @ %bb.0:1981; HARD-NEXT:    .save {r4, r5, r11, lr}1982; HARD-NEXT:    push {r4, r5, r11, lr}1983; HARD-NEXT:    .pad #161984; HARD-NEXT:    sub sp, sp, #161985; HARD-NEXT:    ldr r4, [r0]1986; HARD-NEXT:    mov r5, r11987; HARD-NEXT:    ldmib r0, {r1, r2, r3}1988; HARD-NEXT:    mov r0, r41989; HARD-NEXT:    str r4, [sp]1990; HARD-NEXT:    stmib sp, {r1, r2, r3}1991; HARD-NEXT:    bl __addtf31992; HARD-NEXT:    bl test_v2f64_f128_helper1993; HARD-NEXT:    vadd.f64 d17, d1, d11994; HARD-NEXT:    vadd.f64 d16, d0, d01995; HARD-NEXT:    vst1.64 {d16, d17}, [r5]1996; HARD-NEXT:    add sp, sp, #161997; HARD-NEXT:    pop {r4, r5, r11, pc}1998    %1 = load fp128, ptr %p1999    %2 = fadd fp128 %1, %12000    %3 = call <2 x double> @test_v2f64_f128_helper(fp128 %2)2001    %4 = fadd <2 x double> %3, %32002    store <2 x double> %4, ptr %q2003    ret void2004 2005}2006 2007declare <2 x double> @test_v2f64_v2i64_helper(<2 x i64> %p)2008define void @test_v2f64_v2i64(ptr %p, ptr %q) {2009; SOFT-LABEL: test_v2f64_v2i64:2010; SOFT:       @ %bb.0:2011; SOFT-NEXT:    .save {r4, lr}2012; SOFT-NEXT:    push {r4, lr}2013; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]2014; SOFT-NEXT:    mov r4, r12015; SOFT-NEXT:    vadd.i64 q8, q8, q82016; SOFT-NEXT:    vmov r1, r0, d162017; SOFT-NEXT:    vmov r3, r2, d172018; SOFT-NEXT:    bl test_v2f64_v2i64_helper2019; SOFT-NEXT:    vmov d16, r3, r22020; SOFT-NEXT:    vmov d17, r1, r02021; SOFT-NEXT:    vadd.f64 d19, d16, d162022; SOFT-NEXT:    vadd.f64 d18, d17, d172023; SOFT-NEXT:    vst1.64 {d18, d19}, [r4]2024; SOFT-NEXT:    pop {r4, pc}2025;2026; HARD-LABEL: test_v2f64_v2i64:2027; HARD:       @ %bb.0:2028; HARD-NEXT:    .save {r4, lr}2029; HARD-NEXT:    push {r4, lr}2030; HARD-NEXT:    vld1.64 {d16, d17}, [r0]2031; HARD-NEXT:    mov r4, r12032; HARD-NEXT:    vadd.i64 q0, q8, q82033; HARD-NEXT:    bl test_v2f64_v2i64_helper2034; HARD-NEXT:    vadd.f64 d17, d1, d12035; HARD-NEXT:    vadd.f64 d16, d0, d02036; HARD-NEXT:    vst1.64 {d16, d17}, [r4]2037; HARD-NEXT:    pop {r4, pc}2038    %1 = load <2 x i64>, ptr %p2039    %2 = add <2 x i64> %1, %12040    %3 = call <2 x double> @test_v2f64_v2i64_helper(<2 x i64> %2)2041    %4 = fadd <2 x double> %3, %32042    store <2 x double> %4, ptr %q2043    ret void2044}2045 2046declare <2 x double> @test_v2f64_v4f32_helper(<4 x float> %p)2047define void @test_v2f64_v4f32(ptr %p, ptr %q) {2048; SOFT-LABEL: test_v2f64_v4f32:2049; SOFT:       @ %bb.0:2050; SOFT-NEXT:    .save {r4, lr}2051; SOFT-NEXT:    push {r4, lr}2052; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]2053; SOFT-NEXT:    mov r4, r12054; SOFT-NEXT:    vrev64.32 q8, q82055; SOFT-NEXT:    vadd.f32 q8, q8, q82056; SOFT-NEXT:    vrev64.32 q8, q82057; SOFT-NEXT:    vmov r1, r0, d162058; SOFT-NEXT:    vmov r3, r2, d172059; SOFT-NEXT:    bl test_v2f64_v4f32_helper2060; SOFT-NEXT:    vmov d16, r3, r22061; SOFT-NEXT:    vmov d17, r1, r02062; SOFT-NEXT:    vadd.f64 d19, d16, d162063; SOFT-NEXT:    vadd.f64 d18, d17, d172064; SOFT-NEXT:    vst1.64 {d18, d19}, [r4]2065; SOFT-NEXT:    pop {r4, pc}2066;2067; HARD-LABEL: test_v2f64_v4f32:2068; HARD:       @ %bb.0:2069; HARD-NEXT:    .save {r4, lr}2070; HARD-NEXT:    push {r4, lr}2071; HARD-NEXT:    vld1.64 {d16, d17}, [r0]2072; HARD-NEXT:    mov r4, r12073; HARD-NEXT:    vrev64.32 q8, q82074; HARD-NEXT:    vadd.f32 q8, q8, q82075; HARD-NEXT:    vrev64.32 q0, q82076; HARD-NEXT:    bl test_v2f64_v4f32_helper2077; HARD-NEXT:    vadd.f64 d17, d1, d12078; HARD-NEXT:    vadd.f64 d16, d0, d02079; HARD-NEXT:    vst1.64 {d16, d17}, [r4]2080; HARD-NEXT:    pop {r4, pc}2081    %1 = load <4 x float>, ptr %p2082    %2 = fadd <4 x float> %1, %12083    %3 = call <2 x double> @test_v2f64_v4f32_helper(<4 x float> %2)2084    %4 = fadd <2 x double> %3, %32085    store <2 x double> %4, ptr %q2086    ret void2087}2088 2089declare <2 x double> @test_v2f64_v4i32_helper(<4 x i32> %p)2090define void @test_v2f64_v4i32(ptr %p, ptr %q) {2091; SOFT-LABEL: test_v2f64_v4i32:2092; SOFT:       @ %bb.0:2093; SOFT-NEXT:    .save {r4, lr}2094; SOFT-NEXT:    push {r4, lr}2095; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]2096; SOFT-NEXT:    mov r4, r12097; SOFT-NEXT:    vrev64.32 q8, q82098; SOFT-NEXT:    vadd.i32 q8, q8, q82099; SOFT-NEXT:    vrev64.32 q8, q82100; SOFT-NEXT:    vmov r1, r0, d162101; SOFT-NEXT:    vmov r3, r2, d172102; SOFT-NEXT:    bl test_v2f64_v4i32_helper2103; SOFT-NEXT:    vmov d16, r3, r22104; SOFT-NEXT:    vmov d17, r1, r02105; SOFT-NEXT:    vadd.f64 d19, d16, d162106; SOFT-NEXT:    vadd.f64 d18, d17, d172107; SOFT-NEXT:    vst1.64 {d18, d19}, [r4]2108; SOFT-NEXT:    pop {r4, pc}2109;2110; HARD-LABEL: test_v2f64_v4i32:2111; HARD:       @ %bb.0:2112; HARD-NEXT:    .save {r4, lr}2113; HARD-NEXT:    push {r4, lr}2114; HARD-NEXT:    vld1.64 {d16, d17}, [r0]2115; HARD-NEXT:    mov r4, r12116; HARD-NEXT:    vrev64.32 q8, q82117; HARD-NEXT:    vadd.i32 q8, q8, q82118; HARD-NEXT:    vrev64.32 q0, q82119; HARD-NEXT:    bl test_v2f64_v4i32_helper2120; HARD-NEXT:    vadd.f64 d17, d1, d12121; HARD-NEXT:    vadd.f64 d16, d0, d02122; HARD-NEXT:    vst1.64 {d16, d17}, [r4]2123; HARD-NEXT:    pop {r4, pc}2124    %1 = load <4 x i32>, ptr %p2125    %2 = add <4 x i32> %1, %12126    %3 = call <2 x double> @test_v2f64_v4i32_helper(<4 x i32> %2)2127    %4 = fadd <2 x double> %3, %32128    store <2 x double> %4, ptr %q2129    ret void2130}2131 2132declare <2 x double> @test_v2f64_v8i16_helper(<8 x i16> %p)2133define void @test_v2f64_v8i16(ptr %p, ptr %q) {2134; SOFT-LABEL: test_v2f64_v8i16:2135; SOFT:       @ %bb.0:2136; SOFT-NEXT:    .save {r4, lr}2137; SOFT-NEXT:    push {r4, lr}2138; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]2139; SOFT-NEXT:    mov r4, r12140; SOFT-NEXT:    vrev64.16 q8, q82141; SOFT-NEXT:    vadd.i16 q8, q8, q82142; SOFT-NEXT:    vrev64.16 q8, q82143; SOFT-NEXT:    vmov r1, r0, d162144; SOFT-NEXT:    vmov r3, r2, d172145; SOFT-NEXT:    bl test_v2f64_v8i16_helper2146; SOFT-NEXT:    vmov d16, r3, r22147; SOFT-NEXT:    vmov d17, r1, r02148; SOFT-NEXT:    vadd.f64 d19, d16, d162149; SOFT-NEXT:    vadd.f64 d18, d17, d172150; SOFT-NEXT:    vst1.64 {d18, d19}, [r4]2151; SOFT-NEXT:    pop {r4, pc}2152;2153; HARD-LABEL: test_v2f64_v8i16:2154; HARD:       @ %bb.0:2155; HARD-NEXT:    .save {r4, lr}2156; HARD-NEXT:    push {r4, lr}2157; HARD-NEXT:    vld1.64 {d16, d17}, [r0]2158; HARD-NEXT:    mov r4, r12159; HARD-NEXT:    vrev64.16 q8, q82160; HARD-NEXT:    vadd.i16 q8, q8, q82161; HARD-NEXT:    vrev64.16 q0, q82162; HARD-NEXT:    bl test_v2f64_v8i16_helper2163; HARD-NEXT:    vadd.f64 d17, d1, d12164; HARD-NEXT:    vadd.f64 d16, d0, d02165; HARD-NEXT:    vst1.64 {d16, d17}, [r4]2166; HARD-NEXT:    pop {r4, pc}2167    %1 = load <8 x i16>, ptr %p2168    %2 = add <8 x i16> %1, %12169    %3 = call <2 x double> @test_v2f64_v8i16_helper(<8 x i16> %2)2170    %4 = fadd <2 x double> %3, %32171    store <2 x double> %4, ptr %q2172    ret void2173}2174 2175declare <2 x double> @test_v2f64_v16i8_helper(<16 x i8> %p)2176define void @test_v2f64_v16i8(ptr %p, ptr %q) {2177; SOFT-LABEL: test_v2f64_v16i8:2178; SOFT:       @ %bb.0:2179; SOFT-NEXT:    .save {r4, lr}2180; SOFT-NEXT:    push {r4, lr}2181; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]2182; SOFT-NEXT:    mov r4, r12183; SOFT-NEXT:    vrev64.8 q8, q82184; SOFT-NEXT:    vadd.i8 q8, q8, q82185; SOFT-NEXT:    vrev64.8 q8, q82186; SOFT-NEXT:    vmov r1, r0, d162187; SOFT-NEXT:    vmov r3, r2, d172188; SOFT-NEXT:    bl test_v2f64_v16i8_helper2189; SOFT-NEXT:    vmov d16, r3, r22190; SOFT-NEXT:    vmov d17, r1, r02191; SOFT-NEXT:    vadd.f64 d19, d16, d162192; SOFT-NEXT:    vadd.f64 d18, d17, d172193; SOFT-NEXT:    vst1.64 {d18, d19}, [r4]2194; SOFT-NEXT:    pop {r4, pc}2195;2196; HARD-LABEL: test_v2f64_v16i8:2197; HARD:       @ %bb.0:2198; HARD-NEXT:    .save {r4, lr}2199; HARD-NEXT:    push {r4, lr}2200; HARD-NEXT:    vld1.64 {d16, d17}, [r0]2201; HARD-NEXT:    mov r4, r12202; HARD-NEXT:    vrev64.8 q8, q82203; HARD-NEXT:    vadd.i8 q8, q8, q82204; HARD-NEXT:    vrev64.8 q0, q82205; HARD-NEXT:    bl test_v2f64_v16i8_helper2206; HARD-NEXT:    vadd.f64 d17, d1, d12207; HARD-NEXT:    vadd.f64 d16, d0, d02208; HARD-NEXT:    vst1.64 {d16, d17}, [r4]2209; HARD-NEXT:    pop {r4, pc}2210    %1 = load <16 x i8>, ptr %p2211    %2 = add <16 x i8> %1, %12212    %3 = call <2 x double> @test_v2f64_v16i8_helper(<16 x i8> %2)2213    %4 = fadd <2 x double> %3, %32214    store <2 x double> %4, ptr %q2215    ret void2216}2217 2218declare <2 x i64> @test_v2i64_f128_helper(fp128 %p)2219define void @test_v2i64_f128(ptr %p, ptr %q) {2220; SOFT-LABEL: test_v2i64_f128:2221; SOFT:       @ %bb.0:2222; SOFT-NEXT:    .save {r4, r5, r11, lr}2223; SOFT-NEXT:    push {r4, r5, r11, lr}2224; SOFT-NEXT:    .pad #162225; SOFT-NEXT:    sub sp, sp, #162226; SOFT-NEXT:    ldr r4, [r0]2227; SOFT-NEXT:    mov r5, r12228; SOFT-NEXT:    ldmib r0, {r1, r2, r3}2229; SOFT-NEXT:    mov r0, r42230; SOFT-NEXT:    str r4, [sp]2231; SOFT-NEXT:    stmib sp, {r1, r2, r3}2232; SOFT-NEXT:    bl __addtf32233; SOFT-NEXT:    bl test_v2i64_f128_helper2234; SOFT-NEXT:    vmov d17, r3, r22235; SOFT-NEXT:    vmov d16, r1, r02236; SOFT-NEXT:    vadd.i64 q8, q8, q82237; SOFT-NEXT:    vst1.64 {d16, d17}, [r5]2238; SOFT-NEXT:    add sp, sp, #162239; SOFT-NEXT:    pop {r4, r5, r11, pc}2240;2241; HARD-LABEL: test_v2i64_f128:2242; HARD:       @ %bb.0:2243; HARD-NEXT:    .save {r4, r5, r11, lr}2244; HARD-NEXT:    push {r4, r5, r11, lr}2245; HARD-NEXT:    .pad #162246; HARD-NEXT:    sub sp, sp, #162247; HARD-NEXT:    ldr r4, [r0]2248; HARD-NEXT:    mov r5, r12249; HARD-NEXT:    ldmib r0, {r1, r2, r3}2250; HARD-NEXT:    mov r0, r42251; HARD-NEXT:    str r4, [sp]2252; HARD-NEXT:    stmib sp, {r1, r2, r3}2253; HARD-NEXT:    bl __addtf32254; HARD-NEXT:    bl test_v2i64_f128_helper2255; HARD-NEXT:    vadd.i64 q8, q0, q02256; HARD-NEXT:    vst1.64 {d16, d17}, [r5]2257; HARD-NEXT:    add sp, sp, #162258; HARD-NEXT:    pop {r4, r5, r11, pc}2259    %1 = load fp128, ptr %p2260    %2 = fadd fp128 %1, %12261    %3 = call <2 x i64> @test_v2i64_f128_helper(fp128 %2)2262    %4 = add <2 x i64> %3, %32263    store <2 x i64> %4, ptr %q2264    ret void2265}2266 2267declare <2 x i64> @test_v2i64_v2f64_helper(<2 x double> %p)2268define void @test_v2i64_v2f64(ptr %p, ptr %q) {2269; SOFT-LABEL: test_v2i64_v2f64:2270; SOFT:       @ %bb.0:2271; SOFT-NEXT:    .save {r4, lr}2272; SOFT-NEXT:    push {r4, lr}2273; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]2274; SOFT-NEXT:    mov r4, r12275; SOFT-NEXT:    vadd.f64 d18, d16, d162276; SOFT-NEXT:    vadd.f64 d16, d17, d172277; SOFT-NEXT:    vmov r1, r0, d182278; SOFT-NEXT:    vmov r3, r2, d162279; SOFT-NEXT:    bl test_v2i64_v2f64_helper2280; SOFT-NEXT:    vmov d17, r3, r22281; SOFT-NEXT:    vmov d16, r1, r02282; SOFT-NEXT:    vadd.i64 q8, q8, q82283; SOFT-NEXT:    vst1.64 {d16, d17}, [r4]2284; SOFT-NEXT:    pop {r4, pc}2285;2286; HARD-LABEL: test_v2i64_v2f64:2287; HARD:       @ %bb.0:2288; HARD-NEXT:    .save {r4, lr}2289; HARD-NEXT:    push {r4, lr}2290; HARD-NEXT:    vld1.64 {d16, d17}, [r0]2291; HARD-NEXT:    mov r4, r12292; HARD-NEXT:    vadd.f64 d1, d17, d172293; HARD-NEXT:    vadd.f64 d0, d16, d162294; HARD-NEXT:    bl test_v2i64_v2f64_helper2295; HARD-NEXT:    vadd.i64 q8, q0, q02296; HARD-NEXT:    vst1.64 {d16, d17}, [r4]2297; HARD-NEXT:    pop {r4, pc}2298    %1 = load <2 x double>, ptr %p2299    %2 = fadd <2 x double> %1, %12300    %3 = call <2 x i64> @test_v2i64_v2f64_helper(<2 x double> %2)2301    %4 = add <2 x i64> %3, %32302    store <2 x i64> %4, ptr %q2303    ret void2304}2305 2306declare <2 x i64> @test_v2i64_v4f32_helper(<4 x float> %p)2307define void @test_v2i64_v4f32(ptr %p, ptr %q) {2308; SOFT-LABEL: test_v2i64_v4f32:2309; SOFT:       @ %bb.0:2310; SOFT-NEXT:    .save {r4, lr}2311; SOFT-NEXT:    push {r4, lr}2312; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]2313; SOFT-NEXT:    mov r4, r12314; SOFT-NEXT:    vrev64.32 q8, q82315; SOFT-NEXT:    vadd.f32 q8, q8, q82316; SOFT-NEXT:    vrev64.32 q8, q82317; SOFT-NEXT:    vmov r1, r0, d162318; SOFT-NEXT:    vmov r3, r2, d172319; SOFT-NEXT:    bl test_v2i64_v4f32_helper2320; SOFT-NEXT:    vmov d17, r3, r22321; SOFT-NEXT:    vmov d16, r1, r02322; SOFT-NEXT:    vadd.i64 q8, q8, q82323; SOFT-NEXT:    vst1.64 {d16, d17}, [r4]2324; SOFT-NEXT:    pop {r4, pc}2325;2326; HARD-LABEL: test_v2i64_v4f32:2327; HARD:       @ %bb.0:2328; HARD-NEXT:    .save {r4, lr}2329; HARD-NEXT:    push {r4, lr}2330; HARD-NEXT:    vld1.64 {d16, d17}, [r0]2331; HARD-NEXT:    mov r4, r12332; HARD-NEXT:    vrev64.32 q8, q82333; HARD-NEXT:    vadd.f32 q8, q8, q82334; HARD-NEXT:    vrev64.32 q0, q82335; HARD-NEXT:    bl test_v2i64_v4f32_helper2336; HARD-NEXT:    vadd.i64 q8, q0, q02337; HARD-NEXT:    vst1.64 {d16, d17}, [r4]2338; HARD-NEXT:    pop {r4, pc}2339    %1 = load <4 x float>, ptr %p2340    %2 = fadd <4 x float> %1, %12341    %3 = call <2 x i64> @test_v2i64_v4f32_helper(<4 x float> %2)2342    %4 = add <2 x i64> %3, %32343    store <2 x i64> %4, ptr %q2344    ret void2345}2346 2347declare <2 x i64> @test_v2i64_v4i32_helper(<4 x i32> %p)2348define void @test_v2i64_v4i32(ptr %p, ptr %q) {2349; SOFT-LABEL: test_v2i64_v4i32:2350; SOFT:       @ %bb.0:2351; SOFT-NEXT:    .save {r4, lr}2352; SOFT-NEXT:    push {r4, lr}2353; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]2354; SOFT-NEXT:    mov r4, r12355; SOFT-NEXT:    vrev64.32 q8, q82356; SOFT-NEXT:    vadd.i32 q8, q8, q82357; SOFT-NEXT:    vrev64.32 q8, q82358; SOFT-NEXT:    vmov r1, r0, d162359; SOFT-NEXT:    vmov r3, r2, d172360; SOFT-NEXT:    bl test_v2i64_v4i32_helper2361; SOFT-NEXT:    vmov d17, r3, r22362; SOFT-NEXT:    vmov d16, r1, r02363; SOFT-NEXT:    vadd.i64 q8, q8, q82364; SOFT-NEXT:    vst1.64 {d16, d17}, [r4]2365; SOFT-NEXT:    pop {r4, pc}2366;2367; HARD-LABEL: test_v2i64_v4i32:2368; HARD:       @ %bb.0:2369; HARD-NEXT:    .save {r4, lr}2370; HARD-NEXT:    push {r4, lr}2371; HARD-NEXT:    vld1.64 {d16, d17}, [r0]2372; HARD-NEXT:    mov r4, r12373; HARD-NEXT:    vrev64.32 q8, q82374; HARD-NEXT:    vadd.i32 q8, q8, q82375; HARD-NEXT:    vrev64.32 q0, q82376; HARD-NEXT:    bl test_v2i64_v4i32_helper2377; HARD-NEXT:    vadd.i64 q8, q0, q02378; HARD-NEXT:    vst1.64 {d16, d17}, [r4]2379; HARD-NEXT:    pop {r4, pc}2380    %1 = load <4 x i32>, ptr %p2381    %2 = add <4 x i32> %1, %12382    %3 = call <2 x i64> @test_v2i64_v4i32_helper(<4 x i32> %2)2383    %4 = add <2 x i64> %3, %32384    store <2 x i64> %4, ptr %q2385    ret void2386}2387 2388declare <2 x i64> @test_v2i64_v8i16_helper(<8 x i16> %p)2389define void @test_v2i64_v8i16(ptr %p, ptr %q) {2390; SOFT-LABEL: test_v2i64_v8i16:2391; SOFT:       @ %bb.0:2392; SOFT-NEXT:    .save {r4, lr}2393; SOFT-NEXT:    push {r4, lr}2394; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]2395; SOFT-NEXT:    mov r4, r12396; SOFT-NEXT:    vrev64.16 q8, q82397; SOFT-NEXT:    vadd.i16 q8, q8, q82398; SOFT-NEXT:    vrev64.16 q8, q82399; SOFT-NEXT:    vmov r1, r0, d162400; SOFT-NEXT:    vmov r3, r2, d172401; SOFT-NEXT:    bl test_v2i64_v8i16_helper2402; SOFT-NEXT:    vmov d17, r3, r22403; SOFT-NEXT:    vmov d16, r1, r02404; SOFT-NEXT:    vadd.i64 q8, q8, q82405; SOFT-NEXT:    vst1.64 {d16, d17}, [r4]2406; SOFT-NEXT:    pop {r4, pc}2407;2408; HARD-LABEL: test_v2i64_v8i16:2409; HARD:       @ %bb.0:2410; HARD-NEXT:    .save {r4, lr}2411; HARD-NEXT:    push {r4, lr}2412; HARD-NEXT:    vld1.64 {d16, d17}, [r0]2413; HARD-NEXT:    mov r4, r12414; HARD-NEXT:    vrev64.16 q8, q82415; HARD-NEXT:    vadd.i16 q8, q8, q82416; HARD-NEXT:    vrev64.16 q0, q82417; HARD-NEXT:    bl test_v2i64_v8i16_helper2418; HARD-NEXT:    vadd.i64 q8, q0, q02419; HARD-NEXT:    vst1.64 {d16, d17}, [r4]2420; HARD-NEXT:    pop {r4, pc}2421    %1 = load <8 x i16>, ptr %p2422    %2 = add <8 x i16> %1, %12423    %3 = call <2 x i64> @test_v2i64_v8i16_helper(<8 x i16> %2)2424    %4 = add <2 x i64> %3, %32425    store <2 x i64> %4, ptr %q2426    ret void2427}2428 2429declare <2 x i64> @test_v2i64_v16i8_helper(<16 x i8> %p)2430define void @test_v2i64_v16i8(ptr %p, ptr %q) {2431; SOFT-LABEL: test_v2i64_v16i8:2432; SOFT:       @ %bb.0:2433; SOFT-NEXT:    .save {r4, lr}2434; SOFT-NEXT:    push {r4, lr}2435; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]2436; SOFT-NEXT:    mov r4, r12437; SOFT-NEXT:    vrev64.8 q8, q82438; SOFT-NEXT:    vadd.i8 q8, q8, q82439; SOFT-NEXT:    vrev64.8 q8, q82440; SOFT-NEXT:    vmov r1, r0, d162441; SOFT-NEXT:    vmov r3, r2, d172442; SOFT-NEXT:    bl test_v2i64_v16i8_helper2443; SOFT-NEXT:    vmov d17, r3, r22444; SOFT-NEXT:    vmov d16, r1, r02445; SOFT-NEXT:    vadd.i64 q8, q8, q82446; SOFT-NEXT:    vst1.64 {d16, d17}, [r4]2447; SOFT-NEXT:    pop {r4, pc}2448;2449; HARD-LABEL: test_v2i64_v16i8:2450; HARD:       @ %bb.0:2451; HARD-NEXT:    .save {r4, lr}2452; HARD-NEXT:    push {r4, lr}2453; HARD-NEXT:    vld1.64 {d16, d17}, [r0]2454; HARD-NEXT:    mov r4, r12455; HARD-NEXT:    vrev64.8 q8, q82456; HARD-NEXT:    vadd.i8 q8, q8, q82457; HARD-NEXT:    vrev64.8 q0, q82458; HARD-NEXT:    bl test_v2i64_v16i8_helper2459; HARD-NEXT:    vadd.i64 q8, q0, q02460; HARD-NEXT:    vst1.64 {d16, d17}, [r4]2461; HARD-NEXT:    pop {r4, pc}2462    %1 = load <16 x i8>, ptr %p2463    %2 = add <16 x i8> %1, %12464    %3 = call <2 x i64> @test_v2i64_v16i8_helper(<16 x i8> %2)2465    %4 = add <2 x i64> %3, %32466    store <2 x i64> %4, ptr %q2467    ret void2468}2469 2470declare <4 x float> @test_v4f32_f128_helper(fp128 %p)2471define void @test_v4f32_f128(ptr %p, ptr %q) {2472; SOFT-LABEL: test_v4f32_f128:2473; SOFT:       @ %bb.0:2474; SOFT-NEXT:    .save {r4, r5, r11, lr}2475; SOFT-NEXT:    push {r4, r5, r11, lr}2476; SOFT-NEXT:    .pad #162477; SOFT-NEXT:    sub sp, sp, #162478; SOFT-NEXT:    ldr r4, [r0]2479; SOFT-NEXT:    mov r5, r12480; SOFT-NEXT:    ldmib r0, {r1, r2, r3}2481; SOFT-NEXT:    mov r0, r42482; SOFT-NEXT:    str r4, [sp]2483; SOFT-NEXT:    stmib sp, {r1, r2, r3}2484; SOFT-NEXT:    bl __addtf32485; SOFT-NEXT:    bl test_v4f32_f128_helper2486; SOFT-NEXT:    vmov d17, r3, r22487; SOFT-NEXT:    vmov d16, r1, r02488; SOFT-NEXT:    vrev64.32 q8, q82489; SOFT-NEXT:    vadd.f32 q8, q8, q82490; SOFT-NEXT:    vrev64.32 q8, q82491; SOFT-NEXT:    vst1.64 {d16, d17}, [r5]2492; SOFT-NEXT:    add sp, sp, #162493; SOFT-NEXT:    pop {r4, r5, r11, pc}2494;2495; HARD-LABEL: test_v4f32_f128:2496; HARD:       @ %bb.0:2497; HARD-NEXT:    .save {r4, r5, r11, lr}2498; HARD-NEXT:    push {r4, r5, r11, lr}2499; HARD-NEXT:    .pad #162500; HARD-NEXT:    sub sp, sp, #162501; HARD-NEXT:    ldr r4, [r0]2502; HARD-NEXT:    mov r5, r12503; HARD-NEXT:    ldmib r0, {r1, r2, r3}2504; HARD-NEXT:    mov r0, r42505; HARD-NEXT:    str r4, [sp]2506; HARD-NEXT:    stmib sp, {r1, r2, r3}2507; HARD-NEXT:    bl __addtf32508; HARD-NEXT:    bl test_v4f32_f128_helper2509; HARD-NEXT:    vrev64.32 q8, q02510; HARD-NEXT:    vadd.f32 q8, q8, q82511; HARD-NEXT:    vrev64.32 q8, q82512; HARD-NEXT:    vst1.64 {d16, d17}, [r5]2513; HARD-NEXT:    add sp, sp, #162514; HARD-NEXT:    pop {r4, r5, r11, pc}2515    %1 = load fp128, ptr %p2516    %2 = fadd fp128 %1, %12517    %3 = call <4 x float> @test_v4f32_f128_helper(fp128 %2)2518    %4 = fadd <4 x float> %3, %32519    store <4 x float> %4, ptr %q2520    ret void2521}2522 2523declare <4 x float> @test_v4f32_v2f64_helper(<2 x double> %p)2524define void @test_v4f32_v2f64(ptr %p, ptr %q) {2525; SOFT-LABEL: test_v4f32_v2f64:2526; SOFT:       @ %bb.0:2527; SOFT-NEXT:    .save {r4, lr}2528; SOFT-NEXT:    push {r4, lr}2529; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]2530; SOFT-NEXT:    mov r4, r12531; SOFT-NEXT:    vadd.f64 d18, d16, d162532; SOFT-NEXT:    vadd.f64 d16, d17, d172533; SOFT-NEXT:    vmov r1, r0, d182534; SOFT-NEXT:    vmov r3, r2, d162535; SOFT-NEXT:    bl test_v4f32_v2f64_helper2536; SOFT-NEXT:    vmov d17, r3, r22537; SOFT-NEXT:    vmov d16, r1, r02538; SOFT-NEXT:    vrev64.32 q8, q82539; SOFT-NEXT:    vadd.f32 q8, q8, q82540; SOFT-NEXT:    vrev64.32 q8, q82541; SOFT-NEXT:    vst1.64 {d16, d17}, [r4]2542; SOFT-NEXT:    pop {r4, pc}2543;2544; HARD-LABEL: test_v4f32_v2f64:2545; HARD:       @ %bb.0:2546; HARD-NEXT:    .save {r4, lr}2547; HARD-NEXT:    push {r4, lr}2548; HARD-NEXT:    vld1.64 {d16, d17}, [r0]2549; HARD-NEXT:    mov r4, r12550; HARD-NEXT:    vadd.f64 d1, d17, d172551; HARD-NEXT:    vadd.f64 d0, d16, d162552; HARD-NEXT:    bl test_v4f32_v2f64_helper2553; HARD-NEXT:    vrev64.32 q8, q02554; HARD-NEXT:    vadd.f32 q8, q8, q82555; HARD-NEXT:    vrev64.32 q8, q82556; HARD-NEXT:    vst1.64 {d16, d17}, [r4]2557; HARD-NEXT:    pop {r4, pc}2558    %1 = load <2 x double>, ptr %p2559    %2 = fadd <2 x double> %1, %12560    %3 = call <4 x float> @test_v4f32_v2f64_helper(<2 x double> %2)2561    %4 = fadd <4 x float> %3, %32562    store <4 x float> %4, ptr %q2563    ret void2564}2565 2566declare <4 x float> @test_v4f32_v2i64_helper(<2 x i64> %p)2567define void @test_v4f32_v2i64(ptr %p, ptr %q) {2568; SOFT-LABEL: test_v4f32_v2i64:2569; SOFT:       @ %bb.0:2570; SOFT-NEXT:    .save {r4, lr}2571; SOFT-NEXT:    push {r4, lr}2572; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]2573; SOFT-NEXT:    mov r4, r12574; SOFT-NEXT:    vadd.i64 q8, q8, q82575; SOFT-NEXT:    vmov r1, r0, d162576; SOFT-NEXT:    vmov r3, r2, d172577; SOFT-NEXT:    bl test_v4f32_v2i64_helper2578; SOFT-NEXT:    vmov d17, r3, r22579; SOFT-NEXT:    vmov d16, r1, r02580; SOFT-NEXT:    vrev64.32 q8, q82581; SOFT-NEXT:    vadd.f32 q8, q8, q82582; SOFT-NEXT:    vrev64.32 q8, q82583; SOFT-NEXT:    vst1.64 {d16, d17}, [r4]2584; SOFT-NEXT:    pop {r4, pc}2585;2586; HARD-LABEL: test_v4f32_v2i64:2587; HARD:       @ %bb.0:2588; HARD-NEXT:    .save {r4, lr}2589; HARD-NEXT:    push {r4, lr}2590; HARD-NEXT:    vld1.64 {d16, d17}, [r0]2591; HARD-NEXT:    mov r4, r12592; HARD-NEXT:    vadd.i64 q0, q8, q82593; HARD-NEXT:    bl test_v4f32_v2i64_helper2594; HARD-NEXT:    vrev64.32 q8, q02595; HARD-NEXT:    vadd.f32 q8, q8, q82596; HARD-NEXT:    vrev64.32 q8, q82597; HARD-NEXT:    vst1.64 {d16, d17}, [r4]2598; HARD-NEXT:    pop {r4, pc}2599    %1 = load <2 x i64>, ptr %p2600    %2 = add <2 x i64> %1, %12601    %3 = call <4 x float> @test_v4f32_v2i64_helper(<2 x i64> %2)2602    %4 = fadd <4 x float> %3, %32603    store <4 x float> %4, ptr %q2604    ret void2605}2606 2607declare <4 x float> @test_v4f32_v4i32_helper(<4 x i32> %p)2608define void @test_v4f32_v4i32(ptr %p, ptr %q) {2609; SOFT-LABEL: test_v4f32_v4i32:2610; SOFT:       @ %bb.0:2611; SOFT-NEXT:    .save {r4, lr}2612; SOFT-NEXT:    push {r4, lr}2613; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]2614; SOFT-NEXT:    mov r4, r12615; SOFT-NEXT:    vrev64.32 q8, q82616; SOFT-NEXT:    vadd.i32 q8, q8, q82617; SOFT-NEXT:    vrev64.32 q8, q82618; SOFT-NEXT:    vmov r1, r0, d162619; SOFT-NEXT:    vmov r3, r2, d172620; SOFT-NEXT:    bl test_v4f32_v4i32_helper2621; SOFT-NEXT:    vmov d17, r3, r22622; SOFT-NEXT:    vmov d16, r1, r02623; SOFT-NEXT:    vrev64.32 q8, q82624; SOFT-NEXT:    vadd.f32 q8, q8, q82625; SOFT-NEXT:    vrev64.32 q8, q82626; SOFT-NEXT:    vst1.64 {d16, d17}, [r4]2627; SOFT-NEXT:    pop {r4, pc}2628;2629; HARD-LABEL: test_v4f32_v4i32:2630; HARD:       @ %bb.0:2631; HARD-NEXT:    .save {r4, lr}2632; HARD-NEXT:    push {r4, lr}2633; HARD-NEXT:    vld1.64 {d16, d17}, [r0]2634; HARD-NEXT:    mov r4, r12635; HARD-NEXT:    vrev64.32 q8, q82636; HARD-NEXT:    vadd.i32 q8, q8, q82637; HARD-NEXT:    vrev64.32 q0, q82638; HARD-NEXT:    bl test_v4f32_v4i32_helper2639; HARD-NEXT:    vrev64.32 q8, q02640; HARD-NEXT:    vadd.f32 q8, q8, q82641; HARD-NEXT:    vrev64.32 q8, q82642; HARD-NEXT:    vst1.64 {d16, d17}, [r4]2643; HARD-NEXT:    pop {r4, pc}2644    %1 = load <4 x i32>, ptr %p2645    %2 = add <4 x i32> %1, %12646    %3 = call <4 x float> @test_v4f32_v4i32_helper(<4 x i32> %2)2647    %4 = fadd <4 x float> %3, %32648    store <4 x float> %4, ptr %q2649    ret void2650}2651 2652declare <4 x float> @test_v4f32_v8i16_helper(<8 x i16> %p)2653define void @test_v4f32_v8i16(ptr %p, ptr %q) {2654; SOFT-LABEL: test_v4f32_v8i16:2655; SOFT:       @ %bb.0:2656; SOFT-NEXT:    .save {r4, lr}2657; SOFT-NEXT:    push {r4, lr}2658; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]2659; SOFT-NEXT:    mov r4, r12660; SOFT-NEXT:    vrev64.16 q8, q82661; SOFT-NEXT:    vadd.i16 q8, q8, q82662; SOFT-NEXT:    vrev64.16 q8, q82663; SOFT-NEXT:    vmov r1, r0, d162664; SOFT-NEXT:    vmov r3, r2, d172665; SOFT-NEXT:    bl test_v4f32_v8i16_helper2666; SOFT-NEXT:    vmov d17, r3, r22667; SOFT-NEXT:    vmov d16, r1, r02668; SOFT-NEXT:    vrev64.32 q8, q82669; SOFT-NEXT:    vadd.f32 q8, q8, q82670; SOFT-NEXT:    vrev64.32 q8, q82671; SOFT-NEXT:    vst1.64 {d16, d17}, [r4]2672; SOFT-NEXT:    pop {r4, pc}2673;2674; HARD-LABEL: test_v4f32_v8i16:2675; HARD:       @ %bb.0:2676; HARD-NEXT:    .save {r4, lr}2677; HARD-NEXT:    push {r4, lr}2678; HARD-NEXT:    vld1.64 {d16, d17}, [r0]2679; HARD-NEXT:    mov r4, r12680; HARD-NEXT:    vrev64.16 q8, q82681; HARD-NEXT:    vadd.i16 q8, q8, q82682; HARD-NEXT:    vrev64.16 q0, q82683; HARD-NEXT:    bl test_v4f32_v8i16_helper2684; HARD-NEXT:    vrev64.32 q8, q02685; HARD-NEXT:    vadd.f32 q8, q8, q82686; HARD-NEXT:    vrev64.32 q8, q82687; HARD-NEXT:    vst1.64 {d16, d17}, [r4]2688; HARD-NEXT:    pop {r4, pc}2689    %1 = load <8 x i16>, ptr %p2690    %2 = add <8 x i16> %1, %12691    %3 = call <4 x float> @test_v4f32_v8i16_helper(<8 x i16> %2)2692    %4 = fadd <4 x float> %3, %32693    store <4 x float> %4, ptr %q2694    ret void2695}2696 2697declare <4 x float> @test_v4f32_v16i8_helper(<16 x i8> %p)2698define void @test_v4f32_v16i8(ptr %p, ptr %q) {2699; SOFT-LABEL: test_v4f32_v16i8:2700; SOFT:       @ %bb.0:2701; SOFT-NEXT:    .save {r4, lr}2702; SOFT-NEXT:    push {r4, lr}2703; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]2704; SOFT-NEXT:    mov r4, r12705; SOFT-NEXT:    vrev64.8 q8, q82706; SOFT-NEXT:    vadd.i8 q8, q8, q82707; SOFT-NEXT:    vrev64.8 q8, q82708; SOFT-NEXT:    vmov r1, r0, d162709; SOFT-NEXT:    vmov r3, r2, d172710; SOFT-NEXT:    bl test_v4f32_v16i8_helper2711; SOFT-NEXT:    vmov d17, r3, r22712; SOFT-NEXT:    vmov d16, r1, r02713; SOFT-NEXT:    vrev64.32 q8, q82714; SOFT-NEXT:    vadd.f32 q8, q8, q82715; SOFT-NEXT:    vrev64.32 q8, q82716; SOFT-NEXT:    vst1.64 {d16, d17}, [r4]2717; SOFT-NEXT:    pop {r4, pc}2718;2719; HARD-LABEL: test_v4f32_v16i8:2720; HARD:       @ %bb.0:2721; HARD-NEXT:    .save {r4, lr}2722; HARD-NEXT:    push {r4, lr}2723; HARD-NEXT:    vld1.64 {d16, d17}, [r0]2724; HARD-NEXT:    mov r4, r12725; HARD-NEXT:    vrev64.8 q8, q82726; HARD-NEXT:    vadd.i8 q8, q8, q82727; HARD-NEXT:    vrev64.8 q0, q82728; HARD-NEXT:    bl test_v4f32_v16i8_helper2729; HARD-NEXT:    vrev64.32 q8, q02730; HARD-NEXT:    vadd.f32 q8, q8, q82731; HARD-NEXT:    vrev64.32 q8, q82732; HARD-NEXT:    vst1.64 {d16, d17}, [r4]2733; HARD-NEXT:    pop {r4, pc}2734    %1 = load <16 x i8>, ptr %p2735    %2 = add <16 x i8> %1, %12736    %3 = call <4 x float> @test_v4f32_v16i8_helper(<16 x i8> %2)2737    %4 = fadd <4 x float> %3, %32738    store <4 x float> %4, ptr %q2739    ret void2740}2741 2742declare <4 x i32> @test_v4i32_f128_helper(fp128 %p)2743define void @test_v4i32_f128(ptr %p, ptr %q) {2744; SOFT-LABEL: test_v4i32_f128:2745; SOFT:       @ %bb.0:2746; SOFT-NEXT:    .save {r4, r5, r11, lr}2747; SOFT-NEXT:    push {r4, r5, r11, lr}2748; SOFT-NEXT:    .pad #162749; SOFT-NEXT:    sub sp, sp, #162750; SOFT-NEXT:    ldr r4, [r0]2751; SOFT-NEXT:    mov r5, r12752; SOFT-NEXT:    ldmib r0, {r1, r2, r3}2753; SOFT-NEXT:    mov r0, r42754; SOFT-NEXT:    str r4, [sp]2755; SOFT-NEXT:    stmib sp, {r1, r2, r3}2756; SOFT-NEXT:    bl __addtf32757; SOFT-NEXT:    bl test_v4i32_f128_helper2758; SOFT-NEXT:    vmov d17, r3, r22759; SOFT-NEXT:    vmov d16, r1, r02760; SOFT-NEXT:    vrev64.32 q8, q82761; SOFT-NEXT:    vadd.i32 q8, q8, q82762; SOFT-NEXT:    vrev64.32 q8, q82763; SOFT-NEXT:    vst1.64 {d16, d17}, [r5]2764; SOFT-NEXT:    add sp, sp, #162765; SOFT-NEXT:    pop {r4, r5, r11, pc}2766;2767; HARD-LABEL: test_v4i32_f128:2768; HARD:       @ %bb.0:2769; HARD-NEXT:    .save {r4, r5, r11, lr}2770; HARD-NEXT:    push {r4, r5, r11, lr}2771; HARD-NEXT:    .pad #162772; HARD-NEXT:    sub sp, sp, #162773; HARD-NEXT:    ldr r4, [r0]2774; HARD-NEXT:    mov r5, r12775; HARD-NEXT:    ldmib r0, {r1, r2, r3}2776; HARD-NEXT:    mov r0, r42777; HARD-NEXT:    str r4, [sp]2778; HARD-NEXT:    stmib sp, {r1, r2, r3}2779; HARD-NEXT:    bl __addtf32780; HARD-NEXT:    bl test_v4i32_f128_helper2781; HARD-NEXT:    vrev64.32 q8, q02782; HARD-NEXT:    vadd.i32 q8, q8, q82783; HARD-NEXT:    vrev64.32 q8, q82784; HARD-NEXT:    vst1.64 {d16, d17}, [r5]2785; HARD-NEXT:    add sp, sp, #162786; HARD-NEXT:    pop {r4, r5, r11, pc}2787    %1 = load fp128, ptr %p2788    %2 = fadd fp128 %1, %12789    %3 = call <4 x i32> @test_v4i32_f128_helper(fp128 %2)2790    %4 = add <4 x i32> %3, %32791    store <4 x i32> %4, ptr %q2792    ret void2793}2794 2795declare <4 x i32> @test_v4i32_v2f64_helper(<2 x double> %p)2796define void @test_v4i32_v2f64(ptr %p, ptr %q) {2797; SOFT-LABEL: test_v4i32_v2f64:2798; SOFT:       @ %bb.0:2799; SOFT-NEXT:    .save {r4, lr}2800; SOFT-NEXT:    push {r4, lr}2801; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]2802; SOFT-NEXT:    mov r4, r12803; SOFT-NEXT:    vadd.f64 d18, d16, d162804; SOFT-NEXT:    vadd.f64 d16, d17, d172805; SOFT-NEXT:    vmov r1, r0, d182806; SOFT-NEXT:    vmov r3, r2, d162807; SOFT-NEXT:    bl test_v4i32_v2f64_helper2808; SOFT-NEXT:    vmov d17, r3, r22809; SOFT-NEXT:    vmov d16, r1, r02810; SOFT-NEXT:    vrev64.32 q8, q82811; SOFT-NEXT:    vadd.i32 q8, q8, q82812; SOFT-NEXT:    vrev64.32 q8, q82813; SOFT-NEXT:    vst1.64 {d16, d17}, [r4]2814; SOFT-NEXT:    pop {r4, pc}2815;2816; HARD-LABEL: test_v4i32_v2f64:2817; HARD:       @ %bb.0:2818; HARD-NEXT:    .save {r4, lr}2819; HARD-NEXT:    push {r4, lr}2820; HARD-NEXT:    vld1.64 {d16, d17}, [r0]2821; HARD-NEXT:    mov r4, r12822; HARD-NEXT:    vadd.f64 d1, d17, d172823; HARD-NEXT:    vadd.f64 d0, d16, d162824; HARD-NEXT:    bl test_v4i32_v2f64_helper2825; HARD-NEXT:    vrev64.32 q8, q02826; HARD-NEXT:    vadd.i32 q8, q8, q82827; HARD-NEXT:    vrev64.32 q8, q82828; HARD-NEXT:    vst1.64 {d16, d17}, [r4]2829; HARD-NEXT:    pop {r4, pc}2830    %1 = load <2 x double>, ptr %p2831    %2 = fadd <2 x double> %1, %12832    %3 = call <4 x i32> @test_v4i32_v2f64_helper(<2 x double> %2)2833    %4 = add <4 x i32> %3, %32834    store <4 x i32> %4, ptr %q2835    ret void2836}2837 2838declare <4 x i32> @test_v4i32_v2i64_helper(<2 x i64> %p)2839define void @test_v4i32_v2i64(ptr %p, ptr %q) {2840; SOFT-LABEL: test_v4i32_v2i64:2841; SOFT:       @ %bb.0:2842; SOFT-NEXT:    .save {r4, lr}2843; SOFT-NEXT:    push {r4, lr}2844; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]2845; SOFT-NEXT:    mov r4, r12846; SOFT-NEXT:    vadd.i64 q8, q8, q82847; SOFT-NEXT:    vmov r1, r0, d162848; SOFT-NEXT:    vmov r3, r2, d172849; SOFT-NEXT:    bl test_v4i32_v2i64_helper2850; SOFT-NEXT:    vmov d17, r3, r22851; SOFT-NEXT:    vmov d16, r1, r02852; SOFT-NEXT:    vrev64.32 q8, q82853; SOFT-NEXT:    vadd.i32 q8, q8, q82854; SOFT-NEXT:    vrev64.32 q8, q82855; SOFT-NEXT:    vst1.64 {d16, d17}, [r4]2856; SOFT-NEXT:    pop {r4, pc}2857;2858; HARD-LABEL: test_v4i32_v2i64:2859; HARD:       @ %bb.0:2860; HARD-NEXT:    .save {r4, lr}2861; HARD-NEXT:    push {r4, lr}2862; HARD-NEXT:    vld1.64 {d16, d17}, [r0]2863; HARD-NEXT:    mov r4, r12864; HARD-NEXT:    vadd.i64 q0, q8, q82865; HARD-NEXT:    bl test_v4i32_v2i64_helper2866; HARD-NEXT:    vrev64.32 q8, q02867; HARD-NEXT:    vadd.i32 q8, q8, q82868; HARD-NEXT:    vrev64.32 q8, q82869; HARD-NEXT:    vst1.64 {d16, d17}, [r4]2870; HARD-NEXT:    pop {r4, pc}2871    %1 = load <2 x i64>, ptr %p2872    %2 = add <2 x i64> %1, %12873    %3 = call <4 x i32> @test_v4i32_v2i64_helper(<2 x i64> %2)2874    %4 = add <4 x i32> %3, %32875    store <4 x i32> %4, ptr %q2876    ret void2877}2878 2879declare <4 x i32> @test_v4i32_v4f32_helper(<4 x float> %p)2880define void @test_v4i32_v4f32(ptr %p, ptr %q) {2881; SOFT-LABEL: test_v4i32_v4f32:2882; SOFT:       @ %bb.0:2883; SOFT-NEXT:    .save {r4, lr}2884; SOFT-NEXT:    push {r4, lr}2885; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]2886; SOFT-NEXT:    mov r4, r12887; SOFT-NEXT:    vrev64.32 q8, q82888; SOFT-NEXT:    vadd.f32 q8, q8, q82889; SOFT-NEXT:    vrev64.32 q8, q82890; SOFT-NEXT:    vmov r1, r0, d162891; SOFT-NEXT:    vmov r3, r2, d172892; SOFT-NEXT:    bl test_v4i32_v4f32_helper2893; SOFT-NEXT:    vmov d17, r3, r22894; SOFT-NEXT:    vmov d16, r1, r02895; SOFT-NEXT:    vrev64.32 q8, q82896; SOFT-NEXT:    vadd.i32 q8, q8, q82897; SOFT-NEXT:    vrev64.32 q8, q82898; SOFT-NEXT:    vst1.64 {d16, d17}, [r4]2899; SOFT-NEXT:    pop {r4, pc}2900;2901; HARD-LABEL: test_v4i32_v4f32:2902; HARD:       @ %bb.0:2903; HARD-NEXT:    .save {r4, lr}2904; HARD-NEXT:    push {r4, lr}2905; HARD-NEXT:    vld1.64 {d16, d17}, [r0]2906; HARD-NEXT:    mov r4, r12907; HARD-NEXT:    vrev64.32 q8, q82908; HARD-NEXT:    vadd.f32 q8, q8, q82909; HARD-NEXT:    vrev64.32 q0, q82910; HARD-NEXT:    bl test_v4i32_v4f32_helper2911; HARD-NEXT:    vrev64.32 q8, q02912; HARD-NEXT:    vadd.i32 q8, q8, q82913; HARD-NEXT:    vrev64.32 q8, q82914; HARD-NEXT:    vst1.64 {d16, d17}, [r4]2915; HARD-NEXT:    pop {r4, pc}2916    %1 = load <4 x float>, ptr %p2917    %2 = fadd <4 x float> %1, %12918    %3 = call <4 x i32> @test_v4i32_v4f32_helper(<4 x float> %2)2919    %4 = add <4 x i32> %3, %32920    store <4 x i32> %4, ptr %q2921    ret void2922}2923 2924declare <4 x i32> @test_v4i32_v8i16_helper(<8 x i16> %p)2925define void @test_v4i32_v8i16(ptr %p, ptr %q) {2926; SOFT-LABEL: test_v4i32_v8i16:2927; SOFT:       @ %bb.0:2928; SOFT-NEXT:    .save {r4, lr}2929; SOFT-NEXT:    push {r4, lr}2930; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]2931; SOFT-NEXT:    mov r4, r12932; SOFT-NEXT:    vrev64.16 q8, q82933; SOFT-NEXT:    vadd.i16 q8, q8, q82934; SOFT-NEXT:    vrev64.16 q8, q82935; SOFT-NEXT:    vmov r1, r0, d162936; SOFT-NEXT:    vmov r3, r2, d172937; SOFT-NEXT:    bl test_v4i32_v8i16_helper2938; SOFT-NEXT:    vmov d17, r3, r22939; SOFT-NEXT:    vmov d16, r1, r02940; SOFT-NEXT:    vrev64.32 q8, q82941; SOFT-NEXT:    vadd.i32 q8, q8, q82942; SOFT-NEXT:    vrev64.32 q8, q82943; SOFT-NEXT:    vst1.64 {d16, d17}, [r4]2944; SOFT-NEXT:    pop {r4, pc}2945;2946; HARD-LABEL: test_v4i32_v8i16:2947; HARD:       @ %bb.0:2948; HARD-NEXT:    .save {r4, lr}2949; HARD-NEXT:    push {r4, lr}2950; HARD-NEXT:    vld1.64 {d16, d17}, [r0]2951; HARD-NEXT:    mov r4, r12952; HARD-NEXT:    vrev64.16 q8, q82953; HARD-NEXT:    vadd.i16 q8, q8, q82954; HARD-NEXT:    vrev64.16 q0, q82955; HARD-NEXT:    bl test_v4i32_v8i16_helper2956; HARD-NEXT:    vrev64.32 q8, q02957; HARD-NEXT:    vadd.i32 q8, q8, q82958; HARD-NEXT:    vrev64.32 q8, q82959; HARD-NEXT:    vst1.64 {d16, d17}, [r4]2960; HARD-NEXT:    pop {r4, pc}2961    %1 = load <8 x i16>, ptr %p2962    %2 = add <8 x i16> %1, %12963    %3 = call <4 x i32> @test_v4i32_v8i16_helper(<8 x i16> %2)2964    %4 = add <4 x i32> %3, %32965    store <4 x i32> %4, ptr %q2966    ret void2967}2968 2969declare <4 x i32> @test_v4i32_v16i8_helper(<16 x i8> %p)2970define void @test_v4i32_v16i8(ptr %p, ptr %q) {2971; SOFT-LABEL: test_v4i32_v16i8:2972; SOFT:       @ %bb.0:2973; SOFT-NEXT:    .save {r4, lr}2974; SOFT-NEXT:    push {r4, lr}2975; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]2976; SOFT-NEXT:    mov r4, r12977; SOFT-NEXT:    vrev64.8 q8, q82978; SOFT-NEXT:    vadd.i8 q8, q8, q82979; SOFT-NEXT:    vrev64.8 q8, q82980; SOFT-NEXT:    vmov r1, r0, d162981; SOFT-NEXT:    vmov r3, r2, d172982; SOFT-NEXT:    bl test_v4i32_v16i8_helper2983; SOFT-NEXT:    vmov d17, r3, r22984; SOFT-NEXT:    vmov d16, r1, r02985; SOFT-NEXT:    vrev64.32 q8, q82986; SOFT-NEXT:    vadd.i32 q8, q8, q82987; SOFT-NEXT:    vrev64.32 q8, q82988; SOFT-NEXT:    vst1.64 {d16, d17}, [r4]2989; SOFT-NEXT:    pop {r4, pc}2990;2991; HARD-LABEL: test_v4i32_v16i8:2992; HARD:       @ %bb.0:2993; HARD-NEXT:    .save {r4, lr}2994; HARD-NEXT:    push {r4, lr}2995; HARD-NEXT:    vld1.64 {d16, d17}, [r0]2996; HARD-NEXT:    mov r4, r12997; HARD-NEXT:    vrev64.8 q8, q82998; HARD-NEXT:    vadd.i8 q8, q8, q82999; HARD-NEXT:    vrev64.8 q0, q83000; HARD-NEXT:    bl test_v4i32_v16i8_helper3001; HARD-NEXT:    vrev64.32 q8, q03002; HARD-NEXT:    vadd.i32 q8, q8, q83003; HARD-NEXT:    vrev64.32 q8, q83004; HARD-NEXT:    vst1.64 {d16, d17}, [r4]3005; HARD-NEXT:    pop {r4, pc}3006    %1 = load <16 x i8>, ptr %p3007    %2 = add <16 x i8> %1, %13008    %3 = call <4 x i32> @test_v4i32_v16i8_helper(<16 x i8> %2)3009    %4 = add <4 x i32> %3, %33010    store <4 x i32> %4, ptr %q3011    ret void3012}3013 3014declare <8 x i16> @test_v8i16_f128_helper(fp128 %p)3015define void @test_v8i16_f128(ptr %p, ptr %q) {3016; SOFT-LABEL: test_v8i16_f128:3017; SOFT:       @ %bb.0:3018; SOFT-NEXT:    .save {r4, r5, r11, lr}3019; SOFT-NEXT:    push {r4, r5, r11, lr}3020; SOFT-NEXT:    .pad #163021; SOFT-NEXT:    sub sp, sp, #163022; SOFT-NEXT:    ldr r4, [r0]3023; SOFT-NEXT:    mov r5, r13024; SOFT-NEXT:    ldmib r0, {r1, r2, r3}3025; SOFT-NEXT:    mov r0, r43026; SOFT-NEXT:    str r4, [sp]3027; SOFT-NEXT:    stmib sp, {r1, r2, r3}3028; SOFT-NEXT:    bl __addtf33029; SOFT-NEXT:    bl test_v8i16_f128_helper3030; SOFT-NEXT:    vmov d17, r3, r23031; SOFT-NEXT:    vmov d16, r1, r03032; SOFT-NEXT:    vrev64.16 q8, q83033; SOFT-NEXT:    vadd.i16 q8, q8, q83034; SOFT-NEXT:    vrev64.16 q8, q83035; SOFT-NEXT:    vst1.64 {d16, d17}, [r5]3036; SOFT-NEXT:    add sp, sp, #163037; SOFT-NEXT:    pop {r4, r5, r11, pc}3038;3039; HARD-LABEL: test_v8i16_f128:3040; HARD:       @ %bb.0:3041; HARD-NEXT:    .save {r4, r5, r11, lr}3042; HARD-NEXT:    push {r4, r5, r11, lr}3043; HARD-NEXT:    .pad #163044; HARD-NEXT:    sub sp, sp, #163045; HARD-NEXT:    ldr r4, [r0]3046; HARD-NEXT:    mov r5, r13047; HARD-NEXT:    ldmib r0, {r1, r2, r3}3048; HARD-NEXT:    mov r0, r43049; HARD-NEXT:    str r4, [sp]3050; HARD-NEXT:    stmib sp, {r1, r2, r3}3051; HARD-NEXT:    bl __addtf33052; HARD-NEXT:    bl test_v8i16_f128_helper3053; HARD-NEXT:    vrev64.16 q8, q03054; HARD-NEXT:    vadd.i16 q8, q8, q83055; HARD-NEXT:    vrev64.16 q8, q83056; HARD-NEXT:    vst1.64 {d16, d17}, [r5]3057; HARD-NEXT:    add sp, sp, #163058; HARD-NEXT:    pop {r4, r5, r11, pc}3059    %1 = load fp128, ptr %p3060    %2 = fadd fp128 %1, %13061    %3 = call <8 x i16> @test_v8i16_f128_helper(fp128 %2)3062    %4 = add <8 x i16> %3, %33063    store <8 x i16> %4, ptr %q3064    ret void3065}3066 3067declare <8 x i16> @test_v8i16_v2f64_helper(<2 x double> %p)3068define void @test_v8i16_v2f64(ptr %p, ptr %q) {3069; SOFT-LABEL: test_v8i16_v2f64:3070; SOFT:       @ %bb.0:3071; SOFT-NEXT:    .save {r4, lr}3072; SOFT-NEXT:    push {r4, lr}3073; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]3074; SOFT-NEXT:    mov r4, r13075; SOFT-NEXT:    vadd.f64 d18, d16, d163076; SOFT-NEXT:    vadd.f64 d16, d17, d173077; SOFT-NEXT:    vmov r1, r0, d183078; SOFT-NEXT:    vmov r3, r2, d163079; SOFT-NEXT:    bl test_v8i16_v2f64_helper3080; SOFT-NEXT:    vmov d17, r3, r23081; SOFT-NEXT:    vmov d16, r1, r03082; SOFT-NEXT:    vrev64.16 q8, q83083; SOFT-NEXT:    vadd.i16 q8, q8, q83084; SOFT-NEXT:    vrev64.16 q8, q83085; SOFT-NEXT:    vst1.64 {d16, d17}, [r4]3086; SOFT-NEXT:    pop {r4, pc}3087;3088; HARD-LABEL: test_v8i16_v2f64:3089; HARD:       @ %bb.0:3090; HARD-NEXT:    .save {r4, lr}3091; HARD-NEXT:    push {r4, lr}3092; HARD-NEXT:    vld1.64 {d16, d17}, [r0]3093; HARD-NEXT:    mov r4, r13094; HARD-NEXT:    vadd.f64 d1, d17, d173095; HARD-NEXT:    vadd.f64 d0, d16, d163096; HARD-NEXT:    bl test_v8i16_v2f64_helper3097; HARD-NEXT:    vrev64.16 q8, q03098; HARD-NEXT:    vadd.i16 q8, q8, q83099; HARD-NEXT:    vrev64.16 q8, q83100; HARD-NEXT:    vst1.64 {d16, d17}, [r4]3101; HARD-NEXT:    pop {r4, pc}3102    %1 = load <2 x double>, ptr %p3103    %2 = fadd <2 x double> %1, %13104    %3 = call <8 x i16> @test_v8i16_v2f64_helper(<2 x double> %2)3105    %4 = add <8 x i16> %3, %33106    store <8 x i16> %4, ptr %q3107    ret void3108}3109 3110declare <8 x i16> @test_v8i16_v2i64_helper(<2 x i64> %p)3111define void @test_v8i16_v2i64(ptr %p, ptr %q) {3112; SOFT-LABEL: test_v8i16_v2i64:3113; SOFT:       @ %bb.0:3114; SOFT-NEXT:    .save {r4, lr}3115; SOFT-NEXT:    push {r4, lr}3116; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]3117; SOFT-NEXT:    mov r4, r13118; SOFT-NEXT:    vadd.i64 q8, q8, q83119; SOFT-NEXT:    vmov r1, r0, d163120; SOFT-NEXT:    vmov r3, r2, d173121; SOFT-NEXT:    bl test_v8i16_v2i64_helper3122; SOFT-NEXT:    vmov d17, r3, r23123; SOFT-NEXT:    vmov d16, r1, r03124; SOFT-NEXT:    vrev64.16 q8, q83125; SOFT-NEXT:    vadd.i16 q8, q8, q83126; SOFT-NEXT:    vrev64.16 q8, q83127; SOFT-NEXT:    vst1.64 {d16, d17}, [r4]3128; SOFT-NEXT:    pop {r4, pc}3129;3130; HARD-LABEL: test_v8i16_v2i64:3131; HARD:       @ %bb.0:3132; HARD-NEXT:    .save {r4, lr}3133; HARD-NEXT:    push {r4, lr}3134; HARD-NEXT:    vld1.64 {d16, d17}, [r0]3135; HARD-NEXT:    mov r4, r13136; HARD-NEXT:    vadd.i64 q0, q8, q83137; HARD-NEXT:    bl test_v8i16_v2i64_helper3138; HARD-NEXT:    vrev64.16 q8, q03139; HARD-NEXT:    vadd.i16 q8, q8, q83140; HARD-NEXT:    vrev64.16 q8, q83141; HARD-NEXT:    vst1.64 {d16, d17}, [r4]3142; HARD-NEXT:    pop {r4, pc}3143    %1 = load <2 x i64>, ptr %p3144    %2 = add <2 x i64> %1, %13145    %3 = call <8 x i16> @test_v8i16_v2i64_helper(<2 x i64> %2)3146    %4 = add <8 x i16> %3, %33147    store <8 x i16> %4, ptr %q3148    ret void3149}3150 3151declare <8 x i16> @test_v8i16_v4f32_helper(<4 x float> %p)3152define void @test_v8i16_v4f32(ptr %p, ptr %q) {3153; SOFT-LABEL: test_v8i16_v4f32:3154; SOFT:       @ %bb.0:3155; SOFT-NEXT:    .save {r4, lr}3156; SOFT-NEXT:    push {r4, lr}3157; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]3158; SOFT-NEXT:    mov r4, r13159; SOFT-NEXT:    vrev64.32 q8, q83160; SOFT-NEXT:    vadd.f32 q8, q8, q83161; SOFT-NEXT:    vrev64.32 q8, q83162; SOFT-NEXT:    vmov r1, r0, d163163; SOFT-NEXT:    vmov r3, r2, d173164; SOFT-NEXT:    bl test_v8i16_v4f32_helper3165; SOFT-NEXT:    vmov d17, r3, r23166; SOFT-NEXT:    vmov d16, r1, r03167; SOFT-NEXT:    vrev64.16 q8, q83168; SOFT-NEXT:    vadd.i16 q8, q8, q83169; SOFT-NEXT:    vrev64.16 q8, q83170; SOFT-NEXT:    vst1.64 {d16, d17}, [r4]3171; SOFT-NEXT:    pop {r4, pc}3172;3173; HARD-LABEL: test_v8i16_v4f32:3174; HARD:       @ %bb.0:3175; HARD-NEXT:    .save {r4, lr}3176; HARD-NEXT:    push {r4, lr}3177; HARD-NEXT:    vld1.64 {d16, d17}, [r0]3178; HARD-NEXT:    mov r4, r13179; HARD-NEXT:    vrev64.32 q8, q83180; HARD-NEXT:    vadd.f32 q8, q8, q83181; HARD-NEXT:    vrev64.32 q0, q83182; HARD-NEXT:    bl test_v8i16_v4f32_helper3183; HARD-NEXT:    vrev64.16 q8, q03184; HARD-NEXT:    vadd.i16 q8, q8, q83185; HARD-NEXT:    vrev64.16 q8, q83186; HARD-NEXT:    vst1.64 {d16, d17}, [r4]3187; HARD-NEXT:    pop {r4, pc}3188    %1 = load <4 x float>, ptr %p3189    %2 = fadd <4 x float> %1, %13190    %3 = call <8 x i16> @test_v8i16_v4f32_helper(<4 x float> %2)3191    %4 = add <8 x i16> %3, %33192    store <8 x i16> %4, ptr %q3193    ret void3194}3195 3196declare <8 x i16> @test_v8i16_v4i32_helper(<4 x i32> %p)3197define void @test_v8i16_v4i32(ptr %p, ptr %q) {3198; SOFT-LABEL: test_v8i16_v4i32:3199; SOFT:       @ %bb.0:3200; SOFT-NEXT:    .save {r4, lr}3201; SOFT-NEXT:    push {r4, lr}3202; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]3203; SOFT-NEXT:    mov r4, r13204; SOFT-NEXT:    vrev64.32 q8, q83205; SOFT-NEXT:    vadd.i32 q8, q8, q83206; SOFT-NEXT:    vrev64.32 q8, q83207; SOFT-NEXT:    vmov r1, r0, d163208; SOFT-NEXT:    vmov r3, r2, d173209; SOFT-NEXT:    bl test_v8i16_v4i32_helper3210; SOFT-NEXT:    vmov d17, r3, r23211; SOFT-NEXT:    vmov d16, r1, r03212; SOFT-NEXT:    vrev64.16 q8, q83213; SOFT-NEXT:    vadd.i16 q8, q8, q83214; SOFT-NEXT:    vrev64.16 q8, q83215; SOFT-NEXT:    vst1.64 {d16, d17}, [r4]3216; SOFT-NEXT:    pop {r4, pc}3217;3218; HARD-LABEL: test_v8i16_v4i32:3219; HARD:       @ %bb.0:3220; HARD-NEXT:    .save {r4, lr}3221; HARD-NEXT:    push {r4, lr}3222; HARD-NEXT:    vld1.64 {d16, d17}, [r0]3223; HARD-NEXT:    mov r4, r13224; HARD-NEXT:    vrev64.32 q8, q83225; HARD-NEXT:    vadd.i32 q8, q8, q83226; HARD-NEXT:    vrev64.32 q0, q83227; HARD-NEXT:    bl test_v8i16_v4i32_helper3228; HARD-NEXT:    vrev64.16 q8, q03229; HARD-NEXT:    vadd.i16 q8, q8, q83230; HARD-NEXT:    vrev64.16 q8, q83231; HARD-NEXT:    vst1.64 {d16, d17}, [r4]3232; HARD-NEXT:    pop {r4, pc}3233    %1 = load <4 x i32>, ptr %p3234    %2 = add <4 x i32> %1, %13235    %3 = call <8 x i16> @test_v8i16_v4i32_helper(<4 x i32> %2)3236    %4 = add <8 x i16> %3, %33237    store <8 x i16> %4, ptr %q3238    ret void3239}3240 3241declare <8 x i16> @test_v8i16_v16i8_helper(<16 x i8> %p)3242define void @test_v8i16_v16i8(ptr %p, ptr %q) {3243; SOFT-LABEL: test_v8i16_v16i8:3244; SOFT:       @ %bb.0:3245; SOFT-NEXT:    .save {r4, lr}3246; SOFT-NEXT:    push {r4, lr}3247; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]3248; SOFT-NEXT:    mov r4, r13249; SOFT-NEXT:    vrev64.8 q8, q83250; SOFT-NEXT:    vadd.i8 q8, q8, q83251; SOFT-NEXT:    vrev64.8 q8, q83252; SOFT-NEXT:    vmov r1, r0, d163253; SOFT-NEXT:    vmov r3, r2, d173254; SOFT-NEXT:    bl test_v8i16_v16i8_helper3255; SOFT-NEXT:    vmov d17, r3, r23256; SOFT-NEXT:    vmov d16, r1, r03257; SOFT-NEXT:    vrev64.16 q8, q83258; SOFT-NEXT:    vadd.i16 q8, q8, q83259; SOFT-NEXT:    vrev64.16 q8, q83260; SOFT-NEXT:    vst1.64 {d16, d17}, [r4]3261; SOFT-NEXT:    pop {r4, pc}3262;3263; HARD-LABEL: test_v8i16_v16i8:3264; HARD:       @ %bb.0:3265; HARD-NEXT:    .save {r4, lr}3266; HARD-NEXT:    push {r4, lr}3267; HARD-NEXT:    vld1.64 {d16, d17}, [r0]3268; HARD-NEXT:    mov r4, r13269; HARD-NEXT:    vrev64.8 q8, q83270; HARD-NEXT:    vadd.i8 q8, q8, q83271; HARD-NEXT:    vrev64.8 q0, q83272; HARD-NEXT:    bl test_v8i16_v16i8_helper3273; HARD-NEXT:    vrev64.16 q8, q03274; HARD-NEXT:    vadd.i16 q8, q8, q83275; HARD-NEXT:    vrev64.16 q8, q83276; HARD-NEXT:    vst1.64 {d16, d17}, [r4]3277; HARD-NEXT:    pop {r4, pc}3278    %1 = load <16 x i8>, ptr %p3279    %2 = add <16 x i8> %1, %13280    %3 = call <8 x i16> @test_v8i16_v16i8_helper(<16 x i8> %2)3281    %4 = add <8 x i16> %3, %33282    store <8 x i16> %4, ptr %q3283    ret void3284}3285 3286declare <16 x i8> @test_v16i8_f128_helper(fp128 %p)3287define void @test_v16i8_f128(ptr %p, ptr %q) {3288; SOFT-LABEL: test_v16i8_f128:3289; SOFT:       @ %bb.0:3290; SOFT-NEXT:    .save {r4, r5, r11, lr}3291; SOFT-NEXT:    push {r4, r5, r11, lr}3292; SOFT-NEXT:    .pad #163293; SOFT-NEXT:    sub sp, sp, #163294; SOFT-NEXT:    ldr r4, [r0]3295; SOFT-NEXT:    mov r5, r13296; SOFT-NEXT:    ldmib r0, {r1, r2, r3}3297; SOFT-NEXT:    mov r0, r43298; SOFT-NEXT:    str r4, [sp]3299; SOFT-NEXT:    stmib sp, {r1, r2, r3}3300; SOFT-NEXT:    bl __addtf33301; SOFT-NEXT:    bl test_v16i8_f128_helper3302; SOFT-NEXT:    vmov d17, r3, r23303; SOFT-NEXT:    vmov d16, r1, r03304; SOFT-NEXT:    vrev64.8 q8, q83305; SOFT-NEXT:    vadd.i8 q8, q8, q83306; SOFT-NEXT:    vrev64.8 q8, q83307; SOFT-NEXT:    vst1.64 {d16, d17}, [r5]3308; SOFT-NEXT:    add sp, sp, #163309; SOFT-NEXT:    pop {r4, r5, r11, pc}3310;3311; HARD-LABEL: test_v16i8_f128:3312; HARD:       @ %bb.0:3313; HARD-NEXT:    .save {r4, r5, r11, lr}3314; HARD-NEXT:    push {r4, r5, r11, lr}3315; HARD-NEXT:    .pad #163316; HARD-NEXT:    sub sp, sp, #163317; HARD-NEXT:    ldr r4, [r0]3318; HARD-NEXT:    mov r5, r13319; HARD-NEXT:    ldmib r0, {r1, r2, r3}3320; HARD-NEXT:    mov r0, r43321; HARD-NEXT:    str r4, [sp]3322; HARD-NEXT:    stmib sp, {r1, r2, r3}3323; HARD-NEXT:    bl __addtf33324; HARD-NEXT:    bl test_v16i8_f128_helper3325; HARD-NEXT:    vrev64.8 q8, q03326; HARD-NEXT:    vadd.i8 q8, q8, q83327; HARD-NEXT:    vrev64.8 q8, q83328; HARD-NEXT:    vst1.64 {d16, d17}, [r5]3329; HARD-NEXT:    add sp, sp, #163330; HARD-NEXT:    pop {r4, r5, r11, pc}3331    %1 = load fp128, ptr %p3332    %2 = fadd fp128 %1, %13333    %3 = call <16 x i8> @test_v16i8_f128_helper(fp128 %2)3334    %4 = add <16 x i8> %3, %33335    store <16 x i8> %4, ptr %q3336    ret void3337}3338 3339declare <16 x i8> @test_v16i8_v2f64_helper(<2 x double> %p)3340define void @test_v16i8_v2f64(ptr %p, ptr %q) {3341; SOFT-LABEL: test_v16i8_v2f64:3342; SOFT:       @ %bb.0:3343; SOFT-NEXT:    .save {r4, lr}3344; SOFT-NEXT:    push {r4, lr}3345; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]3346; SOFT-NEXT:    mov r4, r13347; SOFT-NEXT:    vadd.f64 d18, d16, d163348; SOFT-NEXT:    vadd.f64 d16, d17, d173349; SOFT-NEXT:    vmov r1, r0, d183350; SOFT-NEXT:    vmov r3, r2, d163351; SOFT-NEXT:    bl test_v16i8_v2f64_helper3352; SOFT-NEXT:    vmov d17, r3, r23353; SOFT-NEXT:    vmov d16, r1, r03354; SOFT-NEXT:    vrev64.8 q8, q83355; SOFT-NEXT:    vadd.i8 q8, q8, q83356; SOFT-NEXT:    vrev64.8 q8, q83357; SOFT-NEXT:    vst1.64 {d16, d17}, [r4]3358; SOFT-NEXT:    pop {r4, pc}3359;3360; HARD-LABEL: test_v16i8_v2f64:3361; HARD:       @ %bb.0:3362; HARD-NEXT:    .save {r4, lr}3363; HARD-NEXT:    push {r4, lr}3364; HARD-NEXT:    vld1.64 {d16, d17}, [r0]3365; HARD-NEXT:    mov r4, r13366; HARD-NEXT:    vadd.f64 d1, d17, d173367; HARD-NEXT:    vadd.f64 d0, d16, d163368; HARD-NEXT:    bl test_v16i8_v2f64_helper3369; HARD-NEXT:    vrev64.8 q8, q03370; HARD-NEXT:    vadd.i8 q8, q8, q83371; HARD-NEXT:    vrev64.8 q8, q83372; HARD-NEXT:    vst1.64 {d16, d17}, [r4]3373; HARD-NEXT:    pop {r4, pc}3374    %1 = load <2 x double>, ptr %p3375    %2 = fadd <2 x double> %1, %13376    %3 = call <16 x i8> @test_v16i8_v2f64_helper(<2 x double> %2)3377    %4 = add <16 x i8> %3, %33378    store <16 x i8> %4, ptr %q3379    ret void3380}3381 3382declare <16 x i8> @test_v16i8_v2i64_helper(<2 x i64> %p)3383define void @test_v16i8_v2i64(ptr %p, ptr %q) {3384; SOFT-LABEL: test_v16i8_v2i64:3385; SOFT:       @ %bb.0:3386; SOFT-NEXT:    .save {r4, lr}3387; SOFT-NEXT:    push {r4, lr}3388; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]3389; SOFT-NEXT:    mov r4, r13390; SOFT-NEXT:    vadd.i64 q8, q8, q83391; SOFT-NEXT:    vmov r1, r0, d163392; SOFT-NEXT:    vmov r3, r2, d173393; SOFT-NEXT:    bl test_v16i8_v2i64_helper3394; SOFT-NEXT:    vmov d17, r3, r23395; SOFT-NEXT:    vmov d16, r1, r03396; SOFT-NEXT:    vrev64.8 q8, q83397; SOFT-NEXT:    vadd.i8 q8, q8, q83398; SOFT-NEXT:    vrev64.8 q8, q83399; SOFT-NEXT:    vst1.64 {d16, d17}, [r4]3400; SOFT-NEXT:    pop {r4, pc}3401;3402; HARD-LABEL: test_v16i8_v2i64:3403; HARD:       @ %bb.0:3404; HARD-NEXT:    .save {r4, lr}3405; HARD-NEXT:    push {r4, lr}3406; HARD-NEXT:    vld1.64 {d16, d17}, [r0]3407; HARD-NEXT:    mov r4, r13408; HARD-NEXT:    vadd.i64 q0, q8, q83409; HARD-NEXT:    bl test_v16i8_v2i64_helper3410; HARD-NEXT:    vrev64.8 q8, q03411; HARD-NEXT:    vadd.i8 q8, q8, q83412; HARD-NEXT:    vrev64.8 q8, q83413; HARD-NEXT:    vst1.64 {d16, d17}, [r4]3414; HARD-NEXT:    pop {r4, pc}3415    %1 = load <2 x i64>, ptr %p3416    %2 = add <2 x i64> %1, %13417    %3 = call <16 x i8> @test_v16i8_v2i64_helper(<2 x i64> %2)3418    %4 = add <16 x i8> %3, %33419    store <16 x i8> %4, ptr %q3420    ret void3421}3422 3423declare <16 x i8> @test_v16i8_v4f32_helper(<4 x float> %p)3424define void @test_v16i8_v4f32(ptr %p, ptr %q) {3425; SOFT-LABEL: test_v16i8_v4f32:3426; SOFT:       @ %bb.0:3427; SOFT-NEXT:    .save {r4, lr}3428; SOFT-NEXT:    push {r4, lr}3429; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]3430; SOFT-NEXT:    mov r4, r13431; SOFT-NEXT:    vrev64.32 q8, q83432; SOFT-NEXT:    vadd.f32 q8, q8, q83433; SOFT-NEXT:    vrev64.32 q8, q83434; SOFT-NEXT:    vmov r1, r0, d163435; SOFT-NEXT:    vmov r3, r2, d173436; SOFT-NEXT:    bl test_v16i8_v4f32_helper3437; SOFT-NEXT:    vmov d17, r3, r23438; SOFT-NEXT:    vmov d16, r1, r03439; SOFT-NEXT:    vrev64.8 q8, q83440; SOFT-NEXT:    vadd.i8 q8, q8, q83441; SOFT-NEXT:    vrev64.8 q8, q83442; SOFT-NEXT:    vst1.64 {d16, d17}, [r4]3443; SOFT-NEXT:    pop {r4, pc}3444;3445; HARD-LABEL: test_v16i8_v4f32:3446; HARD:       @ %bb.0:3447; HARD-NEXT:    .save {r4, lr}3448; HARD-NEXT:    push {r4, lr}3449; HARD-NEXT:    vld1.64 {d16, d17}, [r0]3450; HARD-NEXT:    mov r4, r13451; HARD-NEXT:    vrev64.32 q8, q83452; HARD-NEXT:    vadd.f32 q8, q8, q83453; HARD-NEXT:    vrev64.32 q0, q83454; HARD-NEXT:    bl test_v16i8_v4f32_helper3455; HARD-NEXT:    vrev64.8 q8, q03456; HARD-NEXT:    vadd.i8 q8, q8, q83457; HARD-NEXT:    vrev64.8 q8, q83458; HARD-NEXT:    vst1.64 {d16, d17}, [r4]3459; HARD-NEXT:    pop {r4, pc}3460    %1 = load <4 x float>, ptr %p3461    %2 = fadd <4 x float> %1, %13462    %3 = call <16 x i8> @test_v16i8_v4f32_helper(<4 x float> %2)3463    %4 = add <16 x i8> %3, %33464    store <16 x i8> %4, ptr %q3465    ret void3466}3467 3468declare <16 x i8> @test_v16i8_v4i32_helper(<4 x i32> %p)3469define void @test_v16i8_v4i32(ptr %p, ptr %q) {3470; SOFT-LABEL: test_v16i8_v4i32:3471; SOFT:       @ %bb.0:3472; SOFT-NEXT:    .save {r4, lr}3473; SOFT-NEXT:    push {r4, lr}3474; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]3475; SOFT-NEXT:    mov r4, r13476; SOFT-NEXT:    vrev64.32 q8, q83477; SOFT-NEXT:    vadd.i32 q8, q8, q83478; SOFT-NEXT:    vrev64.32 q8, q83479; SOFT-NEXT:    vmov r1, r0, d163480; SOFT-NEXT:    vmov r3, r2, d173481; SOFT-NEXT:    bl test_v16i8_v4i32_helper3482; SOFT-NEXT:    vmov d17, r3, r23483; SOFT-NEXT:    vmov d16, r1, r03484; SOFT-NEXT:    vrev64.8 q8, q83485; SOFT-NEXT:    vadd.i8 q8, q8, q83486; SOFT-NEXT:    vrev64.8 q8, q83487; SOFT-NEXT:    vst1.64 {d16, d17}, [r4]3488; SOFT-NEXT:    pop {r4, pc}3489;3490; HARD-LABEL: test_v16i8_v4i32:3491; HARD:       @ %bb.0:3492; HARD-NEXT:    .save {r4, lr}3493; HARD-NEXT:    push {r4, lr}3494; HARD-NEXT:    vld1.64 {d16, d17}, [r0]3495; HARD-NEXT:    mov r4, r13496; HARD-NEXT:    vrev64.32 q8, q83497; HARD-NEXT:    vadd.i32 q8, q8, q83498; HARD-NEXT:    vrev64.32 q0, q83499; HARD-NEXT:    bl test_v16i8_v4i32_helper3500; HARD-NEXT:    vrev64.8 q8, q03501; HARD-NEXT:    vadd.i8 q8, q8, q83502; HARD-NEXT:    vrev64.8 q8, q83503; HARD-NEXT:    vst1.64 {d16, d17}, [r4]3504; HARD-NEXT:    pop {r4, pc}3505    %1 = load <4 x i32>, ptr %p3506    %2 = add <4 x i32> %1, %13507    %3 = call <16 x i8> @test_v16i8_v4i32_helper(<4 x i32> %2)3508    %4 = add <16 x i8> %3, %33509    store <16 x i8> %4, ptr %q3510    ret void3511}3512 3513declare <16 x i8> @test_v16i8_v8i16_helper(<8 x i16> %p)3514define void @test_v16i8_v8i16(ptr %p, ptr %q) {3515; SOFT-LABEL: test_v16i8_v8i16:3516; SOFT:       @ %bb.0:3517; SOFT-NEXT:    .save {r4, lr}3518; SOFT-NEXT:    push {r4, lr}3519; SOFT-NEXT:    vld1.64 {d16, d17}, [r0]3520; SOFT-NEXT:    mov r4, r13521; SOFT-NEXT:    vrev64.16 q8, q83522; SOFT-NEXT:    vadd.i16 q8, q8, q83523; SOFT-NEXT:    vrev64.16 q8, q83524; SOFT-NEXT:    vmov r1, r0, d163525; SOFT-NEXT:    vmov r3, r2, d173526; SOFT-NEXT:    bl test_v16i8_v8i16_helper3527; SOFT-NEXT:    vmov d17, r3, r23528; SOFT-NEXT:    vmov d16, r1, r03529; SOFT-NEXT:    vrev64.8 q8, q83530; SOFT-NEXT:    vadd.i8 q8, q8, q83531; SOFT-NEXT:    vrev64.8 q8, q83532; SOFT-NEXT:    vst1.64 {d16, d17}, [r4]3533; SOFT-NEXT:    pop {r4, pc}3534;3535; HARD-LABEL: test_v16i8_v8i16:3536; HARD:       @ %bb.0:3537; HARD-NEXT:    .save {r4, lr}3538; HARD-NEXT:    push {r4, lr}3539; HARD-NEXT:    vld1.64 {d16, d17}, [r0]3540; HARD-NEXT:    mov r4, r13541; HARD-NEXT:    vrev64.16 q8, q83542; HARD-NEXT:    vadd.i16 q8, q8, q83543; HARD-NEXT:    vrev64.16 q0, q83544; HARD-NEXT:    bl test_v16i8_v8i16_helper3545; HARD-NEXT:    vrev64.8 q8, q03546; HARD-NEXT:    vadd.i8 q8, q8, q83547; HARD-NEXT:    vrev64.8 q8, q83548; HARD-NEXT:    vst1.64 {d16, d17}, [r4]3549; HARD-NEXT:    pop {r4, pc}3550    %1 = load <8 x i16>, ptr %p3551    %2 = add <8 x i16> %1, %13552    %3 = call <16 x i8> @test_v16i8_v8i16_helper(<8 x i16> %2)3553    %4 = add <16 x i8> %3, %33554    store <16 x i8> %4, ptr %q3555    ret void3556}3557