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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple armv7-eabi -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LE3; RUN: llc < %s -mtriple armebv7-eabi -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE4 5define arm_aapcs_vfpcc <8 x i8> @vmov_i8() {6; CHECK-LE-LABEL: vmov_i8:7; CHECK-LE: @ %bb.0:8; CHECK-LE-NEXT: vmov.i64 d0, #0xff000000000000009; CHECK-LE-NEXT: bx lr10;11; CHECK-BE-LABEL: vmov_i8:12; CHECK-BE: @ %bb.0:13; CHECK-BE-NEXT: vmov.i64 d16, #0xff0000000000000014; CHECK-BE-NEXT: vrev64.8 d0, d1615; CHECK-BE-NEXT: bx lr16 ret <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 -1>17}18 19define arm_aapcs_vfpcc <4 x i16> @vmov_i16_a() {20; CHECK-LE-LABEL: vmov_i16_a:21; CHECK-LE: @ %bb.0:22; CHECK-LE-NEXT: vmov.i64 d0, #0xffff00000000000023; CHECK-LE-NEXT: bx lr24;25; CHECK-BE-LABEL: vmov_i16_a:26; CHECK-BE: @ %bb.0:27; CHECK-BE-NEXT: vmov.i64 d16, #0xffff00000000000028; CHECK-BE-NEXT: vrev64.16 d0, d1629; CHECK-BE-NEXT: bx lr30 ret <4 x i16> <i16 0, i16 0, i16 0, i16 -1>31}32 33define arm_aapcs_vfpcc <4 x i16> @vmov_i16_b() {34; CHECK-LE-LABEL: vmov_i16_b:35; CHECK-LE: @ %bb.0:36; CHECK-LE-NEXT: vmov.i64 d0, #0xff00000000000037; CHECK-LE-NEXT: bx lr38;39; CHECK-BE-LABEL: vmov_i16_b:40; CHECK-BE: @ %bb.0:41; CHECK-BE-NEXT: vmov.i64 d16, #0xff00000000000042; CHECK-BE-NEXT: vrev64.16 d0, d1643; CHECK-BE-NEXT: bx lr44 ret <4 x i16> <i16 0, i16 0, i16 0, i16 255>45}46 47define arm_aapcs_vfpcc <4 x i16> @vmov_i16_c() {48; CHECK-LE-LABEL: vmov_i16_c:49; CHECK-LE: @ %bb.0:50; CHECK-LE-NEXT: vmov.i64 d0, #0xff0000000000000051; CHECK-LE-NEXT: bx lr52;53; CHECK-BE-LABEL: vmov_i16_c:54; CHECK-BE: @ %bb.0:55; CHECK-BE-NEXT: vmov.i64 d16, #0xff0000000000000056; CHECK-BE-NEXT: vrev64.16 d0, d1657; CHECK-BE-NEXT: bx lr58 ret <4 x i16> <i16 0, i16 0, i16 0, i16 65280>59}60 61define arm_aapcs_vfpcc <2 x i32> @vmov_i32_a() {62; CHECK-LE-LABEL: vmov_i32_a:63; CHECK-LE: @ %bb.0:64; CHECK-LE-NEXT: vmov.i64 d0, #0xffffffff0000000065; CHECK-LE-NEXT: bx lr66;67; CHECK-BE-LABEL: vmov_i32_a:68; CHECK-BE: @ %bb.0:69; CHECK-BE-NEXT: vmov.i64 d16, #0xffffffff0000000070; CHECK-BE-NEXT: vrev64.32 d0, d1671; CHECK-BE-NEXT: bx lr72 ret <2 x i32> <i32 0, i32 -1>73}74 75define arm_aapcs_vfpcc <2 x i32> @vmov_i32_b() {76; CHECK-LE-LABEL: vmov_i32_b:77; CHECK-LE: @ %bb.0:78; CHECK-LE-NEXT: vmov.i64 d0, #0xff0000000079; CHECK-LE-NEXT: bx lr80;81; CHECK-BE-LABEL: vmov_i32_b:82; CHECK-BE: @ %bb.0:83; CHECK-BE-NEXT: vmov.i64 d16, #0xff0000000084; CHECK-BE-NEXT: vrev64.32 d0, d1685; CHECK-BE-NEXT: bx lr86 ret <2 x i32> <i32 0, i32 255>87}88 89define arm_aapcs_vfpcc <2 x i32> @vmov_i32_c() {90; CHECK-LE-LABEL: vmov_i32_c:91; CHECK-LE: @ %bb.0:92; CHECK-LE-NEXT: vmov.i64 d0, #0xff000000000093; CHECK-LE-NEXT: bx lr94;95; CHECK-BE-LABEL: vmov_i32_c:96; CHECK-BE: @ %bb.0:97; CHECK-BE-NEXT: vmov.i64 d16, #0xff000000000098; CHECK-BE-NEXT: vrev64.32 d0, d1699; CHECK-BE-NEXT: bx lr100 ret <2 x i32> <i32 0, i32 65280>101}102 103define arm_aapcs_vfpcc <2 x i32> @vmov_i32_d() {104; CHECK-LE-LABEL: vmov_i32_d:105; CHECK-LE: @ %bb.0:106; CHECK-LE-NEXT: vmov.i64 d0, #0xff000000000000107; CHECK-LE-NEXT: bx lr108;109; CHECK-BE-LABEL: vmov_i32_d:110; CHECK-BE: @ %bb.0:111; CHECK-BE-NEXT: vmov.i64 d16, #0xff000000000000112; CHECK-BE-NEXT: vrev64.32 d0, d16113; CHECK-BE-NEXT: bx lr114 ret <2 x i32> <i32 0, i32 16711680>115}116 117define arm_aapcs_vfpcc <2 x i32> @vmov_i32_e() {118; CHECK-LE-LABEL: vmov_i32_e:119; CHECK-LE: @ %bb.0:120; CHECK-LE-NEXT: vmov.i64 d0, #0xff00000000000000121; CHECK-LE-NEXT: bx lr122;123; CHECK-BE-LABEL: vmov_i32_e:124; CHECK-BE: @ %bb.0:125; CHECK-BE-NEXT: vmov.i64 d16, #0xff00000000000000126; CHECK-BE-NEXT: vrev64.32 d0, d16127; CHECK-BE-NEXT: bx lr128 ret <2 x i32> <i32 0, i32 4278190080>129}130 131define arm_aapcs_vfpcc <1 x i64> @vmov_i64_a() {132; CHECK-LABEL: vmov_i64_a:133; CHECK: @ %bb.0:134; CHECK-NEXT: vmov.i8 d0, #0xff135; CHECK-NEXT: bx lr136 ret <1 x i64> <i64 -1>137}138 139define arm_aapcs_vfpcc <1 x i64> @vmov_i64_b() {140; CHECK-LE-LABEL: vmov_i64_b:141; CHECK-LE: @ %bb.0:142; CHECK-LE-NEXT: vmov.i64 d0, #0xffff00ff0000ff143; CHECK-LE-NEXT: bx lr144;145; CHECK-BE-LABEL: vmov_i64_b:146; CHECK-BE: @ %bb.0:147; CHECK-BE-NEXT: vmov.i64 d16, #0xff0000ff00ffff00148; CHECK-BE-NEXT: vrev64.32 d0, d16149; CHECK-BE-NEXT: bx lr150 ret <1 x i64> <i64 72056498804490495>151}152 153define arm_aapcs_vfpcc <2 x i64> @vmov_v2i64_b() {154; CHECK-LABEL: vmov_v2i64_b:155; CHECK: @ %bb.0:156; CHECK-NEXT: vmov.i64 q0, #0xffff00ff0000ff157; CHECK-NEXT: bx lr158 ret <2 x i64> <i64 72056498804490495, i64 72056498804490495>159}160 161define arm_aapcs_vfpcc <4 x i32> @vmov_v4i32_b() {162; CHECK-LE-LABEL: vmov_v4i32_b:163; CHECK-LE: @ %bb.0:164; CHECK-LE-NEXT: vmov.i64 q0, #0xff0000ff00ffff00165; CHECK-LE-NEXT: bx lr166;167; CHECK-BE-LABEL: vmov_v4i32_b:168; CHECK-BE: @ %bb.0:169; CHECK-BE-NEXT: vmov.i64 q0, #0xffff00ff0000ff170; CHECK-BE-NEXT: bx lr171 ret <4 x i32> <i32 u0xffff00, i32 u0xff0000ff, i32 u0xffff00, i32 u0xff0000ff>172}173 174define arm_aapcs_vfpcc <2 x i64> @and_v2i64_b(<2 x i64> %a) {175; CHECK-LE-LABEL: and_v2i64_b:176; CHECK-LE: @ %bb.0:177; CHECK-LE-NEXT: vmov.i64 q8, #0xffff00ff0000ff178; CHECK-LE-NEXT: vand q0, q0, q8179; CHECK-LE-NEXT: bx lr180;181; CHECK-BE-LABEL: and_v2i64_b:182; CHECK-BE: @ %bb.0:183; CHECK-BE-NEXT: vmov.i64 q8, #0xff0000ff00ffff00184; CHECK-BE-NEXT: vrev64.32 q8, q8185; CHECK-BE-NEXT: vand q0, q0, q8186; CHECK-BE-NEXT: bx lr187 %b = and <2 x i64> %a, <i64 72056498804490495, i64 72056498804490495>188 ret <2 x i64> %b189}190 191define arm_aapcs_vfpcc <4 x i32> @and_v4i32_b(<4 x i32> %a) {192; CHECK-LE-LABEL: and_v4i32_b:193; CHECK-LE: @ %bb.0:194; CHECK-LE-NEXT: vmov.i64 q8, #0xff0000ff00ffff00195; CHECK-LE-NEXT: vand q0, q0, q8196; CHECK-LE-NEXT: bx lr197;198; CHECK-BE-LABEL: and_v4i32_b:199; CHECK-BE: @ %bb.0:200; CHECK-BE-NEXT: vmov.i64 q8, #0xff0000ff00ffff00201; CHECK-BE-NEXT: vrev64.32 q9, q0202; CHECK-BE-NEXT: vand q8, q9, q8203; CHECK-BE-NEXT: vrev64.32 q0, q8204; CHECK-BE-NEXT: bx lr205 %b = and <4 x i32> %a, <i32 u0xffff00, i32 u0xff0000ff, i32 u0xffff00, i32 u0xff0000ff>206 ret <4 x i32> %b207}208 209define arm_aapcs_vfpcc <8 x i16> @vmvn_v16i8_m1() {210; CHECK-LE-LABEL: vmvn_v16i8_m1:211; CHECK-LE: @ %bb.0:212; CHECK-LE-NEXT: vmvn.i32 q0, #0x10000213; CHECK-LE-NEXT: bx lr214;215; CHECK-BE-LABEL: vmvn_v16i8_m1:216; CHECK-BE: @ %bb.0:217; CHECK-BE-NEXT: vmvn.i32 q0, #0x1218; CHECK-BE-NEXT: bx lr219 ret <8 x i16> <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>220}221 222define arm_aapcs_vfpcc <8 x i16> @and_v8i16_m1(<8 x i16> %a) {223; CHECK-LE-LABEL: and_v8i16_m1:224; CHECK-LE: @ %bb.0:225; CHECK-LE-NEXT: vbic.i32 q0, #0x10000226; CHECK-LE-NEXT: bx lr227;228; CHECK-BE-LABEL: and_v8i16_m1:229; CHECK-BE: @ %bb.0:230; CHECK-BE-NEXT: vrev64.16 q8, q0231; CHECK-BE-NEXT: vbic.i32 q8, #0x10000232; CHECK-BE-NEXT: vrev64.16 q0, q8233; CHECK-BE-NEXT: bx lr234 %b = and <8 x i16> %a, <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>235 ret <8 x i16> %b236}237 238define arm_aapcs_vfpcc <8 x i16> @or_v8i16_1(<8 x i16> %a) {239; CHECK-LE-LABEL: or_v8i16_1:240; CHECK-LE: @ %bb.0:241; CHECK-LE-NEXT: vorr.i32 q0, #0x10000242; CHECK-LE-NEXT: bx lr243;244; CHECK-BE-LABEL: or_v8i16_1:245; CHECK-BE: @ %bb.0:246; CHECK-BE-NEXT: vrev64.16 q8, q0247; CHECK-BE-NEXT: vorr.i32 q8, #0x10000248; CHECK-BE-NEXT: vrev64.16 q0, q8249; CHECK-BE-NEXT: bx lr250 %b = or <8 x i16> %a, <i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1>251 ret <8 x i16> %b252}253 254define arm_aapcs_vfpcc <8 x i16> @xor_v8i16_m1(<8 x i16> %a) {255; CHECK-LE-LABEL: xor_v8i16_m1:256; CHECK-LE: @ %bb.0:257; CHECK-LE-NEXT: vmvn.i32 q8, #0x10000258; CHECK-LE-NEXT: veor q0, q0, q8259; CHECK-LE-NEXT: bx lr260;261; CHECK-BE-LABEL: xor_v8i16_m1:262; CHECK-BE: @ %bb.0:263; CHECK-BE-NEXT: vmvn.i32 q8, #0x10000264; CHECK-BE-NEXT: vrev64.16 q9, q0265; CHECK-BE-NEXT: veor q8, q9, q8266; CHECK-BE-NEXT: vrev64.16 q0, q8267; CHECK-BE-NEXT: bx lr268 %b = xor <8 x i16> %a, <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>269 ret <8 x i16> %b270}271