69 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=arm-eabi -mattr=neon | FileCheck %s3 4define i32 @sext_inc(i1 zeroext %x) {5; CHECK-LABEL: sext_inc:6; CHECK: @ %bb.0:7; CHECK-NEXT: eor r0, r0, #18; CHECK-NEXT: mov pc, lr9 %ext = sext i1 %x to i3210 %add = add i32 %ext, 111 ret i32 %add12}13 14define <4 x i32> @sext_inc_vec(<4 x i1> %x) {15; CHECK-LABEL: sext_inc_vec:16; CHECK: @ %bb.0:17; CHECK-NEXT: vmov.i16 d16, #0x118; CHECK-NEXT: vmov d17, r0, r119; CHECK-NEXT: veor d16, d17, d1620; CHECK-NEXT: vmov.i32 q9, #0x121; CHECK-NEXT: vmovl.u16 q8, d1622; CHECK-NEXT: vand q8, q8, q923; CHECK-NEXT: vmov r0, r1, d1624; CHECK-NEXT: vmov r2, r3, d1725; CHECK-NEXT: mov pc, lr26 %ext = sext <4 x i1> %x to <4 x i32>27 %add = add <4 x i32> %ext, <i32 1, i32 1, i32 1, i32 1>28 ret <4 x i32> %add29}30 31define <4 x i32> @cmpgt_sext_inc_vec(<4 x i32> %x, <4 x i32> %y) {32; CHECK-LABEL: cmpgt_sext_inc_vec:33; CHECK: @ %bb.0:34; CHECK-NEXT: vmov d17, r2, r335; CHECK-NEXT: vmov d16, r0, r136; CHECK-NEXT: mov r0, sp37; CHECK-NEXT: vld1.64 {d18, d19}, [r0]38; CHECK-NEXT: vcge.s32 q8, q9, q839; CHECK-NEXT: vmov.i32 q9, #0x140; CHECK-NEXT: vand q8, q8, q941; CHECK-NEXT: vmov r0, r1, d1642; CHECK-NEXT: vmov r2, r3, d1743; CHECK-NEXT: mov pc, lr44 %cmp = icmp sgt <4 x i32> %x, %y45 %ext = sext <4 x i1> %cmp to <4 x i32>46 %add = add <4 x i32> %ext, <i32 1, i32 1, i32 1, i32 1>47 ret <4 x i32> %add48}49 50define <4 x i32> @cmpne_sext_inc_vec(<4 x i32> %x, <4 x i32> %y) {51; CHECK-LABEL: cmpne_sext_inc_vec:52; CHECK: @ %bb.0:53; CHECK-NEXT: vmov d17, r2, r354; CHECK-NEXT: mov r12, sp55; CHECK-NEXT: vld1.64 {d18, d19}, [r12]56; CHECK-NEXT: vmov d16, r0, r157; CHECK-NEXT: vceq.i32 q8, q8, q958; CHECK-NEXT: vmov.i32 q9, #0x159; CHECK-NEXT: vand q8, q8, q960; CHECK-NEXT: vmov r0, r1, d1661; CHECK-NEXT: vmov r2, r3, d1762; CHECK-NEXT: mov pc, lr63 %cmp = icmp ne <4 x i32> %x, %y64 %ext = sext <4 x i1> %cmp to <4 x i32>65 %add = add <4 x i32> %ext, <i32 1, i32 1, i32 1, i32 1>66 ret <4 x i32> %add67}68 69