85 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 62; RUN: llc -mtriple=armv6t2-eabi %s -o - | FileCheck %s3 4define i64 @f1(i64 %a, i64 %b) {5; CHECK-LABEL: f1:6; CHECK: @ %bb.0: @ %entry7; CHECK-NEXT: subs r0, r0, r28; CHECK-NEXT: sbc r1, r1, r39; CHECK-NEXT: bx lr10entry:11 %tmp = sub i64 %a, %b12 ret i64 %tmp13}14 15define i64 @f2(i64 %a, i64 %b) {16; CHECK-LABEL: f2:17; CHECK: @ %bb.0: @ %entry18; CHECK-NEXT: lsl r1, r1, #119; CHECK-NEXT: orr r1, r1, r0, lsr #3120; CHECK-NEXT: rsbs r0, r2, r0, lsl #121; CHECK-NEXT: sbc r1, r1, r322; CHECK-NEXT: bx lr23entry:24 %tmp1 = shl i64 %a, 125 %tmp2 = sub i64 %tmp1, %b26 ret i64 %tmp227}28 29; add with live carry30define i64 @f3(i32 %al, i32 %bl) {31; CHECK-LABEL: f3:32; CHECK: @ %bb.0: @ %entry33; CHECK-NEXT: adds r0, r0, r134; CHECK-NEXT: mov r2, #035; CHECK-NEXT: adcs r0, r1, #036; CHECK-NEXT: adc r1, r2, #037; CHECK-NEXT: bx lr38entry:39 ; unsigned wide add40 %aw = zext i32 %al to i6441 %bw = zext i32 %bl to i6442 %cw = add i64 %aw, %bw43 ; ch == carry bit44 %ch = lshr i64 %cw, 3245 %dw = add i64 %ch, %bw46 ret i64 %dw47}48 49; rdar://1007374550define i64 @f4(i64 %x) nounwind readnone {51; CHECK-LABEL: f4:52; CHECK: @ %bb.0: @ %entry53; CHECK-NEXT: rsbs r0, r0, #054; CHECK-NEXT: rsc r1, r1, #055; CHECK-NEXT: bx lr56entry:57 %0 = sub nsw i64 0, %x58 ret i64 %059}60 61; rdar://1255938562define i64 @f5(i32 %vi) {63; CHECK-LABEL: f5:64; CHECK: @ %bb.0: @ %entry65; CHECK-NEXT: movw r1, #1949366; CHECK-NEXT: movw r2, #2943367; CHECK-NEXT: movt r1, #5719168; CHECK-NEXT: eor r0, r0, r169; CHECK-NEXT: movw r3, #4604370; CHECK-NEXT: movt r2, #6553571; CHECK-NEXT: adds r0, r0, r072; CHECK-NEXT: movw r1, #3610273; CHECK-NEXT: sbc r2, r2, r174; CHECK-NEXT: movt r3, #834475; CHECK-NEXT: adds r0, r0, r376; CHECK-NEXT: adc r1, r2, r177; CHECK-NEXT: bx lr78entry:79 %v0 = zext i32 %vi to i6480 %v1 = xor i64 %v0, -15505745619861981 %v4 = add i64 %v1, 15505745619861982 %v5 = add i64 %v4, %v183 ret i64 %v584}85