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1; RUN: llc -mtriple=armv5 %s -o - | FileCheck %s2 3; CHECK: eor [[T:r[0-9]+]], [[T]], [[T]], asr #314; CHECK-NEXT: mov [[C1:r[0-9]+]], #15; CHECK-NEXT: orr [[T]], [[C1]], [[T]], lsl #16; CHECK-NEXT: clz [[T]], [[T]]7define i32 @cls(i32 %t) {8 %cls.i = call i32 @llvm.arm.cls(i32 %t)9 ret i32 %cls.i10}11 12; CHECK: cmp r1, #013; CHECK: mvnne [[ADJUSTEDLO:r[0-9]+]], r014; CHECK: clz [[CLZLO:r[0-9]+]], [[ADJUSTEDLO]]15; CHECK: eor [[A:r[0-9]+]], r1, r1, asr #3116; CHECK: mov r1, #117; CHECK: orr [[A]], r1, [[A]], lsl #118; CHECK: clz [[CLSHI:r[0-9]+]], [[A]]19; CHECK: cmp [[CLSHI]], #3120; CHECK: addeq r0, [[CLZLO]], #3121define i32 @cls64(i64 %t) {22 %cls.i = call i32 @llvm.arm.cls64(i64 %t)23 ret i32 %cls.i24}25 26declare i32 @llvm.arm.cls(i32) nounwind27declare i32 @llvm.arm.cls64(i64) nounwind28