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1; RUN: llc -mtriple=armv7 %s -o - | FileCheck %s2; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s --check-prefix=CHECK-T23 4define i1 @f1(i32 %a, i32 %b) {5; CHECK-LABEL: f1:6; CHECK: subs r0, r0, r17; CHECK: movwne r0, #18; CHECK-T2: subs r0, r0, r19; CHECK-T2: it ne10; CHECK-T2: movne r0, #111 %tmp = icmp ne i32 %a, %b12 ret i1 %tmp13}14 15define i1 @f2(i32 %a, i32 %b) {16; CHECK-LABEL: f2:17; CHECK: sub r0, r0, r118; CHECK: clz r0, r019; CHECK: lsr r0, r0, #520; CHECK-T2: subs r0, r0, r121; CHECK-T2: clz r0, r022; CHECK-T2: lsrs r0, r0, #523 %tmp = icmp eq i32 %a, %b24 ret i1 %tmp25}26 27define i1 @f6(i32 %a, i32 %b) {28; CHECK-LABEL: f6:29; CHECK: sub r0, r0, r1, lsl #530; CHECK: clz r0, r031; CHECK: lsr r0, r0, #532; CHECK-T2: sub.w r0, r0, r1, lsl #533; CHECK-T2: clz r0, r034; CHECK-T2: lsrs r0, r0, #535 %tmp = shl i32 %b, 536 %tmp1 = icmp eq i32 %a, %tmp37 ret i1 %tmp138}39 40define i1 @f7(i32 %a, i32 %b) {41; CHECK-LABEL: f7:42; CHECK: subs r0, r0, r1, lsr #643; CHECK: movwne r0, #144; CHECK-T2: subs.w r0, r0, r1, lsr #645; CHECK-T2: it ne46; CHECK-T2: movne r0, #147 %tmp = lshr i32 %b, 648 %tmp1 = icmp ne i32 %a, %tmp49 ret i1 %tmp150}51 52define i1 @f8(i32 %a, i32 %b) {53; CHECK-LABEL: f8:54; CHECK: sub r0, r0, r1, asr #755; CHECK: clz r0, r056; CHECK: lsr r0, r0, #557; CHECK-T2: sub.w r0, r0, r1, asr #758; CHECK-T2: clz r0, r059; CHECK-T2: lsrs r0, r0, #560 %tmp = ashr i32 %b, 761 %tmp1 = icmp eq i32 %a, %tmp62 ret i1 %tmp163}64 65define i1 @f9(i32 %a) {66; CHECK-LABEL: f9:67; CHECK: subs r0, r0, r0, ror #868; CHECK: movwne r0, #169; CHECK-T2: subs.w r0, r0, r0, ror #870; CHECK-T2: it ne71; CHECK-T2: movne r0, #172 %l8 = shl i32 %a, 2473 %r8 = lshr i32 %a, 874 %tmp = or i32 %l8, %r875 %tmp1 = icmp ne i32 %a, %tmp76 ret i1 %tmp177}78 79; CHECK-LABEL: swap_cmp_shl80; CHECK: mov r2, #081; CHECK: cmp r1, r0, lsl #1182; CHECK: movwlt r2, #183; CHECK-T2: mov{{.*}} r2, #084; CHECK-T2: cmp.w r1, r0, lsl #1185; CHECK-T2: movlt r2, #186define arm_aapcscc i32 @swap_cmp_shl(i32 %a, i32 %b) {87entry:88 %shift = shl i32 %a, 1189 %cmp = icmp sgt i32 %shift, %b90 %conv = zext i1 %cmp to i3291 ret i32 %conv92}93 94; CHECK-LABEL: swap_cmp_lshr95; CHECK: mov r2, #096; CHECK: cmp r1, r0, lsr #1197; CHECK: movwhi r2, #198; CHECK-T2: mov{{.*}} r2, #099; CHECK-T2: cmp.w r1, r0, lsr #11100; CHECK-T2: movhi r2, #1101define arm_aapcscc i32 @swap_cmp_lshr(i32 %a, i32 %b) {102entry:103 %shift = lshr i32 %a, 11104 %cmp = icmp ult i32 %shift, %b105 %conv = zext i1 %cmp to i32106 ret i32 %conv107}108 109; CHECK-LABEL: swap_cmp_ashr110; CHECK: mov r2, #0111; CHECK: cmp r1, r0, asr #11112; CHECK: movwle r2, #1113; CHECK-T2: mov{{.*}} r2, #0114; CHECK-T2: cmp.w r1, r0, asr #11115; CHECK-T2: movle r2, #1116define arm_aapcscc i32 @swap_cmp_ashr(i32 %a, i32 %b) {117entry:118 %shift = ashr i32 %a, 11119 %cmp = icmp sge i32 %shift, %b120 %conv = zext i1 %cmp to i32121 ret i32 %conv122}123 124; CHECK-LABEL: swap_cmp_rotr125; CHECK: mov r2, #0126; CHECK: cmp r1, r0, ror #11127; CHECK: movwls r2, #1128; CHECK-T2: mov{{.*}} r2, #0129; CHECK-T2: cmp.w r1, r0, ror #11130; CHECK-T2: movls r2, #1131define arm_aapcscc i32 @swap_cmp_rotr(i32 %a, i32 %b) {132entry:133 %lsr = lshr i32 %a, 11134 %lsl = shl i32 %a, 21135 %ror = or i32 %lsr, %lsl136 %cmp = icmp uge i32 %ror, %b137 %conv = zext i1 %cmp to i32138 ret i32 %conv139}140