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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s3# RUN: llc -passes=peephole-opt %s -o - | FileCheck %s4 5--- |6 ; ModuleID = '<stdin>'7 source_filename = "<stdin>"8 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"9 target triple = "thumb-none--eabi"10 11 define i32 @f(i32 %a, i32 %b) {12 entry:13 %mul = mul nsw i32 %b, %a14 %cmp = icmp eq i32 %mul, 015 %conv = zext i1 %cmp to i3216 ret i32 %conv17 }18 19...20---21name: f22alignment: 223exposesReturnsTwice: false24legalized: false25regBankSelected: false26selected: false27tracksRegLiveness: true28registers:29 - { id: 0, class: tgpr }30 - { id: 1, class: tgpr }31 - { id: 2, class: tgpr }32 - { id: 3, class: tgpr }33 - { id: 4, class: tgpr }34 - { id: 5, class: tgpr }35liveins:36 - { reg: '$r0', virtual-reg: '%0' }37 - { reg: '$r1', virtual-reg: '%1' }38frameInfo:39 isFrameAddressTaken: false40 isReturnAddressTaken: false41 hasStackMap: false42 hasPatchPoint: false43 stackSize: 044 offsetAdjustment: 045 maxAlignment: 046 adjustsStack: false47 hasCalls: false48 maxCallFrameSize: 049 hasOpaqueSPAdjustment: false50 hasVAStart: false51 hasMustTailInVarArgFunc: false52 53body: |54 ; CHECK-LABEL: name: f55 ; CHECK: bb.0.entry:56 ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)57 ; CHECK: liveins: $r0, $r158 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r159 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r060 ; CHECK: %3:tgpr, $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg61 ; CHECK: %4:tgpr, $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg62 ; CHECK: %2:tgpr, $cpsr = tMUL [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg63 ; CHECK: tBcc %bb.2, 0 /* CC::eq */, $cpsr64 ; CHECK: bb.1.entry:65 ; CHECK: successors: %bb.2(0x80000000)66 ; CHECK: bb.2.entry:67 ; CHECK: [[PHI:%[0-9]+]]:tgpr = PHI %4, %bb.1, %3, %bb.068 ; CHECK: $r0 = COPY [[PHI]]69 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r070 bb.0.entry:71 liveins: $r0, $r172 73 %1 = COPY $r174 %0 = COPY $r075 %2, $cpsr = tMUL %1, %0, 14, $noreg76 %3, $cpsr = tMOVi8 1, 14, $noreg77 %4, $cpsr = tMOVi8 0, 14, $noreg78 tCMPi8 killed %2, 0, 14, $noreg, implicit-def $cpsr79 tBcc %bb.2.entry, 0, $cpsr80 81 bb.1.entry:82 83 bb.2.entry:84 %5 = PHI %4, %bb.1.entry, %3, %bb.0.entry85 $r0 = COPY %586 tBX_RET 14, $noreg, implicit $r087 88...89