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1# RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s2 3# Here we check that the peephole cmp rewrite is not triggered, because4# there is store instruction between the tMUL and tCMP, i.e. there are5# no constants to reorder.6 7--- |8 ; ModuleID = 'cmp2-peephole-thumb.ll'9 source_filename = "<stdin>"10 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"11 target triple = "thumb-none--eabi"12 13 define i32 @g(i32 %a, i32 %b) {14 entry:15 %retval = alloca i32, align 416 %mul = alloca i32, align 417 %mul1 = mul nsw i32 %a, %b18 store i32 %mul1, ptr %mul, align 419 %0 = load i32, ptr %mul, align 420 %cmp = icmp sle i32 %0, 021 br i1 %cmp, label %if.then, label %if.end22 23 if.then: ; preds = %entry24 store i32 42, ptr %retval, align 425 br label %return26 27 if.end: ; preds = %entry28 store i32 1, ptr %retval, align 429 br label %return30 31 return: ; preds = %if.end, %if.then32 %1 = load i32, ptr %retval, align 433 ret i32 %134 }35 36...37---38name: g39# CHECK-LABEL: name: g40alignment: 241exposesReturnsTwice: false42legalized: false43regBankSelected: false44selected: false45tracksRegLiveness: true46registers:47 - { id: 0, class: tgpr }48 - { id: 1, class: tgpr }49 - { id: 2, class: tgpr }50 - { id: 3, class: tgpr }51 - { id: 4, class: tgpr }52 - { id: 5, class: tgpr }53liveins:54 - { reg: '$r0', virtual-reg: '%0' }55 - { reg: '$r1', virtual-reg: '%1' }56frameInfo:57 isFrameAddressTaken: false58 isReturnAddressTaken: false59 hasStackMap: false60 hasPatchPoint: false61 stackSize: 062 offsetAdjustment: 063 maxAlignment: 464 adjustsStack: false65 hasCalls: false66 maxCallFrameSize: 067 hasOpaqueSPAdjustment: false68 hasVAStart: false69 hasMustTailInVarArgFunc: false70stack:71 - { id: 0, name: retval, offset: 0, size: 4, alignment: 4, local-offset: -4 }72 - { id: 1, name: mul, offset: 0, size: 4, alignment: 4, local-offset: -8 }73 74# CHECK: tMUL75# CHECK-NEXT: tSTRspi76# CHECK-NEXT: tCMPi877body: |78 bb.0.entry:79 liveins: $r0, $r180 81 %1 = COPY $r182 %0 = COPY $r083 %2, $cpsr = tMUL %0, %1, 14, $noreg84 tSTRspi %2, %stack.1.mul, 0, 14, $noreg :: (store (s32) into %ir.mul)85 tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr86 tBcc %bb.2.if.end, 12, $cpsr87 tB %bb.1.if.then, 14, $noreg88 89 bb.1.if.then:90 %4, $cpsr = tMOVi8 42, 14, $noreg91 tSTRspi killed %4, %stack.0.retval, 0, 14, $noreg :: (store (s32) into %ir.retval)92 tB %bb.3.return, 14, $noreg93 94 bb.2.if.end:95 %3, $cpsr = tMOVi8 1, 14, $noreg96 tSTRspi killed %3, %stack.0.retval, 0, 14, $noreg :: (store (s32) into %ir.retval)97 98 bb.3.return:99 %5 = tLDRspi %stack.0.retval, 0, 14, $noreg :: (dereferenceable load (s32) from %ir.retval)100 $r0 = COPY %5101 tBX_RET 14, $noreg, implicit $r0102 103...104