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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc %s -o - -mtriple=thumbv8m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \3; RUN: FileCheck %s --check-prefix=CHECK-V8-LE4; RUN: llc %s -o - -mtriple=thumbebv8m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \5; RUN: FileCheck %s --check-prefix=CHECK-V8-BE6 7; RUN: llc %s -o - -mtriple=thumbv8.1m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \8; RUN: FileCheck %s --check-prefix=CHECK-V81-LE9; RUN: llc %s -o - -mtriple=thumbebv8.1m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \10; RUN: FileCheck %s --check-prefix=CHECK-V81-BE11 12attributes #0 = { nounwind }13attributes #1 = { "cmse_nonsecure_call" nounwind }14 15define void @fidififiddddff(ptr %fu, float %a, i32 %b, double %c, i32 %d, float %e, i32 %f, float %g, i32 %h, double %i, double %j, double %k, double %l, float %m, float %n) #0 {16; CHECK-V8-LE-LABEL: fidififiddddff:17; CHECK-V8-LE: @ %bb.0: @ %entry18; CHECK-V8-LE-NEXT: push {r7, lr}19; CHECK-V8-LE-NEXT: mov lr, r320; CHECK-V8-LE-NEXT: mov r12, r021; CHECK-V8-LE-NEXT: mov r0, r122; CHECK-V8-LE-NEXT: mov r1, r223; CHECK-V8-LE-NEXT: ldr r3, [sp, #8]24; CHECK-V8-LE-NEXT: mov r2, lr25; CHECK-V8-LE-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}26; CHECK-V8-LE-NEXT: bic r12, r12, #127; CHECK-V8-LE-NEXT: sub sp, #13628; CHECK-V8-LE-NEXT: vmov r4, s529; CHECK-V8-LE-NEXT: vmov r11, s030; CHECK-V8-LE-NEXT: vmov r9, r10, d131; CHECK-V8-LE-NEXT: vmov r8, s132; CHECK-V8-LE-NEXT: vmov r7, s433; CHECK-V8-LE-NEXT: vmov r5, r6, d334; CHECK-V8-LE-NEXT: vlstm sp35; CHECK-V8-LE-NEXT: vmov s0, r1136; CHECK-V8-LE-NEXT: vmov d1, r9, r1037; CHECK-V8-LE-NEXT: vmov s1, r838; CHECK-V8-LE-NEXT: vmov s4, r739; CHECK-V8-LE-NEXT: vmov d3, r5, r640; CHECK-V8-LE-NEXT: vmov s5, r441; CHECK-V8-LE-NEXT: vldr d4, [sp, #32]42; CHECK-V8-LE-NEXT: vldr d5, [sp, #40]43; CHECK-V8-LE-NEXT: vldr d6, [sp, #48]44; CHECK-V8-LE-NEXT: vldr s14, [sp, #56]45; CHECK-V8-LE-NEXT: ldr r4, [sp, #64]46; CHECK-V8-LE-NEXT: bic r4, r4, #15947; CHECK-V8-LE-NEXT: bic r4, r4, #402653184048; CHECK-V8-LE-NEXT: vmsr fpscr, r449; CHECK-V8-LE-NEXT: msr apsr_nzcvqg, r1250; CHECK-V8-LE-NEXT: blxns r1251; CHECK-V8-LE-NEXT: vlldm sp52; CHECK-V8-LE-NEXT: add sp, #13653; CHECK-V8-LE-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}54; CHECK-V8-LE-NEXT: pop {r7, pc}55;56; CHECK-V8-BE-LABEL: fidififiddddff:57; CHECK-V8-BE: @ %bb.0: @ %entry58; CHECK-V8-BE-NEXT: push {r7, lr}59; CHECK-V8-BE-NEXT: mov lr, r360; CHECK-V8-BE-NEXT: mov r12, r061; CHECK-V8-BE-NEXT: mov r0, r162; CHECK-V8-BE-NEXT: mov r1, r263; CHECK-V8-BE-NEXT: ldr r3, [sp, #8]64; CHECK-V8-BE-NEXT: mov r2, lr65; CHECK-V8-BE-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}66; CHECK-V8-BE-NEXT: bic r12, r12, #167; CHECK-V8-BE-NEXT: sub sp, #13668; CHECK-V8-BE-NEXT: vmov r4, s569; CHECK-V8-BE-NEXT: vmov r11, s070; CHECK-V8-BE-NEXT: vmov r9, r10, d171; CHECK-V8-BE-NEXT: vmov r8, s172; CHECK-V8-BE-NEXT: vmov r7, s473; CHECK-V8-BE-NEXT: vmov r5, r6, d374; CHECK-V8-BE-NEXT: vlstm sp75; CHECK-V8-BE-NEXT: vmov s0, r1176; CHECK-V8-BE-NEXT: vmov d1, r9, r1077; CHECK-V8-BE-NEXT: vmov s1, r878; CHECK-V8-BE-NEXT: vmov s4, r779; CHECK-V8-BE-NEXT: vmov d3, r5, r680; CHECK-V8-BE-NEXT: vmov s5, r481; CHECK-V8-BE-NEXT: vldr s8, [sp, #32]82; CHECK-V8-BE-NEXT: vldr s9, [sp, #36]83; CHECK-V8-BE-NEXT: vldr s10, [sp, #40]84; CHECK-V8-BE-NEXT: vldr s11, [sp, #44]85; CHECK-V8-BE-NEXT: vldr s12, [sp, #48]86; CHECK-V8-BE-NEXT: vldr s13, [sp, #52]87; CHECK-V8-BE-NEXT: vldr s14, [sp, #56]88; CHECK-V8-BE-NEXT: ldr r4, [sp, #64]89; CHECK-V8-BE-NEXT: bic r4, r4, #15990; CHECK-V8-BE-NEXT: bic r4, r4, #402653184091; CHECK-V8-BE-NEXT: vmsr fpscr, r492; CHECK-V8-BE-NEXT: msr apsr_nzcvqg, r1293; CHECK-V8-BE-NEXT: blxns r1294; CHECK-V8-BE-NEXT: vlldm sp95; CHECK-V8-BE-NEXT: add sp, #13696; CHECK-V8-BE-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}97; CHECK-V8-BE-NEXT: pop {r7, pc}98;99; CHECK-V81-LE-LABEL: fidififiddddff:100; CHECK-V81-LE: @ %bb.0: @ %entry101; CHECK-V81-LE-NEXT: push {r7, lr}102; CHECK-V81-LE-NEXT: mov lr, r3103; CHECK-V81-LE-NEXT: mov r12, r0104; CHECK-V81-LE-NEXT: mov r0, r1105; CHECK-V81-LE-NEXT: mov r1, r2106; CHECK-V81-LE-NEXT: ldr r3, [sp, #8]107; CHECK-V81-LE-NEXT: mov r2, lr108; CHECK-V81-LE-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}109; CHECK-V81-LE-NEXT: bic r12, r12, #1110; CHECK-V81-LE-NEXT: vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}111; CHECK-V81-LE-NEXT: vscclrm {s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}112; CHECK-V81-LE-NEXT: vstr fpcxts, [sp, #-8]!113; CHECK-V81-LE-NEXT: clrm {r4, r5, r6, r7, r8, r9, r10, r11, apsr}114; CHECK-V81-LE-NEXT: blxns r12115; CHECK-V81-LE-NEXT: vldr fpcxts, [sp], #8116; CHECK-V81-LE-NEXT: vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}117; CHECK-V81-LE-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}118; CHECK-V81-LE-NEXT: pop {r7, pc}119;120; CHECK-V81-BE-LABEL: fidififiddddff:121; CHECK-V81-BE: @ %bb.0: @ %entry122; CHECK-V81-BE-NEXT: push {r7, lr}123; CHECK-V81-BE-NEXT: mov lr, r3124; CHECK-V81-BE-NEXT: mov r12, r0125; CHECK-V81-BE-NEXT: mov r0, r1126; CHECK-V81-BE-NEXT: mov r1, r2127; CHECK-V81-BE-NEXT: ldr r3, [sp, #8]128; CHECK-V81-BE-NEXT: mov r2, lr129; CHECK-V81-BE-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}130; CHECK-V81-BE-NEXT: bic r12, r12, #1131; CHECK-V81-BE-NEXT: vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}132; CHECK-V81-BE-NEXT: vscclrm {s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}133; CHECK-V81-BE-NEXT: vstr fpcxts, [sp, #-8]!134; CHECK-V81-BE-NEXT: clrm {r4, r5, r6, r7, r8, r9, r10, r11, apsr}135; CHECK-V81-BE-NEXT: blxns r12136; CHECK-V81-BE-NEXT: vldr fpcxts, [sp], #8137; CHECK-V81-BE-NEXT: vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}138; CHECK-V81-BE-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}139; CHECK-V81-BE-NEXT: pop {r7, pc}140entry:141 call void %fu(float %a, i32 %b, double %c, i32 %d, float %e, i32 %f, float %g, i32 %h, double %i, double %j, double %k, double %l, float %m, float %n) #1142 ret void143}144 145