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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc %s -o - -mtriple=thumbv8m.main -mattr=+fp-armv8d16sp,+dsp | \3; RUN: FileCheck %s --check-prefix=CHECK-8M --check-prefix=CHECK-8M-LE4; RUN: llc %s -o - -mtriple=thumbebv8m.main -mattr=+fp-armv8d16sp,+dsp | \5; RUN: FileCheck %s --check-prefix=CHECK-8M --check-prefix=CHECK-8M-BE6 7; RUN: llc %s -o - -mtriple=thumbv8.1m.main -mattr=+fp-armv8d16sp,+dsp | \8; RUN: FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-LE9; RUN: llc %s -o - -mtriple=thumbebv8.1m.main -mattr=+fp-armv8d16sp,+dsp | \10; RUN: FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-BE11; RUN: llc %s -o - -mtriple=thumbv8.1m.main -mattr=+mve | \12; RUN: FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-LE13; RUN: llc %s -o - -mtriple=thumbebv8.1m.main -mattr=+mve | \14; RUN: FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-BE15 16define float @f1(ptr nocapture %fptr) #0 {17; CHECK-8M-LABEL: f1:18; CHECK-8M: @ %bb.0: @ %entry19; CHECK-8M-NEXT: push {r7, lr}20; CHECK-8M-NEXT: mov r1, r021; CHECK-8M-NEXT: movs r0, #022; CHECK-8M-NEXT: movt r0, #1667223; CHECK-8M-NEXT: blx r124; CHECK-8M-NEXT: pop.w {r7, lr}25; CHECK-8M-NEXT: mrs r12, control26; CHECK-8M-NEXT: tst.w r12, #827; CHECK-8M-NEXT: beq .LBB0_228; CHECK-8M-NEXT: @ %bb.1: @ %entry29; CHECK-8M-NEXT: vmrs r12, fpscr30; CHECK-8M-NEXT: vmov d0, lr, lr31; CHECK-8M-NEXT: vmov d1, lr, lr32; CHECK-8M-NEXT: vmov d2, lr, lr33; CHECK-8M-NEXT: vmov d3, lr, lr34; CHECK-8M-NEXT: vmov d4, lr, lr35; CHECK-8M-NEXT: vmov d5, lr, lr36; CHECK-8M-NEXT: vmov d6, lr, lr37; CHECK-8M-NEXT: vmov d7, lr, lr38; CHECK-8M-NEXT: bic r12, r12, #15939; CHECK-8M-NEXT: bic r12, r12, #402653184040; CHECK-8M-NEXT: vmsr fpscr, r1241; CHECK-8M-NEXT: .LBB0_2: @ %entry42; CHECK-8M-NEXT: mov r1, lr43; CHECK-8M-NEXT: mov r2, lr44; CHECK-8M-NEXT: mov r3, lr45; CHECK-8M-NEXT: mov r12, lr46; CHECK-8M-NEXT: msr apsr_nzcvqg, lr47; CHECK-8M-NEXT: bxns lr48;49; CHECK-81M-LABEL: f1:50; CHECK-81M: @ %bb.0: @ %entry51; CHECK-81M-NEXT: vstr fpcxtns, [sp, #-4]!52; CHECK-81M-NEXT: push {r7, lr}53; CHECK-81M-NEXT: sub sp, #454; CHECK-81M-NEXT: mov r1, r055; CHECK-81M-NEXT: movs r0, #056; CHECK-81M-NEXT: movt r0, #1667257; CHECK-81M-NEXT: blx r158; CHECK-81M-NEXT: add sp, #459; CHECK-81M-NEXT: pop.w {r7, lr}60; CHECK-81M-NEXT: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}61; CHECK-81M-NEXT: vldr fpcxtns, [sp], #462; CHECK-81M-NEXT: clrm {r1, r2, r3, r12, apsr}63; CHECK-81M-NEXT: bxns lr64entry:65 %call = call float %fptr(float 10.0) #166 ret float %call67}68 69attributes #0 = { "cmse_nonsecure_entry" nounwind }70attributes #1 = { nounwind }71 72define double @d1(ptr nocapture %fptr) #0 {73; CHECK-8M-LE-LABEL: d1:74; CHECK-8M-LE: @ %bb.0: @ %entry75; CHECK-8M-LE-NEXT: push {r7, lr}76; CHECK-8M-LE-NEXT: vldr d0, .LCPI1_077; CHECK-8M-LE-NEXT: mov r2, r078; CHECK-8M-LE-NEXT: vmov r0, r1, d079; CHECK-8M-LE-NEXT: blx r280; CHECK-8M-LE-NEXT: pop.w {r7, lr}81; CHECK-8M-LE-NEXT: mrs r12, control82; CHECK-8M-LE-NEXT: tst.w r12, #883; CHECK-8M-LE-NEXT: beq .LBB1_284; CHECK-8M-LE-NEXT: @ %bb.1: @ %entry85; CHECK-8M-LE-NEXT: vmrs r12, fpscr86; CHECK-8M-LE-NEXT: vmov d0, lr, lr87; CHECK-8M-LE-NEXT: vmov d1, lr, lr88; CHECK-8M-LE-NEXT: vmov d2, lr, lr89; CHECK-8M-LE-NEXT: vmov d3, lr, lr90; CHECK-8M-LE-NEXT: vmov d4, lr, lr91; CHECK-8M-LE-NEXT: vmov d5, lr, lr92; CHECK-8M-LE-NEXT: vmov d6, lr, lr93; CHECK-8M-LE-NEXT: vmov d7, lr, lr94; CHECK-8M-LE-NEXT: bic r12, r12, #15995; CHECK-8M-LE-NEXT: bic r12, r12, #402653184096; CHECK-8M-LE-NEXT: vmsr fpscr, r1297; CHECK-8M-LE-NEXT: .LBB1_2: @ %entry98; CHECK-8M-LE-NEXT: mov r2, lr99; CHECK-8M-LE-NEXT: mov r3, lr100; CHECK-8M-LE-NEXT: mov r12, lr101; CHECK-8M-LE-NEXT: msr apsr_nzcvqg, lr102; CHECK-8M-LE-NEXT: bxns lr103; CHECK-8M-LE-NEXT: .p2align 3104; CHECK-8M-LE-NEXT: @ %bb.3:105; CHECK-8M-LE-NEXT: .LCPI1_0:106; CHECK-8M-LE-NEXT: .long 0 @ double 10107; CHECK-8M-LE-NEXT: .long 1076101120108;109; CHECK-8M-BE-LABEL: d1:110; CHECK-8M-BE: @ %bb.0: @ %entry111; CHECK-8M-BE-NEXT: push {r7, lr}112; CHECK-8M-BE-NEXT: vldr d0, .LCPI1_0113; CHECK-8M-BE-NEXT: mov r2, r0114; CHECK-8M-BE-NEXT: vmov r1, r0, d0115; CHECK-8M-BE-NEXT: blx r2116; CHECK-8M-BE-NEXT: pop.w {r7, lr}117; CHECK-8M-BE-NEXT: mrs r12, control118; CHECK-8M-BE-NEXT: tst.w r12, #8119; CHECK-8M-BE-NEXT: beq .LBB1_2120; CHECK-8M-BE-NEXT: @ %bb.1: @ %entry121; CHECK-8M-BE-NEXT: vmrs r12, fpscr122; CHECK-8M-BE-NEXT: vmov d0, lr, lr123; CHECK-8M-BE-NEXT: vmov d1, lr, lr124; CHECK-8M-BE-NEXT: vmov d2, lr, lr125; CHECK-8M-BE-NEXT: vmov d3, lr, lr126; CHECK-8M-BE-NEXT: vmov d4, lr, lr127; CHECK-8M-BE-NEXT: vmov d5, lr, lr128; CHECK-8M-BE-NEXT: vmov d6, lr, lr129; CHECK-8M-BE-NEXT: vmov d7, lr, lr130; CHECK-8M-BE-NEXT: bic r12, r12, #159131; CHECK-8M-BE-NEXT: bic r12, r12, #4026531840132; CHECK-8M-BE-NEXT: vmsr fpscr, r12133; CHECK-8M-BE-NEXT: .LBB1_2: @ %entry134; CHECK-8M-BE-NEXT: mov r2, lr135; CHECK-8M-BE-NEXT: mov r3, lr136; CHECK-8M-BE-NEXT: mov r12, lr137; CHECK-8M-BE-NEXT: msr apsr_nzcvqg, lr138; CHECK-8M-BE-NEXT: bxns lr139; CHECK-8M-BE-NEXT: .p2align 3140; CHECK-8M-BE-NEXT: @ %bb.3:141; CHECK-8M-BE-NEXT: .LCPI1_0:142; CHECK-8M-BE-NEXT: .long 1076101120 @ double 10143; CHECK-8M-BE-NEXT: .long 0144;145; CHECK-81M-LE-LABEL: d1:146; CHECK-81M-LE: @ %bb.0: @ %entry147; CHECK-81M-LE-NEXT: vstr fpcxtns, [sp, #-4]!148; CHECK-81M-LE-NEXT: push {r7, lr}149; CHECK-81M-LE-NEXT: sub sp, #4150; CHECK-81M-LE-NEXT: vldr d0, .LCPI1_0151; CHECK-81M-LE-NEXT: mov r2, r0152; CHECK-81M-LE-NEXT: vmov r0, r1, d0153; CHECK-81M-LE-NEXT: blx r2154; CHECK-81M-LE-NEXT: add sp, #4155; CHECK-81M-LE-NEXT: pop.w {r7, lr}156; CHECK-81M-LE-NEXT: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}157; CHECK-81M-LE-NEXT: vldr fpcxtns, [sp], #4158; CHECK-81M-LE-NEXT: clrm {r2, r3, r12, apsr}159; CHECK-81M-LE-NEXT: bxns lr160; CHECK-81M-LE-NEXT: .p2align 3161; CHECK-81M-LE-NEXT: @ %bb.1:162; CHECK-81M-LE-NEXT: .LCPI1_0:163; CHECK-81M-LE-NEXT: .long 0 @ double 10164; CHECK-81M-LE-NEXT: .long 1076101120165;166; CHECK-81M-BE-LABEL: d1:167; CHECK-81M-BE: @ %bb.0: @ %entry168; CHECK-81M-BE-NEXT: vstr fpcxtns, [sp, #-4]!169; CHECK-81M-BE-NEXT: push {r7, lr}170; CHECK-81M-BE-NEXT: sub sp, #4171; CHECK-81M-BE-NEXT: vldr d0, .LCPI1_0172; CHECK-81M-BE-NEXT: mov r2, r0173; CHECK-81M-BE-NEXT: vmov r1, r0, d0174; CHECK-81M-BE-NEXT: blx r2175; CHECK-81M-BE-NEXT: add sp, #4176; CHECK-81M-BE-NEXT: pop.w {r7, lr}177; CHECK-81M-BE-NEXT: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}178; CHECK-81M-BE-NEXT: vldr fpcxtns, [sp], #4179; CHECK-81M-BE-NEXT: clrm {r2, r3, r12, apsr}180; CHECK-81M-BE-NEXT: bxns lr181; CHECK-81M-BE-NEXT: .p2align 3182; CHECK-81M-BE-NEXT: @ %bb.1:183; CHECK-81M-BE-NEXT: .LCPI1_0:184; CHECK-81M-BE-NEXT: .long 1076101120 @ double 10185; CHECK-81M-BE-NEXT: .long 0186entry:187 %call = call double %fptr(double 10.0) #1188 ret double %call189}190 191define float @f2(ptr nocapture %fptr) #2 {192; CHECK-8M-LABEL: f2:193; CHECK-8M: @ %bb.0: @ %entry194; CHECK-8M-NEXT: push {r7, lr}195; CHECK-8M-NEXT: mov r1, r0196; CHECK-8M-NEXT: movs r0, #0197; CHECK-8M-NEXT: movt r0, #16672198; CHECK-8M-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}199; CHECK-8M-NEXT: bic r1, r1, #1200; CHECK-8M-NEXT: sub sp, #136201; CHECK-8M-NEXT: vlstm sp202; CHECK-8M-NEXT: mov r2, r1203; CHECK-8M-NEXT: mov r3, r1204; CHECK-8M-NEXT: mov r4, r1205; CHECK-8M-NEXT: mov r5, r1206; CHECK-8M-NEXT: mov r6, r1207; CHECK-8M-NEXT: mov r7, r1208; CHECK-8M-NEXT: mov r8, r1209; CHECK-8M-NEXT: mov r9, r1210; CHECK-8M-NEXT: mov r10, r1211; CHECK-8M-NEXT: mov r11, r1212; CHECK-8M-NEXT: mov r12, r1213; CHECK-8M-NEXT: msr apsr_nzcvqg, r1214; CHECK-8M-NEXT: blxns r1215; CHECK-8M-NEXT: vlldm sp216; CHECK-8M-NEXT: add sp, #136217; CHECK-8M-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}218; CHECK-8M-NEXT: pop {r7, pc}219;220; CHECK-81M-LABEL: f2:221; CHECK-81M: @ %bb.0: @ %entry222; CHECK-81M-NEXT: push {r7, lr}223; CHECK-81M-NEXT: mov r1, r0224; CHECK-81M-NEXT: movs r0, #0225; CHECK-81M-NEXT: movt r0, #16672226; CHECK-81M-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}227; CHECK-81M-NEXT: bic r1, r1, #1228; CHECK-81M-NEXT: sub sp, #136229; CHECK-81M-NEXT: vlstm sp230; CHECK-81M-NEXT: clrm {r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}231; CHECK-81M-NEXT: blxns r1232; CHECK-81M-NEXT: vlldm sp233; CHECK-81M-NEXT: add sp, #136234; CHECK-81M-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}235; CHECK-81M-NEXT: pop {r7, pc}236entry:237 %call = call float %fptr(float 10.0) #3238 ret float %call239}240 241attributes #2 = { nounwind }242attributes #3 = { "cmse_nonsecure_call" nounwind }243 244define double @d2(ptr nocapture %fptr) #2 {245; CHECK-8M-LE-LABEL: d2:246; CHECK-8M-LE: @ %bb.0: @ %entry247; CHECK-8M-LE-NEXT: push {r7, lr}248; CHECK-8M-LE-NEXT: vldr d0, .LCPI3_0249; CHECK-8M-LE-NEXT: mov r2, r0250; CHECK-8M-LE-NEXT: vmov r0, r1, d0251; CHECK-8M-LE-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}252; CHECK-8M-LE-NEXT: bic r2, r2, #1253; CHECK-8M-LE-NEXT: sub sp, #136254; CHECK-8M-LE-NEXT: vlstm sp255; CHECK-8M-LE-NEXT: mov r3, r2256; CHECK-8M-LE-NEXT: mov r4, r2257; CHECK-8M-LE-NEXT: mov r5, r2258; CHECK-8M-LE-NEXT: mov r6, r2259; CHECK-8M-LE-NEXT: mov r7, r2260; CHECK-8M-LE-NEXT: mov r8, r2261; CHECK-8M-LE-NEXT: mov r9, r2262; CHECK-8M-LE-NEXT: mov r10, r2263; CHECK-8M-LE-NEXT: mov r11, r2264; CHECK-8M-LE-NEXT: mov r12, r2265; CHECK-8M-LE-NEXT: msr apsr_nzcvqg, r2266; CHECK-8M-LE-NEXT: blxns r2267; CHECK-8M-LE-NEXT: vlldm sp268; CHECK-8M-LE-NEXT: add sp, #136269; CHECK-8M-LE-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}270; CHECK-8M-LE-NEXT: pop {r7, pc}271; CHECK-8M-LE-NEXT: .p2align 3272; CHECK-8M-LE-NEXT: @ %bb.1:273; CHECK-8M-LE-NEXT: .LCPI3_0:274; CHECK-8M-LE-NEXT: .long 0 @ double 10275; CHECK-8M-LE-NEXT: .long 1076101120276;277; CHECK-8M-BE-LABEL: d2:278; CHECK-8M-BE: @ %bb.0: @ %entry279; CHECK-8M-BE-NEXT: push {r7, lr}280; CHECK-8M-BE-NEXT: vldr d0, .LCPI3_0281; CHECK-8M-BE-NEXT: mov r2, r0282; CHECK-8M-BE-NEXT: vmov r1, r0, d0283; CHECK-8M-BE-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}284; CHECK-8M-BE-NEXT: bic r2, r2, #1285; CHECK-8M-BE-NEXT: sub sp, #136286; CHECK-8M-BE-NEXT: vlstm sp287; CHECK-8M-BE-NEXT: mov r3, r2288; CHECK-8M-BE-NEXT: mov r4, r2289; CHECK-8M-BE-NEXT: mov r5, r2290; CHECK-8M-BE-NEXT: mov r6, r2291; CHECK-8M-BE-NEXT: mov r7, r2292; CHECK-8M-BE-NEXT: mov r8, r2293; CHECK-8M-BE-NEXT: mov r9, r2294; CHECK-8M-BE-NEXT: mov r10, r2295; CHECK-8M-BE-NEXT: mov r11, r2296; CHECK-8M-BE-NEXT: mov r12, r2297; CHECK-8M-BE-NEXT: msr apsr_nzcvqg, r2298; CHECK-8M-BE-NEXT: blxns r2299; CHECK-8M-BE-NEXT: vlldm sp300; CHECK-8M-BE-NEXT: add sp, #136301; CHECK-8M-BE-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}302; CHECK-8M-BE-NEXT: pop {r7, pc}303; CHECK-8M-BE-NEXT: .p2align 3304; CHECK-8M-BE-NEXT: @ %bb.1:305; CHECK-8M-BE-NEXT: .LCPI3_0:306; CHECK-8M-BE-NEXT: .long 1076101120 @ double 10307; CHECK-8M-BE-NEXT: .long 0308;309; CHECK-81M-LE-LABEL: d2:310; CHECK-81M-LE: @ %bb.0: @ %entry311; CHECK-81M-LE-NEXT: push {r7, lr}312; CHECK-81M-LE-NEXT: vldr d0, .LCPI3_0313; CHECK-81M-LE-NEXT: mov r2, r0314; CHECK-81M-LE-NEXT: vmov r0, r1, d0315; CHECK-81M-LE-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}316; CHECK-81M-LE-NEXT: bic r2, r2, #1317; CHECK-81M-LE-NEXT: sub sp, #136318; CHECK-81M-LE-NEXT: vlstm sp319; CHECK-81M-LE-NEXT: clrm {r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}320; CHECK-81M-LE-NEXT: blxns r2321; CHECK-81M-LE-NEXT: vlldm sp322; CHECK-81M-LE-NEXT: add sp, #136323; CHECK-81M-LE-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}324; CHECK-81M-LE-NEXT: pop {r7, pc}325; CHECK-81M-LE-NEXT: .p2align 3326; CHECK-81M-LE-NEXT: @ %bb.1:327; CHECK-81M-LE-NEXT: .LCPI3_0:328; CHECK-81M-LE-NEXT: .long 0 @ double 10329; CHECK-81M-LE-NEXT: .long 1076101120330;331; CHECK-81M-BE-LABEL: d2:332; CHECK-81M-BE: @ %bb.0: @ %entry333; CHECK-81M-BE-NEXT: push {r7, lr}334; CHECK-81M-BE-NEXT: vldr d0, .LCPI3_0335; CHECK-81M-BE-NEXT: mov r2, r0336; CHECK-81M-BE-NEXT: vmov r1, r0, d0337; CHECK-81M-BE-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}338; CHECK-81M-BE-NEXT: bic r2, r2, #1339; CHECK-81M-BE-NEXT: sub sp, #136340; CHECK-81M-BE-NEXT: vlstm sp341; CHECK-81M-BE-NEXT: clrm {r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}342; CHECK-81M-BE-NEXT: blxns r2343; CHECK-81M-BE-NEXT: vlldm sp344; CHECK-81M-BE-NEXT: add sp, #136345; CHECK-81M-BE-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}346; CHECK-81M-BE-NEXT: pop {r7, pc}347; CHECK-81M-BE-NEXT: .p2align 3348; CHECK-81M-BE-NEXT: @ %bb.1:349; CHECK-81M-BE-NEXT: .LCPI3_0:350; CHECK-81M-BE-NEXT: .long 1076101120 @ double 10351; CHECK-81M-BE-NEXT: .long 0352entry:353 %call = call double %fptr(double 10.0) #3354 ret double %call355}356 357define float @f3(ptr nocapture %fptr) #4 {358; CHECK-8M-LABEL: f3:359; CHECK-8M: @ %bb.0: @ %entry360; CHECK-8M-NEXT: push {r7, lr}361; CHECK-8M-NEXT: mov r1, r0362; CHECK-8M-NEXT: movs r0, #0363; CHECK-8M-NEXT: movt r0, #16672364; CHECK-8M-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}365; CHECK-8M-NEXT: bic r1, r1, #1366; CHECK-8M-NEXT: sub sp, #136367; CHECK-8M-NEXT: vlstm sp368; CHECK-8M-NEXT: mov r2, r1369; CHECK-8M-NEXT: mov r3, r1370; CHECK-8M-NEXT: mov r4, r1371; CHECK-8M-NEXT: mov r5, r1372; CHECK-8M-NEXT: mov r6, r1373; CHECK-8M-NEXT: mov r7, r1374; CHECK-8M-NEXT: mov r8, r1375; CHECK-8M-NEXT: mov r9, r1376; CHECK-8M-NEXT: mov r10, r1377; CHECK-8M-NEXT: mov r11, r1378; CHECK-8M-NEXT: mov r12, r1379; CHECK-8M-NEXT: msr apsr_nzcvqg, r1380; CHECK-8M-NEXT: blxns r1381; CHECK-8M-NEXT: vlldm sp382; CHECK-8M-NEXT: add sp, #136383; CHECK-8M-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}384; CHECK-8M-NEXT: pop {r7, pc}385;386; CHECK-81M-LABEL: f3:387; CHECK-81M: @ %bb.0: @ %entry388; CHECK-81M-NEXT: push {r7, lr}389; CHECK-81M-NEXT: mov r1, r0390; CHECK-81M-NEXT: movs r0, #0391; CHECK-81M-NEXT: movt r0, #16672392; CHECK-81M-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}393; CHECK-81M-NEXT: bic r1, r1, #1394; CHECK-81M-NEXT: sub sp, #136395; CHECK-81M-NEXT: vlstm sp396; CHECK-81M-NEXT: clrm {r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}397; CHECK-81M-NEXT: blxns r1398; CHECK-81M-NEXT: vlldm sp399; CHECK-81M-NEXT: add sp, #136400; CHECK-81M-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}401; CHECK-81M-NEXT: pop {r7, pc}402entry:403 %call = tail call float %fptr(float 10.0) #5404 ret float %call405}406 407attributes #4 = { nounwind }408attributes #5 = { "cmse_nonsecure_call" nounwind }409 410define double @d3(ptr nocapture %fptr) #4 {411; CHECK-8M-LE-LABEL: d3:412; CHECK-8M-LE: @ %bb.0: @ %entry413; CHECK-8M-LE-NEXT: push {r7, lr}414; CHECK-8M-LE-NEXT: vldr d0, .LCPI5_0415; CHECK-8M-LE-NEXT: mov r2, r0416; CHECK-8M-LE-NEXT: vmov r0, r1, d0417; CHECK-8M-LE-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}418; CHECK-8M-LE-NEXT: bic r2, r2, #1419; CHECK-8M-LE-NEXT: sub sp, #136420; CHECK-8M-LE-NEXT: vlstm sp421; CHECK-8M-LE-NEXT: mov r3, r2422; CHECK-8M-LE-NEXT: mov r4, r2423; CHECK-8M-LE-NEXT: mov r5, r2424; CHECK-8M-LE-NEXT: mov r6, r2425; CHECK-8M-LE-NEXT: mov r7, r2426; CHECK-8M-LE-NEXT: mov r8, r2427; CHECK-8M-LE-NEXT: mov r9, r2428; CHECK-8M-LE-NEXT: mov r10, r2429; CHECK-8M-LE-NEXT: mov r11, r2430; CHECK-8M-LE-NEXT: mov r12, r2431; CHECK-8M-LE-NEXT: msr apsr_nzcvqg, r2432; CHECK-8M-LE-NEXT: blxns r2433; CHECK-8M-LE-NEXT: vlldm sp434; CHECK-8M-LE-NEXT: add sp, #136435; CHECK-8M-LE-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}436; CHECK-8M-LE-NEXT: pop {r7, pc}437; CHECK-8M-LE-NEXT: .p2align 3438; CHECK-8M-LE-NEXT: @ %bb.1:439; CHECK-8M-LE-NEXT: .LCPI5_0:440; CHECK-8M-LE-NEXT: .long 0 @ double 10441; CHECK-8M-LE-NEXT: .long 1076101120442;443; CHECK-8M-BE-LABEL: d3:444; CHECK-8M-BE: @ %bb.0: @ %entry445; CHECK-8M-BE-NEXT: push {r7, lr}446; CHECK-8M-BE-NEXT: vldr d0, .LCPI5_0447; CHECK-8M-BE-NEXT: mov r2, r0448; CHECK-8M-BE-NEXT: vmov r1, r0, d0449; CHECK-8M-BE-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}450; CHECK-8M-BE-NEXT: bic r2, r2, #1451; CHECK-8M-BE-NEXT: sub sp, #136452; CHECK-8M-BE-NEXT: vlstm sp453; CHECK-8M-BE-NEXT: mov r3, r2454; CHECK-8M-BE-NEXT: mov r4, r2455; CHECK-8M-BE-NEXT: mov r5, r2456; CHECK-8M-BE-NEXT: mov r6, r2457; CHECK-8M-BE-NEXT: mov r7, r2458; CHECK-8M-BE-NEXT: mov r8, r2459; CHECK-8M-BE-NEXT: mov r9, r2460; CHECK-8M-BE-NEXT: mov r10, r2461; CHECK-8M-BE-NEXT: mov r11, r2462; CHECK-8M-BE-NEXT: mov r12, r2463; CHECK-8M-BE-NEXT: msr apsr_nzcvqg, r2464; CHECK-8M-BE-NEXT: blxns r2465; CHECK-8M-BE-NEXT: vlldm sp466; CHECK-8M-BE-NEXT: add sp, #136467; CHECK-8M-BE-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}468; CHECK-8M-BE-NEXT: pop {r7, pc}469; CHECK-8M-BE-NEXT: .p2align 3470; CHECK-8M-BE-NEXT: @ %bb.1:471; CHECK-8M-BE-NEXT: .LCPI5_0:472; CHECK-8M-BE-NEXT: .long 1076101120 @ double 10473; CHECK-8M-BE-NEXT: .long 0474;475; CHECK-81M-LE-LABEL: d3:476; CHECK-81M-LE: @ %bb.0: @ %entry477; CHECK-81M-LE-NEXT: push {r7, lr}478; CHECK-81M-LE-NEXT: vldr d0, .LCPI5_0479; CHECK-81M-LE-NEXT: mov r2, r0480; CHECK-81M-LE-NEXT: vmov r0, r1, d0481; CHECK-81M-LE-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}482; CHECK-81M-LE-NEXT: bic r2, r2, #1483; CHECK-81M-LE-NEXT: sub sp, #136484; CHECK-81M-LE-NEXT: vlstm sp485; CHECK-81M-LE-NEXT: clrm {r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}486; CHECK-81M-LE-NEXT: blxns r2487; CHECK-81M-LE-NEXT: vlldm sp488; CHECK-81M-LE-NEXT: add sp, #136489; CHECK-81M-LE-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}490; CHECK-81M-LE-NEXT: pop {r7, pc}491; CHECK-81M-LE-NEXT: .p2align 3492; CHECK-81M-LE-NEXT: @ %bb.1:493; CHECK-81M-LE-NEXT: .LCPI5_0:494; CHECK-81M-LE-NEXT: .long 0 @ double 10495; CHECK-81M-LE-NEXT: .long 1076101120496;497; CHECK-81M-BE-LABEL: d3:498; CHECK-81M-BE: @ %bb.0: @ %entry499; CHECK-81M-BE-NEXT: push {r7, lr}500; CHECK-81M-BE-NEXT: vldr d0, .LCPI5_0501; CHECK-81M-BE-NEXT: mov r2, r0502; CHECK-81M-BE-NEXT: vmov r1, r0, d0503; CHECK-81M-BE-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}504; CHECK-81M-BE-NEXT: bic r2, r2, #1505; CHECK-81M-BE-NEXT: sub sp, #136506; CHECK-81M-BE-NEXT: vlstm sp507; CHECK-81M-BE-NEXT: clrm {r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}508; CHECK-81M-BE-NEXT: blxns r2509; CHECK-81M-BE-NEXT: vlldm sp510; CHECK-81M-BE-NEXT: add sp, #136511; CHECK-81M-BE-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}512; CHECK-81M-BE-NEXT: pop {r7, pc}513; CHECK-81M-BE-NEXT: .p2align 3514; CHECK-81M-BE-NEXT: @ %bb.1:515; CHECK-81M-BE-NEXT: .LCPI5_0:516; CHECK-81M-BE-NEXT: .long 1076101120 @ double 10517; CHECK-81M-BE-NEXT: .long 0518entry:519 %call = tail call double %fptr(double 10.0) #5520 ret double %call521}522 523define float @f4(ptr nocapture %fptr) #6 {524; CHECK-8M-LABEL: f4:525; CHECK-8M: @ %bb.0: @ %entry526; CHECK-8M-NEXT: push {r7, lr}527; CHECK-8M-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}528; CHECK-8M-NEXT: bic r0, r0, #1529; CHECK-8M-NEXT: sub sp, #136530; CHECK-8M-NEXT: vlstm sp531; CHECK-8M-NEXT: mov r1, r0532; CHECK-8M-NEXT: mov r2, r0533; CHECK-8M-NEXT: mov r3, r0534; CHECK-8M-NEXT: mov r4, r0535; CHECK-8M-NEXT: mov r5, r0536; CHECK-8M-NEXT: mov r6, r0537; CHECK-8M-NEXT: mov r7, r0538; CHECK-8M-NEXT: mov r8, r0539; CHECK-8M-NEXT: mov r9, r0540; CHECK-8M-NEXT: mov r10, r0541; CHECK-8M-NEXT: mov r11, r0542; CHECK-8M-NEXT: mov r12, r0543; CHECK-8M-NEXT: msr apsr_nzcvqg, r0544; CHECK-8M-NEXT: blxns r0545; CHECK-8M-NEXT: vlldm sp546; CHECK-8M-NEXT: add sp, #136547; CHECK-8M-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}548; CHECK-8M-NEXT: pop {r7, pc}549;550; CHECK-81M-LABEL: f4:551; CHECK-81M: @ %bb.0: @ %entry552; CHECK-81M-NEXT: push {r7, lr}553; CHECK-81M-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}554; CHECK-81M-NEXT: bic r0, r0, #1555; CHECK-81M-NEXT: sub sp, #136556; CHECK-81M-NEXT: vlstm sp557; CHECK-81M-NEXT: clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}558; CHECK-81M-NEXT: blxns r0559; CHECK-81M-NEXT: vlldm sp560; CHECK-81M-NEXT: add sp, #136561; CHECK-81M-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}562; CHECK-81M-NEXT: pop {r7, pc}563entry:564 %call = call float %fptr() #7565 ret float %call566}567 568attributes #6 = { nounwind }569attributes #7 = { "cmse_nonsecure_call" nounwind }570 571define double @d4(ptr nocapture %fptr) #6 {572; CHECK-8M-LABEL: d4:573; CHECK-8M: @ %bb.0: @ %entry574; CHECK-8M-NEXT: push {r7, lr}575; CHECK-8M-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}576; CHECK-8M-NEXT: bic r0, r0, #1577; CHECK-8M-NEXT: sub sp, #136578; CHECK-8M-NEXT: vlstm sp579; CHECK-8M-NEXT: mov r1, r0580; CHECK-8M-NEXT: mov r2, r0581; CHECK-8M-NEXT: mov r3, r0582; CHECK-8M-NEXT: mov r4, r0583; CHECK-8M-NEXT: mov r5, r0584; CHECK-8M-NEXT: mov r6, r0585; CHECK-8M-NEXT: mov r7, r0586; CHECK-8M-NEXT: mov r8, r0587; CHECK-8M-NEXT: mov r9, r0588; CHECK-8M-NEXT: mov r10, r0589; CHECK-8M-NEXT: mov r11, r0590; CHECK-8M-NEXT: mov r12, r0591; CHECK-8M-NEXT: msr apsr_nzcvqg, r0592; CHECK-8M-NEXT: blxns r0593; CHECK-8M-NEXT: vlldm sp594; CHECK-8M-NEXT: add sp, #136595; CHECK-8M-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}596; CHECK-8M-NEXT: pop {r7, pc}597;598; CHECK-81M-LABEL: d4:599; CHECK-81M: @ %bb.0: @ %entry600; CHECK-81M-NEXT: push {r7, lr}601; CHECK-81M-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}602; CHECK-81M-NEXT: bic r0, r0, #1603; CHECK-81M-NEXT: sub sp, #136604; CHECK-81M-NEXT: vlstm sp605; CHECK-81M-NEXT: clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}606; CHECK-81M-NEXT: blxns r0607; CHECK-81M-NEXT: vlldm sp608; CHECK-81M-NEXT: add sp, #136609; CHECK-81M-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}610; CHECK-81M-NEXT: pop {r7, pc}611entry:612 %call = call double %fptr() #7613 ret double %call614}615 616define void @fd(ptr %f, float %a, double %b) #8 {617; CHECK-8M-LABEL: fd:618; CHECK-8M: @ %bb.0: @ %entry619; CHECK-8M-NEXT: push {r7, lr}620; CHECK-8M-NEXT: mov r12, r0621; CHECK-8M-NEXT: mov r0, r1622; CHECK-8M-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}623; CHECK-8M-NEXT: bic r12, r12, #1624; CHECK-8M-NEXT: sub sp, #136625; CHECK-8M-NEXT: vlstm sp626; CHECK-8M-NEXT: mov r1, r12627; CHECK-8M-NEXT: mov r4, r12628; CHECK-8M-NEXT: mov r5, r12629; CHECK-8M-NEXT: mov r6, r12630; CHECK-8M-NEXT: mov r7, r12631; CHECK-8M-NEXT: mov r8, r12632; CHECK-8M-NEXT: mov r9, r12633; CHECK-8M-NEXT: mov r10, r12634; CHECK-8M-NEXT: mov r11, r12635; CHECK-8M-NEXT: msr apsr_nzcvqg, r12636; CHECK-8M-NEXT: blxns r12637; CHECK-8M-NEXT: vlldm sp638; CHECK-8M-NEXT: add sp, #136639; CHECK-8M-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}640; CHECK-8M-NEXT: pop {r7, pc}641;642; CHECK-81M-LABEL: fd:643; CHECK-81M: @ %bb.0: @ %entry644; CHECK-81M-NEXT: push {r7, lr}645; CHECK-81M-NEXT: mov r12, r0646; CHECK-81M-NEXT: mov r0, r1647; CHECK-81M-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}648; CHECK-81M-NEXT: bic r12, r12, #1649; CHECK-81M-NEXT: sub sp, #136650; CHECK-81M-NEXT: vlstm sp651; CHECK-81M-NEXT: clrm {r1, r4, r5, r6, r7, r8, r9, r10, r11, apsr}652; CHECK-81M-NEXT: blxns r12653; CHECK-81M-NEXT: vlldm sp654; CHECK-81M-NEXT: add sp, #136655; CHECK-81M-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}656; CHECK-81M-NEXT: pop {r7, pc}657entry:658 call void %f(float %a, double %b) #9659 ret void660}661 662attributes #8 = { nounwind }663attributes #9 = { "cmse_nonsecure_call" nounwind }664 665define float @f1_minsize(ptr nocapture %fptr) #10 {666; CHECK-8M-LABEL: f1_minsize:667; CHECK-8M: @ %bb.0: @ %entry668; CHECK-8M-NEXT: push {r7, lr}669; CHECK-8M-NEXT: mov r1, r0670; CHECK-8M-NEXT: ldr r0, .LCPI9_0671; CHECK-8M-NEXT: blx r1672; CHECK-8M-NEXT: pop.w {r7, lr}673; CHECK-8M-NEXT: vmrs r12, fpscr674; CHECK-8M-NEXT: vmov d0, lr, lr675; CHECK-8M-NEXT: vmov d1, lr, lr676; CHECK-8M-NEXT: mov r1, lr677; CHECK-8M-NEXT: vmov d2, lr, lr678; CHECK-8M-NEXT: mov r2, lr679; CHECK-8M-NEXT: vmov d3, lr, lr680; CHECK-8M-NEXT: mov r3, lr681; CHECK-8M-NEXT: vmov d4, lr, lr682; CHECK-8M-NEXT: vmov d5, lr, lr683; CHECK-8M-NEXT: vmov d6, lr, lr684; CHECK-8M-NEXT: vmov d7, lr, lr685; CHECK-8M-NEXT: bic r12, r12, #159686; CHECK-8M-NEXT: bic r12, r12, #4026531840687; CHECK-8M-NEXT: vmsr fpscr, r12688; CHECK-8M-NEXT: mov r12, lr689; CHECK-8M-NEXT: msr apsr_nzcvqg, lr690; CHECK-8M-NEXT: bxns lr691; CHECK-8M-NEXT: .p2align 2692; CHECK-8M-NEXT: @ %bb.1:693; CHECK-8M-NEXT: .LCPI9_0:694; CHECK-8M-NEXT: .long 1092616192 @ 0x41200000695;696; CHECK-81M-LABEL: f1_minsize:697; CHECK-81M: @ %bb.0: @ %entry698; CHECK-81M-NEXT: vstr fpcxtns, [sp, #-4]!699; CHECK-81M-NEXT: push {r6, r7, lr}700; CHECK-81M-NEXT: mov r1, r0701; CHECK-81M-NEXT: ldr r0, .LCPI9_0702; CHECK-81M-NEXT: blx r1703; CHECK-81M-NEXT: pop.w {r3, r7, lr}704; CHECK-81M-NEXT: vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}705; CHECK-81M-NEXT: vldr fpcxtns, [sp], #4706; CHECK-81M-NEXT: clrm {r1, r2, r3, r12, apsr}707; CHECK-81M-NEXT: bxns lr708; CHECK-81M-NEXT: .p2align 2709; CHECK-81M-NEXT: @ %bb.1:710; CHECK-81M-NEXT: .LCPI9_0:711; CHECK-81M-NEXT: .long 1092616192 @ 0x41200000712entry:713 %call = call float %fptr(float 10.0) #11714 ret float %call715}716 717attributes #10 = { "cmse_nonsecure_entry" minsize nounwind }718attributes #11 = { nounwind }719