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1# RUN: llc -mtriple=thumbv8m.main -mcpu=cortex-m33 -mattr=-fix-cmse-cve-2021-35465 --float-abi=hard --run-pass=arm-pseudo %s -o - | \2# RUN: FileCheck %s3--- |4 ; ModuleID = 'cmse-vlldm-no-reorder.ll'5 source_filename = "cmse-vlldm-no-reorder.ll"6 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"7 target triple = "thumbv8m.main"8 9 @g = hidden local_unnamed_addr global float (...)* null, align 410 @a = hidden local_unnamed_addr global float 0.000000e+00, align 411 12 ; Function Attrs: nounwind13 define hidden void @f() local_unnamed_addr #0 {14 entry:15 %0 = load float ()*, float ()** bitcast (float (...)** @g to float ()**), align 416 %call = tail call nnan ninf nsz float %0() #217 store float %call, float* @a, align 418 ret void19 }20 21 ; Function Attrs: nounwind22 declare void @llvm.stackprotector(i8*, i8**) #123 24 attributes #0 = { nounwind "target-cpu"="cortex-m33" }25 attributes #1 = { nounwind }26 attributes #2 = { nounwind "cmse_nonsecure_call" }27 28...29---30name: f31alignment: 232exposesReturnsTwice: false33legalized: false34regBankSelected: false35selected: false36failedISel: false37tracksRegLiveness: true38hasWinCFI: false39registers: []40liveins: []41frameInfo:42 isFrameAddressTaken: false43 isReturnAddressTaken: false44 hasStackMap: false45 hasPatchPoint: false46 stackSize: 847 offsetAdjustment: 048 maxAlignment: 449 adjustsStack: true50 hasCalls: true51 stackProtector: ''52 maxCallFrameSize: 053 cvBytesOfCalleeSavedRegisters: 054 hasOpaqueSPAdjustment: false55 hasVAStart: false56 hasMustTailInVarArgFunc: false57 localFrameSize: 058 savePoint: []59 restorePoint: []60fixedStack: []61stack:62 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 63 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 64 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }65 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 66 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 67 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }68callSites: []69constants: []70machineFunctionInfo: {}71body: |72 bb.0.entry:73 liveins: $r7, $lr74 75 $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r7, killed $lr76 frame-setup CFI_INSTRUCTION def_cfa_offset 877 frame-setup CFI_INSTRUCTION offset $lr, -478 frame-setup CFI_INSTRUCTION offset $r7, -879 renamable $r0 = t2MOVi32imm @g80 renamable $r0 = t2LDRi12 killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (dereferenceable load (s32) from `float ()** bitcast (float (...)** @g to float ()**)`)81 tBLXNS_CALL killed renamable $r0, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $s082 renamable $r0 = t2MOVi32imm @a83 VSTRS killed renamable $s0, killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (store (s32) into @a)84 $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r7, def $pc85 86...87 88# CHECK-LABEL: bb.0.entry:89# CHECK: $sp = t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, $r4, $r5, $r6, undef $r7, $r8, $r9, $r10, $r1190# CHECK-NEXT: $r0 = t2BICri $r0, 1, 14 /* CC::al */, $noreg, $noreg91# CHECK-NEXT: $sp = tSUBspi $sp, 34, 14 /* CC::al */, $noreg92# CHECK-NEXT: dead $s0 = VMOVS undef $s0, 14 /* CC::al */, $noreg93# CHECK-NEXT: VLSTM $sp, 14 /* CC::al */, $noreg, 0, implicit-def $vpr, implicit-def $fpscr, implicit-def $fpscr_nzcv, implicit undef $vpr, implicit undef $fpscr, implicit undef $fpscr_nzcv, implicit undef $d0, implicit undef $d1, implicit undef $d2, implicit undef $d3, implicit undef $d4, implicit undef $d5, implicit undef $d6, implicit undef $d7, implicit $d8, implicit $d9, implicit $d10, implicit $d11, implicit $d12, implicit $d13, implicit $d14, implicit $d1594# CHECK-NEXT: $r1 = tMOVr $r0, 14 /* CC::al */, $noreg95# CHECK-NEXT: $r2 = tMOVr $r0, 14 /* CC::al */, $noreg96# CHECK-NEXT: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg97# CHECK-NEXT: $r4 = tMOVr $r0, 14 /* CC::al */, $noreg98# CHECK-NEXT: $r5 = tMOVr $r0, 14 /* CC::al */, $noreg99# CHECK-NEXT: $r6 = tMOVr $r0, 14 /* CC::al */, $noreg100# CHECK-NEXT: $r7 = tMOVr $r0, 14 /* CC::al */, $noreg101# CHECK-NEXT: $r8 = tMOVr $r0, 14 /* CC::al */, $noreg102# CHECK-NEXT: $r9 = tMOVr $r0, 14 /* CC::al */, $noreg103# CHECK-NEXT: $r10 = tMOVr $r0, 14 /* CC::al */, $noreg104# CHECK-NEXT: $r11 = tMOVr $r0, 14 /* CC::al */, $noreg105# CHECK-NEXT: $r12 = tMOVr $r0, 14 /* CC::al */, $noreg106# CHECK-NEXT: t2MSR_M 3072, $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr107# CHECK-NEXT: tBLXNSr 14 /* CC::al */, $noreg, killed $r0, csr_aapcs, implicit-def $lr, implicit $sp, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $s0108# CHECK-NEXT: $r12 = VMOVRS $s0, 14 /* CC::al */, $noreg109# CHECK-NEXT: VLLDM $sp, 14 /* CC::al */, $noreg, 0, implicit-def $vpr, implicit-def $fpscr, implicit-def $fpscr_nzcv, implicit-def $d0, implicit-def $d1, implicit-def $d2, implicit-def $d3, implicit-def $d4, implicit-def $d5, implicit-def $d6, implicit-def $d7, implicit-def $d8, implicit-def $d9, implicit-def $d10, implicit-def $d11, implicit-def $d12, implicit-def $d13, implicit-def $d14, implicit-def $d15110# CHECK-NEXT: $s0 = VMOVSR $r12, 14 /* CC::al */, $noreg111# CHECK-NEXT: $sp = tADDspi $sp, 34, 14 /* CC::al */, $noreg112# CHECK-NEXT: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11113