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1; REQUIRES: asserts2; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s3; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=+use-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=POST-MISCHED4 5; Check the latency for ALU shifted operand variants.6;7; CHECK: ********** MI Scheduling **********8; CHECK: foo:%bb.0 entry9 10; ALU, basic - 1 cyc I0/I111; CHECK: EORrr12; CHECK: rdefs left13; CHECK-NEXT: Latency : 114 15; ALU, shift by immed - 2 cyc M16; CHECK: ADDrsi17; CHECK: rdefs left18; CHECK-NEXT: Latency : 219 20; ALU, shift by register, unconditional - 2 cyc M21; CHECK: RSBrsr22; CHECK: rdefs left23; CHECK-NEXT: Latency : 224 25; ALU, shift by register, conditional - 2 cyc I0/I126; CHECK: ANDrsr27; CHECK: rdefs left28; CHECK-NEXT: Latency : 229 30; Checking scheduling units31 32; CHECK: ** ScheduleDAGMILive::schedule picking next node33; Skipping COPY34; CHECK: ** ScheduleDAGMILive::schedule picking next node35; CHECK: Scheduling36; CHECK-SAME: ANDrsr37; CHECK: Ready38; CHECK-NEXT: A57UnitI39 40; CHECK: ** ScheduleDAGMILive::schedule picking next node41; CHECK: Scheduling42; CHECK-SAME: CMPri43; CHECK: Ready44; CHECK-NEXT: A57UnitI45 46; CHECK: ** ScheduleDAGMILive::schedule picking next node47; CHECK: Scheduling48; CHECK-SAME: RSBrsr49; CHECK: Ready50; CHECK-NEXT: A57UnitM51 52; CHECK: ** ScheduleDAGMILive::schedule picking next node53; CHECK: Scheduling54; CHECK-SAME: ADDrsi55; CHECK: Ready56; CHECK-NEXT: A57UnitM57 58; CHECK: ** ScheduleDAGMILive::schedule picking next node59; CHECK: Scheduling60; CHECK-SAME: EORrr61; CHECK: Ready62; CHECK-NEXT: A57UnitI63 64; Check that post RA MI scheduler is invoked with +use-misched65; POST-MISCHED: Before post-MI-sched66 67target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"68target triple = "armv8r-arm-none-eabi"69 70; Function Attrs: norecurse nounwind readnone71define hidden i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d) local_unnamed_addr #0 {72entry:73 %xor = xor i32 %a, %b74 %xor_shl = shl i32 %xor, 275 %add = add i32 %xor_shl, %d76 %add_ashr = ashr i32 %add, %a77 %sub = sub i32 %add_ashr, %a78 %sub_lshr_pred = lshr i32 %sub, %c79 %pred = icmp sgt i32 %a, 480 %and = and i32 %sub_lshr_pred, %b81 %rv = select i1 %pred, i32 %and, i32 %d82 ret i32 %rv83}84 85