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1; REQUIRES: asserts2; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=A57_SCHED3; RUN: llc < %s -mtriple=armv8r-eabi -mattr=+neon,+fp-armv8 -mcpu=generic -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC4 5; Check the latency for instructions for both generic and cortex-a57.6; SDIV should be scheduled at the block's begin (20 cyc of independent M unit).7;8; CHECK: ********** MI Scheduling **********9; CHECK: foo:%bb.0 entry10 11; GENERIC: LDRi1212; GENERIC: Latency : 113; GENERIC: EORrr14; GENERIC: Latency : 115; GENERIC: ADDrr16; GENERIC: Latency : 117; GENERIC: SDIV18; GENERIC: Latency : 019; GENERIC: SUBrr20; GENERIC: Latency : 121 22; A57_SCHED: SDIV23; A57_SCHED: Latency : 2024; A57_SCHED: EORrr25; A57_SCHED: Latency : 126; A57_SCHED: LDRi1227; A57_SCHED: Latency : 428; A57_SCHED: ADDrr29; A57_SCHED: Latency : 130; A57_SCHED: SUBrr31; A57_SCHED: Latency : 132 33; CHECK: ** Final schedule for %bb.0 ***34; GENERIC: LDRi1235; GENERIC: SDIV36; A57_SCHED: SDIV37; A57_SCHED: LDRi1238; CHECK: ********** INTERVALS **********39 40target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"41target triple = "armv8r-arm-none-eabi"42 43; Function Attrs: norecurse nounwind readnone44define hidden i32 @foo(i32 %a, i32 %b, i32 %c, ptr %d) local_unnamed_addr #0 {45entry:46 %xor = xor i32 %c, %b47 %ld = load i32, ptr %d48 %add = add nsw i32 %xor, %ld49 %div = sdiv i32 %a, %b50 %sub = sub i32 %div, %add51 ret i32 %sub52}53 54