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1; REQUIRES: asserts2; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s3; 4 5@a = dso_local global i32 0, align 46@b = dso_local global i32 0, align 47@c = dso_local global i32 0, align 48 9; CHECK: ********** MI Scheduling **********10; We need second, post-ra scheduling to have LDM instruction combined from single-loads11; CHECK: ********** MI Scheduling **********12; CHECK: LDMIA_UPD13; CHECK: rdefs left14; CHECK-NEXT: Latency : 415; CHECK: Successors:16; CHECK: Data17; CHECK-SAME: Latency=118; CHECK-NEXT: Data19; CHECK-SAME: Latency=320; CHECK-NEXT: Data21; CHECK-SAME: Latency=022; CHECK-NEXT: Data23; CHECK-SAME: Latency=024define dso_local i32 @bar(i32 %a1, i32 %b1, i32 %c1) minsize optsize {25 %1 = load i32, ptr @a, align 426 %2 = load i32, ptr @b, align 427 %3 = load i32, ptr @c, align 428 29 %ptr_after = getelementptr i32, ptr @a, i32 330 31 %ptr_val = ptrtoint ptr %ptr_after to i3232 %mul1 = mul i32 %ptr_val, %133 %mul2 = mul i32 %mul1, %234 %mul3 = mul i32 %mul2, %335 ret i32 %mul336}37 38