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1; REQUIRES: asserts2; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s3 4; CHECK: ********** MI Scheduling **********5; We need second, post-ra scheduling to have LDM instruction combined from single-loads6; CHECK: ********** MI Scheduling **********7; CHECK: LDMIA8; CHECK: rdefs left9; CHECK-NEXT: Latency : 310; CHECK: Successors:11; CHECK: Data12; CHECK-SAME: Latency=313; CHECK-NEXT: Data14; CHECK-SAME: Latency=015 16define i32 @foo(ptr %a) nounwind optsize {17entry:18 %b = getelementptr i32, ptr %a, i32 119 %c = getelementptr i32, ptr %a, i32 2 20 %0 = load i32, ptr %a, align 421 %1 = load i32, ptr %b, align 422 %2 = load i32, ptr %c, align 423 24 %mul1 = mul i32 %0, %125 %mul2 = mul i32 %mul1, %226 ret i32 %mul227}28 29