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1# REQUIRES: asserts2# RUN: llc -mcpu=cortex-a57 -mtriple=thumb -enable-misched -run-pass=machine-scheduler -debug-only=machine-scheduler %s -o - 2>&1 | FileCheck %s3 4# CHECK-LABEL: ********** MI Scheduling **********5# CHECK: %[[RES:[0-9]+]]:rgpr = t2MLA6# CHECK-NEXT: # preds left7# CHECK-NEXT: # succs left8# CHECK-NEXT: # rdefs left9# CHECK-NEXT: Latency : 310# CHECK-NEXT: Depth11# CHECK-NEXT: Height12# CHECK-NEXT: Predecessors:13# CHECK-NEXT: SU({{.*}}): Data Latency=1 Reg=14# CHECK-NEXT: SU({{.*}}): Data Latency=1 Reg=15# CHECK-NEXT: Successors:16# CHECK-NEXT: SU([[SMLA_SU:[0-9]+]]): Data Latency=1 Reg=%[[RES]]17# CHECK-NEXT: Pressure Diff18# CHECK-NEXT: Single Issue : false;19# CHECK-NEXT: SU([[SMLA_SU]]): {{.*}} = t2SMLAL %{{[0-9]+}}:rgpr, %{{[0-9]+}}:rgpr, %{{[0-9]+}}:rgpr(tied-def 0), %[[RES]]:rgpr(tied-def 1), 14, $noreg20 21name: test_smlal_forwarding22tracksRegLiveness: true23body: |24 bb.0:25 liveins: $r1, $r3, $r4, $r5, $r626 %1:rgpr = COPY $r127 %3:rgpr = COPY $r328 %4:rgpr = COPY $r429 %5:rgpr = COPY $r530 %6:rgpr = COPY $r631 %3:rgpr = t2MLA %4:rgpr, %1:rgpr, %4:rgpr, 14, $noreg32 %6:rgpr, %5:rgpr = t2SMLAL %5:rgpr, %6:rgpr, %4:rgpr, %3:rgpr, 14, $noreg33 $r0 = COPY %6:rgpr34 BX_RET 14, $noreg, implicit $r035