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1; REQUIRES: asserts2; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s3; N=3 STMIA_UPD should have latency 2cyc and writeback latency 1cyc4 5; CHECK: ********** MI Scheduling **********6; We need second, post-ra scheduling to have STM instruction combined from single-stores7; CHECK: ********** MI Scheduling **********8; CHECK: schedule starting9; CHECK: STMIA_UPD10; CHECK: rdefs left11; CHECK-NEXT: Latency : 212; CHECK: Successors13; CHECK: Data14; CHECK-SAME: Latency=115 16define i32 @bar(i32 %v0, i32 %v1, i32 %v2, ptr %addr) {17 18 store i32 %v0, ptr %addr19 20 %addr.2 = getelementptr i32, ptr %addr, i32 121 store i32 %v1, ptr %addr.222 23 %addr.3 = getelementptr i32, ptr %addr, i32 224 store i32 %v2, ptr %addr.325 26 %ptr_after = getelementptr i32, ptr %addr, i32 327 %val = ptrtoint ptr %ptr_after to i3228 29 %rv1 = mul i32 %val, %v030 %rv2 = mul i32 %rv1, %v131 %rv3 = mul i32 %rv2, %v232 33 ret i32 %rv334}35 36