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1; REQUIRES: asserts2; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s3; N=3 STMIB should have latency 2cyc4 5; CHECK: ********** MI Scheduling **********6; We need second, post-ra scheduling to have STM instruction combined from single-stores7; CHECK: ********** MI Scheduling **********8; CHECK: schedule starting9; CHECK: STMIB10; CHECK: rdefs left11; CHECK-NEXT: Latency : 212 13define i32 @test_stm(i32 %v0, i32 %v1, ptr %addr) {14 15 %addr.1 = getelementptr i32, ptr %addr, i32 116 store i32 %v0, ptr %addr.117 18 %addr.2 = getelementptr i32, ptr %addr, i32 219 store i32 %v1, ptr %addr.220 21 %addr.3 = getelementptr i32, ptr %addr, i32 322 %val = ptrtoint ptr %addr to i3223 store i32 %val, ptr %addr.324 25 %rv = add i32 %v0, %v126 27 ret i32 %rv28}29 30