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1; REQUIRES: asserts2; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-DEFAULT3; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null -fp-contract=fast | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FAST4; Check latencies of vmul/vfma accumulate chains.5 6define arm_aapcs_vfpcc float @Test1(float %f1, float %f2, float %f3, float %f4, float %f5, float %f6) {7; CHECK: ********** MI Scheduling **********8; CHECK: Test1:%bb.09 10; CHECK: VMULS11; > VMULS common latency = 512; CHECK: Latency : 513; CHECK: Successors:14; CHECK: Data15; > VMULS read-advanced latency to VMLAS = 016; CHECK-SAME: Latency=017 18; CHECK-DEFAULT: VMLAS19; CHECK-FAST: VFMAS20; > VMLAS common latency = 921; CHECK: Latency : 922; CHECK: Successors:23; CHECK: Data24; > VMLAS read-advanced latency to the next VMLAS = 425; CHECK-SAME: Latency=426 27; CHECK-DEFAULT: VMLAS28; CHECK-FAST: VFMAS29; CHECK: Latency : 930; CHECK: Successors:31; CHECK: Data32; > VMLAS not-optimized latency to VMOVRS = 933; CHECK-SAME: Latency=934 35; f1 * f2 + f3 * f4 + f5 * f6 ==> VMULS, VMLAS, VMLAS36 %mul1 = fmul float %f1, %f237 %mul2 = fmul float %f3, %f438 %mul3 = fmul float %f5, %f639 %add1 = fadd float %mul1, %mul240 %add2 = fadd float %add1, %mul341 ret float %add242}43 44; ASIMD form45define arm_aapcs_vfpcc <2 x float> @Test2(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2 x float> %f4, <2 x float> %f5, <2 x float> %f6) {46; CHECK: ********** MI Scheduling **********47; CHECK: Test2:%bb.048 49; CHECK: VMULfd50; > VMULfd common latency = 551; CHECK: Latency : 552; CHECK: Successors:53; CHECK: Data54; VMULfd read-advanced latency to VMLAfd = 055; CHECK-SAME: Latency=056 57; CHECK-DEFAULT: VMLAfd58; CHECK-FAST: VFMAfd59; > VMLAfd common latency = 960; CHECK: Latency : 961; CHECK: Successors:62; CHECK: Data63; > VMLAfd read-advanced latency to the next VMLAfd = 464; CHECK-SAME: Latency=465 66; CHECK-DEFAULT: VMLAfd67; CHECK-FAST: VFMAfd68; CHECK: Latency : 969; CHECK: Successors:70; CHECK: Data71; > VMLAfd not-optimized latency to VMOVRRD = 972; CHECK-SAME: Latency=973 74; f1 * f2 + f3 * f4 + f5 * f6 ==> VMULS, VMLAS, VMLAS75 %mul1 = fmul <2 x float> %f1, %f276 %mul2 = fmul <2 x float> %f3, %f477 %mul3 = fmul <2 x float> %f5, %f678 %add1 = fadd <2 x float> %mul1, %mul279 %add2 = fadd <2 x float> %add1, %mul380 ret <2 x float> %add281}82 83define arm_aapcs_vfpcc float @Test3(float %f1, float %f2, float %f3, float %f4, float %f5, float %f6) {84; CHECK: ********** MI Scheduling **********85; CHECK: Test3:%bb.086 87; CHECK: VMULS88; > VMULS common latency = 589; CHECK: Latency : 590; CHECK: Successors:91; CHECK: Data92; > VMULS read-advanced latency to VMLSS = 093; CHECK-SAME: Latency=094 95; CHECK-DEFAULT: VMLSS96; CHECK-FAST: VFNMSS97; > VFNMSS common latency = 998; CHECK: Latency : 999; CHECK: Successors:100; CHECK: Data101; > VFNMSS read-advanced latency to the next VMLSS = 4102; CHECK-SAME: Latency=4103 104; CHECK-DEFAULT: VMLSS105; CHECK-FAST: VFMSS106; CHECK: Latency : 9107; CHECK: Successors:108; CHECK: Data109; > VMLSS not-optimized latency to VMOVRS = 9110; CHECK-SAME: Latency=9111 112; f1 * f2 + f3 * f4 + f5 * f6 ==> VMULS, VMLSS, VMLSS113 %mul1 = fmul float %f1, %f2114 %mul2 = fmul float %f3, %f4115 %mul3 = fmul float %f5, %f6116 %sub1 = fsub float %mul1, %mul2117 %sub2 = fsub float %sub1, %mul3118 ret float %sub2119}120 121; ASIMD form122define arm_aapcs_vfpcc <2 x float> @Test4(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2 x float> %f4, <2 x float> %f5, <2 x float> %f6) {123; CHECK: ********** MI Scheduling **********124; CHECK: Test4:%bb.0125 126; CHECK: VMULfd127; > VMULfd common latency = 5128; CHECK: Latency : 5129; CHECK: Successors:130; CHECK: Data131; VMULfd read-advanced latency to VMLSfd = 0132; CHECK-SAME: Latency=0133 134; CHECK-DEFAULT: VMLSfd135; CHECK-FAST: VFMSfd136; > VMLSfd common latency = 9137; CHECK: Latency : 9138; CHECK: Successors:139; CHECK: Data140; > VMLSfd read-advanced latency to the next VMLSfd = 4141; CHECK-SAME: Latency=4142 143; CHECK-DEFAULT: VMLSfd144; CHECK-FAST: VFMSfd145; CHECK: Latency : 9146; CHECK: Successors:147; CHECK: Data148; > VMLSfd not-optimized latency to VMOVRRD = 9149; CHECK-SAME: Latency=9150 151; f1 * f2 + f3 * f4 + f5 * f6 ==> VMULS, VMLSS, VMLSS152 %mul1 = fmul <2 x float> %f1, %f2153 %mul2 = fmul <2 x float> %f3, %f4154 %mul3 = fmul <2 x float> %f5, %f6155 %sub1 = fsub <2 x float> %mul1, %mul2156 %sub2 = fsub <2 x float> %sub1, %mul3157 ret <2 x float> %sub2158}159 160define arm_aapcs_vfpcc float @Test5(float %f1, float %f2, float %f3) {161; CHECK: ********** MI Scheduling **********162; CHECK: Test5:%bb.0163 164; CHECK-DEFAULT: VNMLS165; CHECK-FAST: VFNMS166; CHECK: Latency : 9167; CHECK: Successors:168; CHECK: Data169; > VMLAS not-optimized latency to VMOVRS = 9170; CHECK-SAME: Latency=9171 172; f1 * f2 - f3 ==> VNMLS/VFNMS173 %mul = fmul float %f1, %f2174 %sub = fsub float %mul, %f3175 ret float %sub176}177 178 179define arm_aapcs_vfpcc float @Test6(float %f1, float %f2, float %f3) {180; CHECK: ********** MI Scheduling **********181; CHECK: Test6:%bb.0182 183; CHECK-DEFAULT: VNMLA184; CHECK-FAST: VFNMA185; CHECK: Latency : 9186; CHECK: Successors:187; CHECK: Data188; > VMLAS not-optimized latency to VMOVRS = 9189; CHECK-SAME: Latency=9190 191; f1 * f2 - f3 ==> VNMLA/VFNMA192 %mul = fmul float %f1, %f2193 %sub1 = fsub float -0.0, %mul194 %sub2 = fsub float %sub1, %f2195 ret float %sub2196}197