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1; REQUIRES: asserts2; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s3; 4 5@a = dso_local global double 0.0, align 46@b = dso_local global double 0.0, align 47@c = dso_local global double 0.0, align 48 9; CHECK: ********** MI Scheduling **********10; We need second, post-ra scheduling to have VLDM instruction combined from single-loads11; CHECK: ********** MI Scheduling **********12; CHECK: VLDMDIA_UPD13; CHECK: rdefs left14; CHECK-NEXT: Latency : 615; CHECK: Successors:16; CHECK: Data17; CHECK-SAME: Latency=118; CHECK-NEXT: Data19; CHECK-SAME: Latency=120; CHECK-NEXT: Data21; CHECK-SAME: Latency=522; CHECK-NEXT: Data23; CHECK-SAME: Latency=024; CHECK-NEXT: Data25; CHECK-SAME: Latency=026define dso_local i32 @bar(ptr %iptr) minsize optsize {27 %1 = load double, ptr @a, align 828 %2 = load double, ptr @b, align 829 %3 = load double, ptr @c, align 830 31 %ptr_after = getelementptr double, ptr @a, i32 332 33 %ptr_new_ival = ptrtoint ptr %ptr_after to i3234 %ptr_new = inttoptr i32 %ptr_new_ival to ptr35 36 store i32 %ptr_new_ival, ptr %iptr, align 837 38 %v1 = fptoui double %1 to i3239 40 %mul1 = mul i32 %ptr_new_ival, %v141 42 %v2 = fptoui double %2 to i3243 %v3 = fptoui double %3 to i3244 45 %mul2 = mul i32 %mul1, %v246 %mul3 = mul i32 %mul2, %v347 48 ret i32 %mul349}50 51