31 lines · plain
1; REQUIRES: asserts2; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s3 4; CHECK: ********** MI Scheduling **********5; We need second, post-ra scheduling to have VLDM instruction combined from single-loads6; CHECK: ********** MI Scheduling **********7; CHECK: VLDMDIA8; CHECK: rdefs left9; CHECK-NEXT: Latency : 610; CHECK: Successors:11; CHECK: Data12; CHECK-SAME: Latency=513; CHECK-NEXT: Data14; CHECK-SAME: Latency=015; CHECK-NEXT: Data16; CHECK-SAME: Latency=017 18define double @foo(ptr %a) nounwind optsize {19entry:20 %b = getelementptr double, ptr %a, i32 121 %c = getelementptr double, ptr %a, i32 2 22 %0 = load double, ptr %a, align 423 %1 = load double, ptr %b, align 424 %2 = load double, ptr %c, align 425 26 %mul1 = fmul double %0, %127 %mul2 = fmul double %mul1, %228 ret double %mul229}30 31