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1; REQUIRES: asserts2; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s3 4; CHECK: ********** MI Scheduling **********5; We need second, post-ra scheduling to have VSTM instruction combined from single-stores6; CHECK: ********** MI Scheduling **********7; CHECK: schedule starting8; CHECK: VSTMDIA_UPD9; CHECK: rdefs left10; CHECK-NEXT: Latency : 411; CHECK: Successors:12; CHECK: Data13; CHECK-SAME: Latency=114 15@a = dso_local global double 0.0, align 416@b = dso_local global double 0.0, align 417@c = dso_local global double 0.0, align 418 19define dso_local i32 @bar(ptr %vptr, i32 %iv1, ptr %iptr) minsize {20 21 %vp2 = getelementptr double, ptr %vptr, i32 122 %vp3 = getelementptr double, ptr %vptr, i32 223 24 %v1 = load double, ptr %vptr, align 825 %v2 = load double, ptr %vp2, align 826 %v3 = load double, ptr %vp3, align 827 28 store double %v1, ptr @a, align 829 store double %v2, ptr @b, align 830 store double %v3, ptr @c, align 831 32 %ptr_after = getelementptr double, ptr @a, i32 333 34 %ptr_new_ival = ptrtoint ptr %ptr_after to i3235 %ptr_new = inttoptr i32 %ptr_new_ival to ptr36 37 store i32 %ptr_new_ival, ptr %iptr, align 838 39 %mul1 = mul i32 %ptr_new_ival, %iv140 41 ret i32 %mul142}43 44